1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
27 #include "psxcommon.h"
29 #include "psxcounters.h"
35 void (*Execute)(); /* executes up to a break */
36 void (*ExecuteBlock)(); /* executes up to a jump */
37 void (*Clear)(u32 Addr, u32 Size);
41 extern R3000Acpu *psxCpu;
42 extern R3000Acpu psxInt;
43 #if (defined(__x86_64__) || defined(__i386__) || defined(__sh__) || defined(__ppc__) || defined(__arm__)) && !defined(NOPSXREC)
44 extern R3000Acpu psxRec;
49 #if defined(__BIGENDIAN__)
50 struct { u8 h3, h2, h, l; } b;
51 struct { s8 h3, h2, h, l; } sb;
52 struct { u16 h, l; } w;
53 struct { s16 h, l; } sw;
55 struct { u8 l, h, h2, h3; } b;
56 struct { u16 l, h; } w;
57 struct { s8 l, h, h2, h3; } sb;
58 struct { s16 l, h; } sw;
64 u32 r0, at, v0, v1, a0, a1, a2, a3,
65 t0, t1, t2, t3, t4, t5, t6, t7,
66 s0, s1, s2, s3, s4, s5, s6, s7,
67 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
69 u32 r[34]; /* Lo, Hi in r[32] and r[33] */
75 u32 Index, Random, EntryLo0, EntryLo1,
76 Context, PageMask, Wired, Reserved0,
77 BadVAddr, Count, EntryHi, Compare,
78 Status, Cause, EPC, PRid,
79 Config, LLAddr, WatchLO, WatchHI,
80 XContext, Reserved1, Reserved2, Reserved3,
81 Reserved4, Reserved5, ECC, CacheErr,
82 TagLo, TagHi, ErrorEPC, Reserved6;
105 unsigned char r, g, b, c;
109 short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
114 SVector3D v0, v1, v2;
117 s32 ir0, ir1, ir2, ir3;
118 SVector2D sxy0, sxy1, sxy2, sxyp;
119 SVector2Dz sz0, sz1, sz2, sz3;
120 CBGR rgb0, rgb1, rgb2;
122 s32 mac0, mac1, mac2, mac3;
167 psxGPRRegs GPR; /* General Purpose Registers */
168 psxCP0Regs CP0; /* Coprocessor0 Registers */
169 psxCP2Data CP2D; /* Cop2 data registers */
170 psxCP2Ctrl CP2C; /* Cop2 control registers */
171 u32 pc; /* Program counter */
172 u32 code; /* The instruction */
175 struct { u32 sCycle, cycle; } intCycle[32];
178 extern psxRegisters psxRegs;
180 /* new_dynarec stuff */
181 extern u32 event_cycles[PSXINT_COUNT];
182 extern u32 next_interupt;
184 void new_dyna_save(void);
185 void new_dyna_restore(void);
187 #define new_dyna_set_event(e, c) { \
189 u32 abs_ = psxRegs.cycle + c_; \
190 s32 odi_ = next_interupt - psxRegs.cycle; \
191 event_cycles[e] = abs_; \
193 /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
194 next_interupt = abs_; \
198 #if defined(__BIGENDIAN__)
200 #define _i32(x) *(s32 *)&x
203 #define _i16(x) (((short *)&x)[1])
204 #define _u16(x) (((unsigned short *)&x)[1])
206 #define _i8(x) (((char *)&x)[3])
207 #define _u8(x) (((unsigned char *)&x)[3])
211 #define _i32(x) *(s32 *)&x
214 #define _i16(x) *(short *)&x
215 #define _u16(x) *(unsigned short *)&x
217 #define _i8(x) *(char *)&x
218 #define _u8(x) *(unsigned char *)&x
222 /**** R3000A Instruction Macros ****/
223 #define _PC_ psxRegs.pc // The next PC to be executed
225 #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
226 #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
227 #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
228 #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
229 #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
230 #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
231 #define _fIm_(code) ((u16)code) // The immediate part of the instruction register
232 #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
234 #define _fImm_(code) ((s16)code) // sign-extended immediate
235 #define _fImmU_(code) (code&0xffff) // zero-extended immediate
237 #define _Op_ _fOp_(psxRegs.code)
238 #define _Funct_ _fFunct_(psxRegs.code)
239 #define _Rd_ _fRd_(psxRegs.code)
240 #define _Rt_ _fRt_(psxRegs.code)
241 #define _Rs_ _fRs_(psxRegs.code)
242 #define _Sa_ _fSa_(psxRegs.code)
243 #define _Im_ _fIm_(psxRegs.code)
244 #define _Target_ _fTarget_(psxRegs.code)
246 #define _Imm_ _fImm_(psxRegs.code)
247 #define _ImmU_ _fImmU_(psxRegs.code)
249 #define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register
250 #define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register
251 #define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register
252 #define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register
253 #define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register
255 #define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register
256 #define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register
257 #define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register
258 #define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register
260 #define _rHi_ psxRegs.GPR.n.hi // The HI register
261 #define _rLo_ psxRegs.GPR.n.lo // The LO register
263 #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
264 #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
266 #define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
271 void psxException(u32 code, u32 bd);
272 void psxBranchTest();
273 void psxExecuteBios();
274 int psxTestLoadDelay(int reg, u32 tmp);
275 void psxDelayTest(int reg, u32 bpc);
276 void psxTestSWInts();