3 * Copyright (C) 2006 Exophase <exophase@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
22 // This table is configured for sequential access on system defaults
24 u32 waitstate_cycles_sequential[16][3] =
27 { 1, 1, 1 }, // Invalid
28 { 3, 3, 6 }, // EWRAM (default settings)
30 { 1, 1, 1 }, // IO Registers
31 { 1, 1, 2 }, // Palette RAM
34 { 3, 3, 6 }, // Gamepak (wait 0)
35 { 3, 3, 6 }, // Gamepak (wait 0)
36 { 5, 5, 9 }, // Gamepak (wait 1)
37 { 5, 5, 9 }, // Gamepak (wait 1)
38 { 9, 9, 17 }, // Gamepak (wait 2)
39 { 9, 9, 17 }, // Gamepak (wait 2)
42 // Different settings for gamepak ws0-2 sequential (2nd) access
44 u32 gamepak_waitstate_sequential[2][3][3] =
60 u16 palette_ram_converted[512];
61 u16 io_registers[1024 * 16];
62 u8 ewram[1024 * 256 * 2];
63 u8 iwram[1024 * 32 * 2];
64 u8 vram[1024 * 96 * 2];
66 u8 bios_rom[1024 * 32];
67 u32 bios_read_protect;
69 // Up to 128kb, store SRAM, flash ROM, or EEPROM here.
70 u8 gamepak_backup[1024 * 128];
72 // Keeps us knowing how much we have left.
76 dma_transfer_type dma[4];
78 u8 *memory_regions[16];
79 u32 memory_limits[16];
85 } gamepak_swap_entry_type;
87 u32 gamepak_ram_buffer_size;
88 u32 gamepak_ram_pages;
90 // Enough to map the gamepak RAM space.
91 gamepak_swap_entry_type *gamepak_memory_map;
93 // This is global so that it can be kept open for large ROMs to swap
94 // pages from, so there's no slowdown with opening and closing the file
98 file_tag_type gamepak_file_large = -1;
102 file_tag_type gamepak_file_large = NULL;
106 u32 direct_map_vram = 0;
108 // Writes to these respective locations should trigger an update
109 // so the related subsystem may react to it.
111 // If OAM is written to:
114 // If GBC audio is written to:
115 u32 gbc_sound_update = 0;
117 // If the GBC audio waveform is modified:
118 u32 gbc_sound_wave_update = 0;
120 // If the backup space is written (only update once this hits 0)
121 u32 backup_update = 0;
123 // Write out backup file this many cycles after the most recent
125 const u32 write_backup_delay = 10;
142 // Keep it 32KB until the upper 64KB is accessed, then make it 64KB.
144 backup_type_type backup_type = BACKUP_NONE;
145 sram_size_type sram_size = SRAM_SIZE_32KB;
153 FLASH_BANKSWITCH_MODE
162 flash_mode_type flash_mode = FLASH_BASE_MODE;
163 u32 flash_command_position = 0;
164 u8 *flash_bank_ptr = gamepak_backup;
166 flash_device_id_type flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
167 flash_manufacturer_id_type flash_manufacturer_id =
168 FLASH_MANUFACTURER_MACRONIX;
169 flash_size_type flash_size = FLASH_SIZE_64KB;
171 u8 read_backup(u32 address)
175 if(backup_type == BACKUP_NONE)
176 backup_type = BACKUP_SRAM;
178 if(backup_type == BACKUP_SRAM)
180 value = gamepak_backup[address];
184 if(flash_mode == FLASH_ID_MODE)
186 /* ID manufacturer type */
187 if(address == 0x0000)
188 value = flash_manufacturer_id;
192 if(address == 0x0001)
193 value = flash_device_id;
197 value = flash_bank_ptr[address];
203 #define read_backup8() \
204 value = read_backup(address & 0xFFFF) \
206 #define read_backup16() \
209 #define read_backup32() \
213 // EEPROM is 512 bytes by default; it is autodetecte as 8KB if
214 // 14bit address DMAs are made (this is done in the DMA handler).
226 EEPROM_READ_HEADER_MODE,
229 EEPROM_WRITE_ADDRESS_MODE,
230 EEPROM_ADDRESS_FOOTER_MODE,
231 EEPROM_WRITE_FOOTER_MODE
235 eeprom_size_type eeprom_size = EEPROM_512_BYTE;
236 eeprom_mode_type eeprom_mode = EEPROM_BASE_MODE;
237 u32 eeprom_address_length;
238 u32 eeprom_address = 0;
239 s32 eeprom_counter = 0;
243 void function_cc write_eeprom(u32 address, u32 value)
247 case EEPROM_BASE_MODE:
248 backup_type = BACKUP_EEPROM;
249 eeprom_buffer[0] |= (value & 0x01) << (1 - eeprom_counter);
251 if(eeprom_counter == 2)
253 if(eeprom_size == EEPROM_512_BYTE)
254 eeprom_address_length = 6;
256 eeprom_address_length = 14;
260 switch(eeprom_buffer[0] & 0x03)
263 eeprom_mode = EEPROM_WRITE_ADDRESS_MODE;
267 eeprom_mode = EEPROM_ADDRESS_MODE;
270 address16(eeprom_buffer, 0) = 0;
274 case EEPROM_ADDRESS_MODE:
275 case EEPROM_WRITE_ADDRESS_MODE:
276 eeprom_buffer[eeprom_counter / 8]
277 |= (value & 0x01) << (7 - (eeprom_counter % 8));
279 if(eeprom_counter == eeprom_address_length)
281 if(eeprom_size == EEPROM_512_BYTE)
284 (address16(eeprom_buffer, 0) >> 2) * 8;
288 eeprom_address = (((u32)eeprom_buffer[1] >> 2) |
289 ((u32)eeprom_buffer[0] << 6)) * 8;
292 address16(eeprom_buffer, 0) = 0;
295 if(eeprom_mode == EEPROM_ADDRESS_MODE)
297 eeprom_mode = EEPROM_ADDRESS_FOOTER_MODE;
301 eeprom_mode = EEPROM_WRITE_MODE;
302 memset(gamepak_backup + eeprom_address, 0, 8);
307 case EEPROM_WRITE_MODE:
308 gamepak_backup[eeprom_address + (eeprom_counter / 8)] |=
309 (value & 0x01) << (7 - (eeprom_counter % 8));
311 if(eeprom_counter == 64)
313 backup_update = write_backup_delay;
315 eeprom_mode = EEPROM_WRITE_FOOTER_MODE;
319 case EEPROM_ADDRESS_FOOTER_MODE:
320 case EEPROM_WRITE_FOOTER_MODE:
322 if(eeprom_mode == EEPROM_ADDRESS_FOOTER_MODE)
324 eeprom_mode = EEPROM_READ_HEADER_MODE;
328 eeprom_mode = EEPROM_BASE_MODE;
334 #define read_memory_gamepak(type) \
335 u32 gamepak_index = address >> 15; \
336 u8 *map = memory_map_read[gamepak_index]; \
339 map = load_gamepak_page(gamepak_index & 0x3FF); \
341 value = address##type(map, address & 0x7FFF) \
343 #define read_open8() \
344 if(!(reg[REG_CPSR] & 0x20)) \
345 value = read_memory8(reg[REG_PC] + 4 + (address & 0x03)); \
347 value = read_memory8(reg[REG_PC] + 2 + (address & 0x01)) \
349 #define read_open16() \
350 if(!(reg[REG_CPSR] & 0x20)) \
351 value = read_memory16(reg[REG_PC] + 4 + (address & 0x02)); \
353 value = read_memory16(reg[REG_PC] + 2) \
355 #define read_open32() \
356 if(!(reg[REG_CPSR] & 0x20)) \
358 value = read_memory32(reg[REG_PC] + 4); \
362 u32 current_instruction = read_memory16(reg[REG_PC] + 2); \
363 value = current_instruction | (current_instruction << 16); \
366 u32 function_cc read_eeprom()
372 case EEPROM_BASE_MODE:
376 case EEPROM_READ_MODE:
377 value = (gamepak_backup[eeprom_address + (eeprom_counter / 8)] >>
378 (7 - (eeprom_counter % 8))) & 0x01;
380 if(eeprom_counter == 64)
383 eeprom_mode = EEPROM_BASE_MODE;
387 case EEPROM_READ_HEADER_MODE:
390 if(eeprom_counter == 4)
392 eeprom_mode = EEPROM_READ_MODE;
406 #define read_memory(type) \
407 switch(address >> 24) \
411 if(reg[REG_PC] >= 0x4000) \
412 value = address##type(&bios_read_protect, address & 0x03); \
414 value = address##type(bios_rom, address & 0x3FFF); \
418 /* external work RAM */ \
419 address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
420 value = address##type(ewram, address); \
424 /* internal work RAM */ \
425 value = address##type(iwram, (address & 0x7FFF) + 0x8000); \
429 /* I/O registers */ \
430 value = address##type(io_registers, address & 0x3FF); \
435 value = address##type(palette_ram, address & 0x3FF); \
440 address &= 0x1FFFF; \
441 if(address > 0x18000) \
444 value = address##type(vram, address); \
449 value = address##type(oam_ram, address & 0x3FF); \
458 if((address & 0x1FFFFFF) >= gamepak_size) \
464 read_memory_gamepak(type); \
469 if((address & 0x1FFFFFF) < gamepak_size) \
471 read_memory_gamepak(type); \
475 value = read_eeprom(); \
482 read_backup##type(); \
490 #define trigger_dma(dma_number) \
493 if(dma[dma_number].start_type == DMA_INACTIVE) \
495 u32 start_type = (value >> 12) & 0x03; \
496 u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) & \
499 dma[dma_number].dma_channel = dma_number; \
500 dma[dma_number].source_address = \
501 address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF; \
502 dma[dma_number].dest_address = dest_address; \
503 dma[dma_number].source_direction = (value >> 7) & 0x03; \
504 dma[dma_number].repeat_type = (value >> 9) & 0x01; \
505 dma[dma_number].start_type = start_type; \
506 dma[dma_number].irq = (value >> 14) & 0x01; \
508 /* If it is sound FIFO DMA make sure the settings are a certain way */ \
509 if((dma_number >= 1) && (dma_number <= 2) && \
510 (start_type == DMA_START_SPECIAL)) \
512 dma[dma_number].length_type = DMA_32BIT; \
513 dma[dma_number].length = 4; \
514 dma[dma_number].dest_direction = DMA_FIXED; \
515 if(dest_address == 0x40000A4) \
516 dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B; \
518 dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A; \
523 address16(io_registers, (dma_number * 12) + 0xB8); \
525 if((dma_number == 3) && ((dest_address >> 24) == 0x0D) && \
526 ((length & 0x1F) == 17)) \
528 eeprom_size = EEPROM_8_KBYTE; \
536 if(dma_number == 3) \
542 dma[dma_number].length = length; \
543 dma[dma_number].length_type = (value >> 10) & 0x01; \
544 dma[dma_number].dest_direction = (value >> 5) & 0x03; \
547 address16(io_registers, (dma_number * 12) + 0xBA) = value; \
548 if(start_type == DMA_START_IMMEDIATELY) \
549 return dma_transfer(dma + dma_number); \
554 dma[dma_number].start_type = DMA_INACTIVE; \
555 dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND; \
556 address16(io_registers, (dma_number * 12) + 0xBA) = value; \
560 #define access_register8_high(address) \
561 value = (value << 8) | (address8(io_registers, address)) \
563 #define access_register8_low(address) \
564 value = ((address8(io_registers, address + 1)) << 8) | value \
566 #define access_register16_high(address) \
567 value = (value << 16) | (address16(io_registers, address)) \
569 #define access_register16_low(address) \
570 value = ((address16(io_registers, address + 2)) << 16) | value \
572 cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
578 u32 dispcnt = io_registers[REG_DISPCNT];
580 if((value & 0x07) != (dispcnt & 0x07))
583 address8(io_registers, 0x00) = value;
587 // DISPSTAT (lower byte)
589 address8(io_registers, 0x04) =
590 (address8(io_registers, 0x04) & 0x07) | (value & ~0x07);
600 access_register8_low(0x28);
601 access_register16_low(0x28);
602 affine_reference_x[0] = (s32)(value << 4) >> 4;
603 address32(io_registers, 0x28) = value;
607 access_register8_high(0x28);
608 access_register16_low(0x28);
609 affine_reference_x[0] = (s32)(value << 4) >> 4;
610 address32(io_registers, 0x28) = value;
614 access_register8_low(0x2A);
615 access_register16_high(0x28);
616 affine_reference_x[0] = (s32)(value << 4) >> 4;
617 address32(io_registers, 0x28) = value;
621 access_register8_high(0x2A);
622 access_register16_high(0x28);
623 affine_reference_x[0] = (s32)(value << 4) >> 4;
624 address32(io_registers, 0x28) = value;
629 access_register8_low(0x2C);
630 access_register16_low(0x2C);
631 affine_reference_y[0] = (s32)(value << 4) >> 4;
632 address32(io_registers, 0x2C) = value;
636 access_register8_high(0x2C);
637 access_register16_low(0x2C);
638 affine_reference_y[0] = (s32)(value << 4) >> 4;
639 address32(io_registers, 0x2C) = value;
643 access_register8_low(0x2E);
644 access_register16_high(0x2C);
645 affine_reference_y[0] = (s32)(value << 4) >> 4;
646 address32(io_registers, 0x2C) = value;
650 access_register8_high(0x2E);
651 access_register16_high(0x2C);
652 affine_reference_y[0] = (s32)(value << 4) >> 4;
653 address32(io_registers, 0x2C) = value;
658 access_register8_low(0x38);
659 access_register16_low(0x38);
660 affine_reference_x[1] = (s32)(value << 4) >> 4;
661 address32(io_registers, 0x38) = value;
665 access_register8_high(0x38);
666 access_register16_low(0x38);
667 affine_reference_x[1] = (s32)(value << 4) >> 4;
668 address32(io_registers, 0x38) = value;
672 access_register8_low(0x3A);
673 access_register16_high(0x38);
674 affine_reference_x[1] = (s32)(value << 4) >> 4;
675 address32(io_registers, 0x38) = value;
679 access_register8_high(0x3A);
680 access_register16_high(0x38);
681 affine_reference_x[1] = (s32)(value << 4) >> 4;
682 address32(io_registers, 0x38) = value;
687 access_register8_low(0x3C);
688 access_register16_low(0x3C);
689 affine_reference_y[1] = (s32)(value << 4) >> 4;
690 address32(io_registers, 0x3C) = value;
694 access_register8_high(0x3C);
695 access_register16_low(0x3C);
696 affine_reference_y[1] = (s32)(value << 4) >> 4;
697 address32(io_registers, 0x3C) = value;
701 access_register8_low(0x3E);
702 access_register16_high(0x3C);
703 affine_reference_y[1] = (s32)(value << 4) >> 4;
704 address32(io_registers, 0x3C) = value;
708 access_register8_high(0x3E);
709 access_register16_high(0x3C);
710 affine_reference_y[1] = (s32)(value << 4) >> 4;
711 address32(io_registers, 0x3C) = value;
714 // Sound 1 control sweep
716 access_register8_low(0x60);
717 gbc_sound_tone_control_sweep();
721 access_register8_low(0x60);
722 gbc_sound_tone_control_sweep();
725 // Sound 1 control duty/length/envelope
727 access_register8_low(0x62);
728 gbc_sound_tone_control_low(0, 0x62);
732 access_register8_high(0x62);
733 gbc_sound_tone_control_low(0, 0x62);
736 // Sound 1 control frequency
738 access_register8_low(0x64);
739 gbc_sound_tone_control_high(0, 0x64);
743 access_register8_high(0x64);
744 gbc_sound_tone_control_high(0, 0x64);
747 // Sound 2 control duty/length/envelope
749 access_register8_low(0x68);
750 gbc_sound_tone_control_low(1, 0x68);
754 access_register8_high(0x68);
755 gbc_sound_tone_control_low(1, 0x68);
758 // Sound 2 control frequency
760 access_register8_low(0x6C);
761 gbc_sound_tone_control_high(1, 0x6C);
765 access_register8_high(0x6C);
766 gbc_sound_tone_control_high(1, 0x6C);
769 // Sound 3 control wave
771 access_register8_low(0x70);
772 gbc_sound_wave_control();
776 access_register8_high(0x70);
777 gbc_sound_wave_control();
780 // Sound 3 control length/volume
782 access_register8_low(0x72);
783 gbc_sound_tone_control_low_wave();
787 access_register8_high(0x72);
788 gbc_sound_tone_control_low_wave();
791 // Sound 3 control frequency
793 access_register8_low(0x74);
794 gbc_sound_tone_control_high_wave();
798 access_register8_high(0x74);
799 gbc_sound_tone_control_high_wave();
802 // Sound 4 control length/envelope
804 access_register8_low(0x78);
805 gbc_sound_tone_control_low(3, 0x78);
809 access_register8_high(0x78);
810 gbc_sound_tone_control_low(3, 0x78);
813 // Sound 4 control frequency
815 access_register8_low(0x7C);
816 gbc_sound_noise_control();
820 access_register8_high(0x7C);
821 gbc_sound_noise_control();
826 access_register8_low(0x80);
831 access_register8_high(0x80);
837 access_register8_low(0x82);
842 access_register8_high(0x82);
853 gbc_sound_wave_update = 1;
854 address8(io_registers, address) = value;
859 sound_timer_queue8(0, value);
864 sound_timer_queue8(1, value);
867 // DMA control (trigger byte)
869 access_register8_low(0xBA);
874 access_register8_low(0xC6);
879 access_register8_low(0xD2);
884 access_register8_low(0xDE);
890 access_register8_low(0x100);
895 access_register8_high(0x100);
900 access_register8_low(0x104);
905 access_register8_high(0x104);
910 access_register8_low(0x108);
915 access_register8_high(0x108);
920 access_register8_low(0x10C);
925 access_register8_high(0x10C);
929 // Timer control (trigger byte)
931 access_register8_low(0x102);
936 access_register8_low(0x106);
941 access_register8_low(0x10A);
946 access_register8_low(0x10E);
952 address8(io_registers, 0x202) &= ~value;
956 address8(io_registers, 0x203) &= ~value;
961 if((value & 0x01) == 0)
962 reg[CPU_HALT_STATE] = CPU_HALT;
964 reg[CPU_HALT_STATE] = CPU_STOP;
966 return CPU_ALERT_HALT;
970 address8(io_registers, address) = value;
974 return CPU_ALERT_NONE;
977 cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
983 u32 dispcnt = io_registers[REG_DISPCNT];
984 if((value & 0x07) != (dispcnt & 0x07))
987 address16(io_registers, 0x00) = value;
993 address16(io_registers, 0x04) =
994 (address16(io_registers, 0x04) & 0x07) | (value & ~0x07);
1003 access_register16_low(0x28);
1004 affine_reference_x[0] = (s32)(value << 4) >> 4;
1005 address32(io_registers, 0x28) = value;
1009 access_register16_high(0x28);
1010 affine_reference_x[0] = (s32)(value << 4) >> 4;
1011 address32(io_registers, 0x28) = value;
1016 access_register16_low(0x2C);
1017 affine_reference_y[0] = (s32)(value << 4) >> 4;
1018 address32(io_registers, 0x2C) = value;
1022 access_register16_high(0x2C);
1023 affine_reference_y[0] = (s32)(value << 4) >> 4;
1024 address32(io_registers, 0x2C) = value;
1030 access_register16_low(0x38);
1031 affine_reference_x[1] = (s32)(value << 4) >> 4;
1032 address32(io_registers, 0x38) = value;
1036 access_register16_high(0x38);
1037 affine_reference_x[1] = (s32)(value << 4) >> 4;
1038 address32(io_registers, 0x38) = value;
1043 access_register16_low(0x3C);
1044 affine_reference_y[1] = (s32)(value << 4) >> 4;
1045 address32(io_registers, 0x3C) = value;
1049 access_register16_high(0x3C);
1050 affine_reference_y[1] = (s32)(value << 4) >> 4;
1051 address32(io_registers, 0x3C) = value;
1054 // Sound 1 control sweep
1056 gbc_sound_tone_control_sweep();
1059 // Sound 1 control duty/length/envelope
1061 gbc_sound_tone_control_low(0, 0x62);
1064 // Sound 1 control frequency
1066 gbc_sound_tone_control_high(0, 0x64);
1069 // Sound 2 control duty/length/envelope
1071 gbc_sound_tone_control_low(1, 0x68);
1074 // Sound 2 control frequency
1076 gbc_sound_tone_control_high(1, 0x6C);
1079 // Sound 3 control wave
1081 gbc_sound_wave_control();
1084 // Sound 3 control length/volume
1086 gbc_sound_tone_control_low_wave();
1089 // Sound 3 control frequency
1091 gbc_sound_tone_control_high_wave();
1094 // Sound 4 control length/envelope
1096 gbc_sound_tone_control_low(3, 0x78);
1099 // Sound 4 control frequency
1101 gbc_sound_noise_control();
1106 gbc_trigger_sound();
1121 gbc_sound_wave_update = 1;
1122 address16(io_registers, address) = value;
1127 sound_timer_queue16(0, value);
1132 sound_timer_queue16(1, value);
1192 address16(io_registers, 0x202) &= ~value;
1201 if(((value >> 8) & 0x01) == 0)
1202 reg[CPU_HALT_STATE] = CPU_HALT;
1204 reg[CPU_HALT_STATE] = CPU_STOP;
1206 return CPU_ALERT_HALT;
1209 address16(io_registers, address) = value;
1213 return CPU_ALERT_NONE;
1217 cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
1223 affine_reference_x[0] = (s32)(value << 4) >> 4;
1224 address32(io_registers, 0x28) = value;
1229 affine_reference_y[0] = (s32)(value << 4) >> 4;
1230 address32(io_registers, 0x2C) = value;
1235 affine_reference_x[1] = (s32)(value << 4) >> 4;
1236 address32(io_registers, 0x38) = value;
1241 affine_reference_y[1] = (s32)(value << 4) >> 4;
1242 address32(io_registers, 0x3C) = value;
1247 sound_timer_queue32(0, value);
1252 sound_timer_queue32(1, value);
1257 cpu_alert_type alert_low =
1258 write_io_register16(address, value & 0xFFFF);
1260 cpu_alert_type alert_high =
1261 write_io_register16(address + 2, value >> 16);
1270 return CPU_ALERT_NONE;
1273 #define write_palette8(address, value) \
1275 #define write_palette16(address, value) \
1277 u32 palette_address = address; \
1278 address16(palette_ram, palette_address) = value; \
1279 convert_palette(value); \
1280 address16(palette_ram_converted, palette_address) = value; \
1283 #define write_palette32(address, value) \
1285 u32 palette_address = address; \
1286 u32 value_high = value >> 16; \
1287 u32 value_low = value & 0xFFFF; \
1288 address32(palette_ram, palette_address) = value; \
1289 convert_palette(value_high); \
1290 convert_palette(value_low); \
1291 value = (value_high << 16) | value_low; \
1292 address32(palette_ram_converted, palette_address) = value; \
1296 void function_cc write_backup(u32 address, u32 value)
1300 if(backup_type == BACKUP_NONE)
1301 backup_type = BACKUP_SRAM;
1304 // gamepak SRAM or Flash ROM
1305 if((address == 0x5555) && (flash_mode != FLASH_WRITE_MODE))
1307 if((flash_command_position == 0) && (value == 0xAA))
1309 backup_type = BACKUP_FLASH;
1310 flash_command_position = 1;
1313 if(flash_command_position == 2)
1318 // Enter ID mode, this also tells the emulator that we're using
1321 if(flash_mode == FLASH_BASE_MODE)
1322 flash_mode = FLASH_ID_MODE;
1328 if(flash_mode == FLASH_BASE_MODE)
1329 flash_mode = FLASH_ERASE_MODE;
1333 // Terminate ID mode
1334 if(flash_mode == FLASH_ID_MODE)
1335 flash_mode = FLASH_BASE_MODE;
1340 if(flash_mode == FLASH_BASE_MODE)
1341 flash_mode = FLASH_WRITE_MODE;
1346 // Here the chip is now officially 128KB.
1347 flash_size = FLASH_SIZE_128KB;
1348 if(flash_mode == FLASH_BASE_MODE)
1349 flash_mode = FLASH_BANKSWITCH_MODE;
1354 if(flash_mode == FLASH_ERASE_MODE)
1356 if(flash_size == FLASH_SIZE_64KB)
1357 memset(gamepak_backup, 0xFF, 1024 * 64);
1359 memset(gamepak_backup, 0xFF, 1024 * 128);
1360 backup_update = write_backup_delay;
1361 flash_mode = FLASH_BASE_MODE;
1368 flash_command_position = 0;
1370 if(backup_type == BACKUP_SRAM)
1371 gamepak_backup[0x5555] = value;
1375 if((address == 0x2AAA) && (value == 0x55) &&
1376 (flash_command_position == 1))
1378 flash_command_position = 2;
1382 if((flash_command_position == 2) &&
1383 (flash_mode == FLASH_ERASE_MODE) && (value == 0x30))
1386 memset(flash_bank_ptr + (address & 0xF000), 0xFF, 1024 * 4);
1387 backup_update = write_backup_delay;
1388 flash_mode = FLASH_BASE_MODE;
1389 flash_command_position = 0;
1393 if((flash_command_position == 0) &&
1394 (flash_mode == FLASH_BANKSWITCH_MODE) && (address == 0x0000) &&
1395 (flash_size == FLASH_SIZE_128KB))
1397 flash_bank_ptr = gamepak_backup + ((value & 0x01) * (1024 * 64));
1398 flash_mode = FLASH_BASE_MODE;
1402 if((flash_command_position == 0) && (flash_mode == FLASH_WRITE_MODE))
1404 // Write value to flash ROM
1405 backup_update = write_backup_delay;
1406 flash_bank_ptr[address] = value;
1407 flash_mode = FLASH_BASE_MODE;
1411 if(backup_type == BACKUP_SRAM)
1413 // Write value to SRAM
1414 backup_update = write_backup_delay;
1415 // Hit 64KB territory?
1416 if(address >= 0x8000)
1417 sram_size = SRAM_SIZE_64KB;
1418 gamepak_backup[address] = value;
1423 #define write_backup8() \
1424 write_backup(address & 0xFFFF, value) \
1426 #define write_backup16() \
1428 #define write_backup32() \
1430 #define write_vram8() \
1432 address16(vram, address) = ((value << 8) | value) \
1434 #define write_vram16() \
1435 address16(vram, address) = value \
1437 #define write_vram32() \
1438 address32(vram, address) = value \
1440 // RTC code derived from VBA's (due to lack of any real publically available
1441 // documentation...)
1454 RTC_COMMAND_RESET = 0x60,
1455 RTC_COMMAND_WRITE_STATUS = 0x62,
1456 RTC_COMMAND_READ_STATUS = 0x63,
1457 RTC_COMMAND_OUTPUT_TIME_FULL = 0x65,
1458 RTC_COMMAND_OUTPUT_TIME = 0x67
1464 RTC_WRITE_TIME_FULL,
1466 } rtc_write_mode_type;
1468 rtc_state_type rtc_state = RTC_DISABLED;
1469 rtc_write_mode_type rtc_write_mode;
1470 u8 rtc_registers[3];
1473 u32 rtc_status = 0x40;
1477 u32 encode_bcd(u8 value)
1479 return ((value / 10) << 4) | (value % 10);
1482 #define write_rtc_register(index, _value) \
1483 update_address = 0x80000C4 + (index * 2); \
1484 rtc_registers[index] = _value; \
1485 rtc_page_index = update_address >> 15; \
1486 map = memory_map_read[rtc_page_index]; \
1489 map = load_gamepak_page(rtc_page_index & 0x3FF); \
1491 address16(map, update_address & 0x7FFF) = _value \
1493 void function_cc write_rtc(u32 address, u32 value)
1504 // Bit 0: SCHK, perform action
1505 // Bit 1: IO, input/output command data
1506 // Bit 2: CS, select input/output? If high make I/O write only
1508 if(rtc_state == RTC_DISABLED)
1509 rtc_state = RTC_IDLE;
1510 if(!(rtc_registers[0] & 0x04))
1511 value = (rtc_registers[0] & 0x02) | (value & ~0x02);
1512 if(rtc_registers[2] & 0x01)
1514 // To begin writing a command 1, 5 must be written to the command
1516 if((rtc_state == RTC_IDLE) && (rtc_registers[0] == 0x01) &&
1519 // We're now ready to begin receiving a command.
1520 write_rtc_register(0, value);
1521 rtc_state = RTC_COMMAND;
1527 write_rtc_register(0, value);
1530 // Accumulate RTC command by receiving the next bit, and if we
1531 // have accumulated enough bits to form a complete command
1534 if(rtc_registers[0] & 0x01)
1536 rtc_command |= ((value & 0x02) >> 1) << rtc_bit_count;
1540 // Have we received a full RTC command? If so execute it.
1541 if(rtc_bit_count < 0)
1546 case RTC_COMMAND_RESET:
1547 rtc_state = RTC_IDLE;
1548 memset(rtc_registers, 0, sizeof(rtc_registers));
1551 // Sets status of RTC
1552 case RTC_COMMAND_WRITE_STATUS:
1553 rtc_state = RTC_INPUT_DATA;
1555 rtc_write_mode = RTC_WRITE_STATUS;
1558 // Outputs current status of RTC
1559 case RTC_COMMAND_READ_STATUS:
1560 rtc_state = RTC_OUTPUT_DATA;
1562 rtc_data[0] = rtc_status;
1565 // Actually outputs the time, all of it
1566 case RTC_COMMAND_OUTPUT_TIME_FULL:
1568 struct tm *current_time;
1569 time_t current_time_flat;
1572 time(¤t_time_flat);
1573 current_time = localtime(¤t_time_flat);
1575 day_of_week = current_time->tm_wday;
1576 if(day_of_week == 0)
1581 rtc_state = RTC_OUTPUT_DATA;
1583 rtc_data[0] = encode_bcd(current_time->tm_year % 100);
1584 rtc_data[1] = encode_bcd(current_time->tm_mon + 1);
1585 rtc_data[2] = encode_bcd(current_time->tm_mday);
1586 rtc_data[3] = encode_bcd(day_of_week);
1587 rtc_data[4] = encode_bcd(current_time->tm_hour);
1588 rtc_data[5] = encode_bcd(current_time->tm_min);
1589 rtc_data[6] = encode_bcd(current_time->tm_sec);
1594 // Only outputs the current time of day.
1595 case RTC_COMMAND_OUTPUT_TIME:
1597 struct tm *current_time;
1598 time_t current_time_flat;
1600 time(¤t_time_flat);
1601 current_time = localtime(¤t_time_flat);
1603 rtc_state = RTC_OUTPUT_DATA;
1605 rtc_data[0] = encode_bcd(current_time->tm_hour);
1606 rtc_data[1] = encode_bcd(current_time->tm_min);
1607 rtc_data[2] = encode_bcd(current_time->tm_sec);
1615 // Receive parameters from the game as input to the RTC
1616 // for a given command. Read one bit at a time.
1617 case RTC_INPUT_DATA:
1618 // Bit 1 of parameter A must be high for input
1619 if(rtc_registers[1] & 0x02)
1621 // Read next bit for input
1624 rtc_data[rtc_bit_count >> 3] |=
1625 ((value & 0x01) << (7 - (rtc_bit_count & 0x07)));
1631 if(rtc_bit_count == (rtc_data_bytes * 8))
1633 rtc_state = RTC_IDLE;
1634 switch(rtc_write_mode)
1636 case RTC_WRITE_STATUS:
1637 rtc_status = rtc_data[0];
1645 case RTC_OUTPUT_DATA:
1646 // Bit 1 of parameter A must be low for output
1647 if(!(rtc_registers[1] & 0x02))
1649 // Write next bit to output, on bit 1 of parameter B
1652 u8 current_output_byte = rtc_registers[2];
1654 current_output_byte =
1655 (current_output_byte & ~0x02) |
1656 (((rtc_data[rtc_bit_count >> 3] >>
1657 (rtc_bit_count & 0x07)) & 0x01) << 1);
1659 write_rtc_register(0, current_output_byte);
1666 if(rtc_bit_count == (rtc_data_bytes * 8))
1668 rtc_state = RTC_IDLE;
1669 memset(rtc_registers, 0, sizeof(rtc_registers));
1679 write_rtc_register(2, value);
1683 // Write parameter A
1685 write_rtc_register(1, value);
1688 // Write parameter B
1690 write_rtc_register(2, value);
1695 #define write_rtc8() \
1697 #define write_rtc16() \
1698 write_rtc(address & 0xFF, value) \
1700 #define write_rtc32() \
1702 #define write_memory(type) \
1703 switch(address >> 24) \
1706 /* external work RAM */ \
1707 address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
1708 address##type(ewram, address) = value; \
1712 /* internal work RAM */ \
1713 address##type(iwram, (address & 0x7FFF) + 0x8000) = value; \
1717 /* I/O registers */ \
1718 return write_io_register##type(address & 0x3FF, value); \
1722 write_palette##type(address & 0x3FF, value); \
1727 address &= 0x1FFFF; \
1728 if(address >= 0x18000) \
1729 address -= 0x8000; \
1731 write_vram##type(); \
1737 address##type(oam_ram, address & 0x3FF) = value; \
1741 /* gamepak ROM or RTC */ \
1742 write_rtc##type(); \
1745 case 0x09 ... 0x0C: \
1746 /* gamepak ROM space */ \
1750 write_eeprom(address, value); \
1754 write_backup##type(); \
1758 u8 function_cc read_memory8(u32 address)
1765 u16 function_cc read_memory16_signed(u32 address)
1771 return (s8)read_memory8(address);
1781 // unaligned reads are actually 32bit
1783 u32 function_cc read_memory16(u32 address)
1791 ror(value, value, 8);
1802 u32 function_cc read_memory32(u32 address)
1807 u32 rotate = (address & 0x03) * 8;
1810 ror(value, value, rotate);
1820 cpu_alert_type function_cc write_memory8(u32 address, u8 value)
1823 return CPU_ALERT_NONE;
1826 cpu_alert_type function_cc write_memory16(u32 address, u16 value)
1829 return CPU_ALERT_NONE;
1832 cpu_alert_type function_cc write_memory32(u32 address, u32 value)
1835 return CPU_ALERT_NONE;
1838 char backup_filename[512];
1840 u32 load_backup(char *name)
1842 file_open(backup_file, name, read);
1844 if(file_check_valid(backup_file))
1846 u32 backup_size = file_length(name, backup_file);
1848 file_read(backup_file, gamepak_backup, backup_size);
1850 file_close(backup_file);
1852 // The size might give away what kind of backup it is.
1856 backup_type = BACKUP_EEPROM;
1857 eeprom_size = EEPROM_512_BYTE;
1861 backup_type = BACKUP_EEPROM;
1862 eeprom_size = EEPROM_8_KBYTE;
1866 backup_type = BACKUP_SRAM;
1867 sram_size = SRAM_SIZE_32KB;
1870 // Could be either flash or SRAM, go with flash
1872 backup_type = BACKUP_FLASH;
1873 sram_size = FLASH_SIZE_64KB;
1877 backup_type = BACKUP_FLASH;
1878 flash_size = FLASH_SIZE_128KB;
1885 backup_type = BACKUP_NONE;
1886 memset(gamepak_backup, 0xFF, 1024 * 128);
1892 u32 save_backup(char *name)
1894 if(backup_type != BACKUP_NONE)
1896 file_open(backup_file, name, write);
1898 if(file_check_valid(backup_file))
1905 if(sram_size == SRAM_SIZE_32KB)
1906 backup_size = 0x8000;
1908 backup_size = 0x10000;
1912 if(flash_size == FLASH_SIZE_64KB)
1913 backup_size = 0x10000;
1915 backup_size = 0x20000;
1919 if(eeprom_size == EEPROM_512_BYTE)
1920 backup_size = 0x200;
1922 backup_size = 0x2000;
1926 file_write(backup_file, gamepak_backup, backup_size);
1928 file_close(backup_file);
1936 void update_backup()
1938 if(backup_update != (write_backup_delay + 1))
1941 if(backup_update == 0)
1943 save_backup(backup_filename);
1944 backup_update = write_backup_delay + 1;
1948 void update_backup_force()
1950 save_backup(backup_filename);
1953 #define CONFIG_FILENAME "game_config.txt"
1955 u8 *skip_spaces(u8 *line_ptr)
1957 while(*line_ptr == ' ')
1963 s32 parse_config_line(u8 *current_line, u8 *current_variable, u8 *current_value)
1965 u8 *line_ptr = current_line;
1968 if((current_line[0] == 0) || (current_line[0] == '#'))
1971 line_ptr_new = strchr(line_ptr, ' ');
1972 if(line_ptr_new == NULL)
1976 strcpy(current_variable, line_ptr);
1977 line_ptr_new = skip_spaces(line_ptr_new + 1);
1979 if(*line_ptr_new != '=')
1982 line_ptr_new = skip_spaces(line_ptr_new + 1);
1983 strcpy(current_value, line_ptr_new);
1984 line_ptr_new = current_value + strlen(current_value) - 1;
1985 if(*line_ptr_new == '\n')
1991 if(*line_ptr_new == '\r')
1997 s32 load_game_config(u8 *gamepak_title, u8 *gamepak_code, u8 *gamepak_maker)
1999 u8 current_line[256];
2000 u8 current_variable[256];
2001 u8 current_value[256];
2002 u8 config_path[512];
2007 idle_loop_target_pc = 0xFFFFFFFF;
2008 iwram_stack_optimize = 1;
2009 bios_rom[0x39] = 0x00;
2010 bios_rom[0x2C] = 0x00;
2011 translation_gate_targets = 0;
2012 flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
2014 #if (defined(PSP_BUILD) || defined(ARM_ARCH)) && !defined(_WIN32_WCE)
2015 sprintf(config_path, "%s/%s", main_path, CONFIG_FILENAME);
2017 sprintf(config_path, "%s\\%s", main_path, CONFIG_FILENAME);
2020 config_file = fopen(config_path, "rb");
2024 while(fgets(current_line, 256, config_file))
2026 if(parse_config_line(current_line, current_variable, current_value)
2029 if(strcmp(current_variable, "game_name") ||
2030 strcmp(current_value, gamepak_title))
2033 if(!fgets(current_line, 256, config_file) ||
2034 (parse_config_line(current_line, current_variable,
2035 current_value) == -1) ||
2036 strcmp(current_variable, "game_code") ||
2037 strcmp(current_value, gamepak_code))
2040 if(!fgets(current_line, 256, config_file) ||
2041 (parse_config_line(current_line, current_variable,
2042 current_value) == -1) ||
2043 strcmp(current_variable, "vender_code") ||
2044 strcmp(current_value, gamepak_maker))
2047 while(fgets(current_line, 256, config_file))
2049 if(parse_config_line(current_line, current_variable, current_value)
2052 if(!strcmp(current_variable, "game_name"))
2054 fclose(config_file);
2058 if(!strcmp(current_variable, "idle_loop_eliminate_target"))
2059 idle_loop_target_pc = strtol(current_value, NULL, 16);
2061 if(!strcmp(current_variable, "translation_gate_target"))
2063 if(translation_gate_targets < MAX_TRANSLATION_GATES)
2065 translation_gate_target_pc[translation_gate_targets] =
2066 strtol(current_value, NULL, 16);
2067 translation_gate_targets++;
2071 if(!strcmp(current_variable, "iwram_stack_optimize") &&
2072 !strcmp(current_value, "no"))
2074 iwram_stack_optimize = 0;
2077 if(!strcmp(current_variable, "flash_rom_type") &&
2078 !strcmp(current_value, "128KB"))
2080 flash_device_id = FLASH_DEVICE_MACRONIX_128KB;
2083 if(!strcmp(current_variable, "bios_rom_hack_39") &&
2084 !strcmp(current_value, "yes"))
2086 bios_rom[0x39] = 0xC0;
2089 if(!strcmp(current_variable, "bios_rom_hack_2C") &&
2090 !strcmp(current_value, "yes"))
2092 bios_rom[0x2C] = 0x02;
2097 fclose(config_file);
2102 fclose(config_file);
2108 s32 load_gamepak_raw(char *name)
2110 file_open(gamepak_file, name, read);
2112 if(file_check_valid(gamepak_file))
2114 u32 file_size = file_length(name, gamepak_file);
2116 // First, close the last one if it was open, we won't
2117 // be needing it anymore.
2118 if(file_check_valid(gamepak_file_large))
2119 file_close(gamepak_file_large);
2121 // If it's a big file size keep it, don't close it, we'll
2122 // probably want to load from it more later.
2123 if(file_size <= gamepak_ram_buffer_size)
2125 file_read(gamepak_file, gamepak_rom, file_size);
2127 file_close(gamepak_file);
2130 gamepak_file_large = -1;
2132 gamepak_file_large = NULL;
2137 // Read in just enough for the header
2138 file_read(gamepak_file, gamepak_rom, 0x100);
2139 gamepak_file_large = gamepak_file;
2148 u8 gamepak_title[13];
2150 u8 gamepak_maker[3];
2151 u8 gamepak_filename[512];
2153 u32 load_gamepak(char *name)
2155 char *dot_position = strrchr(name, '.');
2157 u8 cheats_filename[256];
2160 file_size = wiz_load_gamepak(name);
2162 if(!strcmp(dot_position, ".zip"))
2163 file_size = load_file_zip(name);
2165 file_size = load_gamepak_raw(name);
2168 // A dumb April fool's joke was here once :o
2172 gamepak_size = (file_size + 0x7FFF) & ~0x7FFF;
2174 strcpy(backup_filename, name);
2175 strncpy(gamepak_filename, name, 512);
2176 change_ext(gamepak_filename, backup_filename, ".sav");
2178 load_backup(backup_filename);
2180 memcpy(gamepak_title, gamepak_rom + 0xA0, 12);
2181 memcpy(gamepak_code, gamepak_rom + 0xAC, 4);
2182 memcpy(gamepak_maker, gamepak_rom + 0xB0, 2);
2183 gamepak_title[12] = 0;
2184 gamepak_code[4] = 0;
2185 gamepak_maker[2] = 0;
2187 load_game_config(gamepak_title, gamepak_code, gamepak_maker);
2188 load_game_config_file();
2190 change_ext(gamepak_filename, cheats_filename, ".cht");
2191 add_cheats(cheats_filename);
2199 s32 load_bios(char *name)
2201 file_open(bios_file, name, read);
2203 if(file_check_valid(bios_file))
2205 file_read(bios_file, bios_rom, 0x4000);
2207 // This is a hack to get Zelda working, because emulating
2208 // the proper memory read behavior here is much too expensive.
2209 file_close(bios_file);
2216 // DMA memory regions can be one of the following:
2217 // IWRAM - 32kb offset from the contiguous iwram region.
2218 // EWRAM - like segmented but with self modifying code check.
2219 // VRAM - 96kb offset from the contiguous vram region, should take care
2220 // Palette RAM - Converts palette entries when written to.
2221 // OAM RAM - Sets OAM modified flag to true.
2222 // I/O registers - Uses the I/O register function.
2223 // of mirroring properly.
2224 // Segmented RAM/ROM - a region >= 32kb, the translated address has to
2225 // be reloaded if it wraps around the limit (cartride ROM)
2226 // Ext - should be handled by the memory read/write function.
2228 // The following map determines the region of each (assumes DMA access
2229 // is not done out of bounds)
2236 DMA_REGION_PALETTE_RAM,
2245 dma_region_type dma_region_map[16] =
2247 DMA_REGION_BIOS, // 0x00 - BIOS
2248 DMA_REGION_NULL, // 0x01 - Nothing
2249 DMA_REGION_EWRAM, // 0x02 - EWRAM
2250 DMA_REGION_IWRAM, // 0x03 - IWRAM
2251 DMA_REGION_IO, // 0x04 - I/O registers
2252 DMA_REGION_PALETTE_RAM, // 0x05 - palette RAM
2253 DMA_REGION_VRAM, // 0x06 - VRAM
2254 DMA_REGION_OAM_RAM, // 0x07 - OAM RAM
2255 DMA_REGION_GAMEPAK, // 0x08 - gamepak ROM
2256 DMA_REGION_GAMEPAK, // 0x09 - gamepak ROM
2257 DMA_REGION_GAMEPAK, // 0x0A - gamepak ROM
2258 DMA_REGION_GAMEPAK, // 0x0B - gamepak ROM
2259 DMA_REGION_GAMEPAK, // 0x0C - gamepak ROM
2260 DMA_REGION_EXT, // 0x0D - EEPROM
2261 DMA_REGION_EXT, // 0x0E - gamepak SRAM/flash ROM
2262 DMA_REGION_EXT // 0x0F - gamepak SRAM/flash ROM
2265 #define dma_adjust_ptr_inc(ptr, size) \
2268 #define dma_adjust_ptr_dec(ptr, size) \
2271 #define dma_adjust_ptr_fix(ptr, size) \
2273 #define dma_adjust_ptr_writeback() \
2274 dma->dest_address = dest_ptr \
2276 #define dma_adjust_ptr_reload() \
2278 #define dma_print(src_op, dest_op, transfer_size, wb) \
2279 printf("dma from %x (%s) to %x (%s) for %x (%s) (%s) (%d) (pc %x)\n", \
2280 src_ptr, #src_op, dest_ptr, #dest_op, length, #transfer_size, #wb, \
2281 dma->irq, reg[15]); \
2283 #define dma_smc_vars_src() \
2285 #define dma_smc_vars_dest() \
2286 u32 smc_trigger = 0 \
2288 #define dma_vars_iwram(type) \
2289 dma_smc_vars_##type() \
2291 #define dma_vars_vram(type) \
2293 #define dma_vars_palette_ram(type) \
2295 #define dma_oam_ram_src() \
2297 #define dma_oam_ram_dest() \
2300 #define dma_vars_oam_ram(type) \
2301 dma_oam_ram_##type() \
2303 #define dma_vars_io(type) \
2305 #define dma_segmented_load_src() \
2306 memory_map_read[src_current_region] \
2308 #define dma_segmented_load_dest() \
2309 memory_map_write[dest_current_region] \
2311 #define dma_vars_gamepak(type) \
2312 u32 type##_new_region; \
2313 u32 type##_current_region = type##_ptr >> 15; \
2314 u8 *type##_address_block = dma_segmented_load_##type(); \
2315 if(type##_address_block == NULL) \
2317 if((type##_ptr & 0x1FFFFFF) >= gamepak_size) \
2319 type##_address_block = load_gamepak_page(type##_current_region & 0x3FF); \
2322 #define dma_vars_ewram(type) \
2323 dma_smc_vars_##type(); \
2324 u32 type##_new_region; \
2325 u32 type##_current_region = type##_ptr >> 15; \
2326 u8 *type##_address_block = dma_segmented_load_##type() \
2328 #define dma_vars_bios(type) \
2330 #define dma_vars_ext(type) \
2332 #define dma_ewram_check_region(type) \
2333 type##_new_region = (type##_ptr >> 15); \
2334 if(type##_new_region != type##_current_region) \
2336 type##_current_region = type##_new_region; \
2337 type##_address_block = dma_segmented_load_##type(); \
2340 #define dma_gamepak_check_region(type) \
2341 type##_new_region = (type##_ptr >> 15); \
2342 if(type##_new_region != type##_current_region) \
2344 type##_current_region = type##_new_region; \
2345 type##_address_block = dma_segmented_load_##type(); \
2346 if(type##_address_block == NULL) \
2348 type##_address_block = \
2349 load_gamepak_page(type##_current_region & 0x3FF); \
2353 #define dma_read_iwram(type, transfer_size) \
2354 read_value = address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) \
2356 #define dma_read_vram(type, transfer_size) \
2357 read_value = address##transfer_size(vram, type##_ptr & 0x1FFFF) \
2359 #define dma_read_io(type, transfer_size) \
2360 read_value = address##transfer_size(io_registers, type##_ptr & 0x7FFF) \
2362 #define dma_read_oam_ram(type, transfer_size) \
2363 read_value = address##transfer_size(oam_ram, type##_ptr & 0x3FF) \
2365 #define dma_read_palette_ram(type, transfer_size) \
2366 read_value = address##transfer_size(palette_ram, type##_ptr & 0x3FF) \
2368 #define dma_read_ewram(type, transfer_size) \
2369 dma_ewram_check_region(type); \
2370 read_value = address##transfer_size(type##_address_block, \
2371 type##_ptr & 0x7FFF) \
2373 #define dma_read_gamepak(type, transfer_size) \
2374 dma_gamepak_check_region(type); \
2375 read_value = address##transfer_size(type##_address_block, \
2376 type##_ptr & 0x7FFF) \
2378 // DMAing from the BIOS is funny, just returns 0..
2380 #define dma_read_bios(type, transfer_size) \
2383 #define dma_read_ext(type, transfer_size) \
2384 read_value = read_memory##transfer_size(type##_ptr) \
2386 #define dma_write_iwram(type, transfer_size) \
2387 address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) = read_value; \
2388 smc_trigger |= address##transfer_size(iwram, type##_ptr & 0x7FFF) \
2390 #define dma_write_vram(type, transfer_size) \
2391 address##transfer_size(vram, type##_ptr & 0x1FFFF) = read_value \
2393 #define dma_write_io(type, transfer_size) \
2394 write_io_register##transfer_size(type##_ptr & 0x3FF, read_value) \
2396 #define dma_write_oam_ram(type, transfer_size) \
2397 address##transfer_size(oam_ram, type##_ptr & 0x3FF) = read_value \
2399 #define dma_write_palette_ram(type, transfer_size) \
2400 write_palette##transfer_size(type##_ptr & 0x3FF, read_value) \
2402 #define dma_write_ext(type, transfer_size) \
2403 write_memory##transfer_size(type##_ptr, read_value) \
2405 #define dma_write_ewram(type, transfer_size) \
2406 dma_ewram_check_region(type); \
2408 address##transfer_size(type##_address_block, type##_ptr & 0x7FFF) = \
2410 smc_trigger |= address##transfer_size(type##_address_block, \
2411 (type##_ptr & 0x7FFF) - 0x8000) \
2413 #define dma_epilogue_iwram() \
2416 /* Special return code indicating to retranslate to the CPU code */ \
2417 return_value = CPU_ALERT_SMC; \
2420 #define dma_epilogue_ewram() \
2423 /* Special return code indicating to retranslate to the CPU code */ \
2424 return_value = CPU_ALERT_SMC; \
2427 #define dma_epilogue_vram() \
2429 #define dma_epilogue_io() \
2431 #define dma_epilogue_oam_ram() \
2433 #define dma_epilogue_palette_ram() \
2435 #define dma_epilogue_GAMEPAK() \
2437 #define dma_epilogue_ext() \
2439 #define print_line() \
2440 dma_print(src_op, dest_op, transfer_size, wb); \
2442 #define dma_transfer_loop_region(src_region_type, dest_region_type, src_op, \
2443 dest_op, transfer_size, wb) \
2445 dma_vars_##src_region_type(src); \
2446 dma_vars_##dest_region_type(dest); \
2448 for(i = 0; i < length; i++) \
2450 dma_read_##src_region_type(src, transfer_size); \
2451 dma_write_##dest_region_type(dest, transfer_size); \
2452 dma_adjust_ptr_##src_op(src_ptr, transfer_size); \
2453 dma_adjust_ptr_##dest_op(dest_ptr, transfer_size); \
2455 dma->source_address = src_ptr; \
2456 dma_adjust_ptr_##wb(); \
2457 dma_epilogue_##dest_region_type(); \
2461 #define dma_transfer_loop(src_op, dest_op, transfer_size, wb); \
2463 u32 src_region = src_ptr >> 24; \
2464 u32 dest_region = dest_ptr >> 24; \
2465 dma_region_type src_region_type = dma_region_map[src_region]; \
2466 dma_region_type dest_region_type = dma_region_map[dest_region]; \
2468 switch(src_region_type | (dest_region_type << 4)) \
2470 case (DMA_REGION_BIOS | (DMA_REGION_IWRAM << 4)): \
2471 dma_transfer_loop_region(bios, iwram, src_op, dest_op, \
2472 transfer_size, wb); \
2474 case (DMA_REGION_IWRAM | (DMA_REGION_IWRAM << 4)): \
2475 dma_transfer_loop_region(iwram, iwram, src_op, dest_op, \
2476 transfer_size, wb); \
2478 case (DMA_REGION_EWRAM | (DMA_REGION_IWRAM << 4)): \
2479 dma_transfer_loop_region(ewram, iwram, src_op, dest_op, \
2480 transfer_size, wb); \
2482 case (DMA_REGION_VRAM | (DMA_REGION_IWRAM << 4)): \
2483 dma_transfer_loop_region(vram, iwram, src_op, dest_op, \
2484 transfer_size, wb); \
2486 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IWRAM << 4)): \
2487 dma_transfer_loop_region(palette_ram, iwram, src_op, dest_op, \
2488 transfer_size, wb); \
2490 case (DMA_REGION_OAM_RAM | (DMA_REGION_IWRAM << 4)): \
2491 dma_transfer_loop_region(oam_ram, iwram, src_op, dest_op, \
2492 transfer_size, wb); \
2494 case (DMA_REGION_IO | (DMA_REGION_IWRAM << 4)): \
2495 dma_transfer_loop_region(io, iwram, src_op, dest_op, \
2496 transfer_size, wb); \
2498 case (DMA_REGION_GAMEPAK | (DMA_REGION_IWRAM << 4)): \
2499 dma_transfer_loop_region(gamepak, iwram, src_op, dest_op, \
2500 transfer_size, wb); \
2502 case (DMA_REGION_EXT | (DMA_REGION_IWRAM << 4)): \
2503 dma_transfer_loop_region(ext, iwram, src_op, dest_op, \
2504 transfer_size, wb); \
2506 case (DMA_REGION_BIOS | (DMA_REGION_EWRAM << 4)): \
2507 dma_transfer_loop_region(bios, ewram, src_op, dest_op, \
2508 transfer_size, wb); \
2510 case (DMA_REGION_IWRAM | (DMA_REGION_EWRAM << 4)): \
2511 dma_transfer_loop_region(iwram, ewram, src_op, dest_op, \
2512 transfer_size, wb); \
2514 case (DMA_REGION_EWRAM | (DMA_REGION_EWRAM << 4)): \
2515 dma_transfer_loop_region(ewram, ewram, src_op, dest_op, \
2516 transfer_size, wb); \
2518 case (DMA_REGION_VRAM | (DMA_REGION_EWRAM << 4)): \
2519 dma_transfer_loop_region(vram, ewram, src_op, dest_op, \
2520 transfer_size, wb); \
2522 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EWRAM << 4)): \
2523 dma_transfer_loop_region(palette_ram, ewram, src_op, dest_op, \
2524 transfer_size, wb); \
2526 case (DMA_REGION_OAM_RAM | (DMA_REGION_EWRAM << 4)): \
2527 dma_transfer_loop_region(oam_ram, ewram, src_op, dest_op, \
2528 transfer_size, wb); \
2530 case (DMA_REGION_IO | (DMA_REGION_EWRAM << 4)): \
2531 dma_transfer_loop_region(io, ewram, src_op, dest_op, \
2532 transfer_size, wb); \
2534 case (DMA_REGION_GAMEPAK | (DMA_REGION_EWRAM << 4)): \
2535 dma_transfer_loop_region(gamepak, ewram, src_op, dest_op, \
2536 transfer_size, wb); \
2538 case (DMA_REGION_EXT | (DMA_REGION_EWRAM << 4)): \
2539 dma_transfer_loop_region(ext, ewram, src_op, dest_op, \
2540 transfer_size, wb); \
2542 case (DMA_REGION_BIOS | (DMA_REGION_VRAM << 4)): \
2543 dma_transfer_loop_region(bios, vram, src_op, dest_op, \
2544 transfer_size, wb); \
2546 case (DMA_REGION_IWRAM | (DMA_REGION_VRAM << 4)): \
2547 dma_transfer_loop_region(iwram, vram, src_op, dest_op, \
2548 transfer_size, wb); \
2550 case (DMA_REGION_EWRAM | (DMA_REGION_VRAM << 4)): \
2551 dma_transfer_loop_region(ewram, vram, src_op, dest_op, \
2552 transfer_size, wb); \
2554 case (DMA_REGION_VRAM | (DMA_REGION_VRAM << 4)): \
2555 dma_transfer_loop_region(vram, vram, src_op, dest_op, \
2556 transfer_size, wb); \
2558 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_VRAM << 4)): \
2559 dma_transfer_loop_region(palette_ram, vram, src_op, dest_op, \
2560 transfer_size, wb); \
2562 case (DMA_REGION_OAM_RAM | (DMA_REGION_VRAM << 4)): \
2563 dma_transfer_loop_region(oam_ram, vram, src_op, dest_op, \
2564 transfer_size, wb); \
2566 case (DMA_REGION_IO | (DMA_REGION_VRAM << 4)): \
2567 dma_transfer_loop_region(io, vram, src_op, dest_op, \
2568 transfer_size, wb); \
2570 case (DMA_REGION_GAMEPAK | (DMA_REGION_VRAM << 4)): \
2571 dma_transfer_loop_region(gamepak, vram, src_op, dest_op, \
2572 transfer_size, wb); \
2574 case (DMA_REGION_EXT | (DMA_REGION_VRAM << 4)): \
2575 dma_transfer_loop_region(ext, vram, src_op, dest_op, \
2576 transfer_size, wb); \
2578 case (DMA_REGION_BIOS | (DMA_REGION_PALETTE_RAM << 4)): \
2579 dma_transfer_loop_region(bios, palette_ram, src_op, dest_op, \
2580 transfer_size, wb); \
2582 case (DMA_REGION_IWRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2583 dma_transfer_loop_region(iwram, palette_ram, src_op, dest_op, \
2584 transfer_size, wb); \
2586 case (DMA_REGION_EWRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2587 dma_transfer_loop_region(ewram, palette_ram, src_op, dest_op, \
2588 transfer_size, wb); \
2590 case (DMA_REGION_VRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2591 dma_transfer_loop_region(vram, palette_ram, src_op, dest_op, \
2592 transfer_size, wb); \
2594 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_PALETTE_RAM << 4)): \
2595 dma_transfer_loop_region(palette_ram, palette_ram, src_op, dest_op, \
2596 transfer_size, wb); \
2598 case (DMA_REGION_OAM_RAM | (DMA_REGION_PALETTE_RAM << 4)): \
2599 dma_transfer_loop_region(oam_ram, palette_ram, src_op, dest_op, \
2600 transfer_size, wb); \
2602 case (DMA_REGION_IO | (DMA_REGION_PALETTE_RAM << 4)): \
2603 dma_transfer_loop_region(io, palette_ram, src_op, dest_op, \
2604 transfer_size, wb); \
2606 case (DMA_REGION_GAMEPAK | (DMA_REGION_PALETTE_RAM << 4)): \
2607 dma_transfer_loop_region(gamepak, palette_ram, src_op, dest_op, \
2608 transfer_size, wb); \
2610 case (DMA_REGION_EXT | (DMA_REGION_PALETTE_RAM << 4)): \
2611 dma_transfer_loop_region(ext, palette_ram, src_op, dest_op, \
2612 transfer_size, wb); \
2614 case (DMA_REGION_BIOS | (DMA_REGION_OAM_RAM << 4)): \
2615 dma_transfer_loop_region(bios, oam_ram, src_op, dest_op, \
2616 transfer_size, wb); \
2618 case (DMA_REGION_IWRAM | (DMA_REGION_OAM_RAM << 4)): \
2619 dma_transfer_loop_region(iwram, oam_ram, src_op, dest_op, \
2620 transfer_size, wb); \
2622 case (DMA_REGION_EWRAM | (DMA_REGION_OAM_RAM << 4)): \
2623 dma_transfer_loop_region(ewram, oam_ram, src_op, dest_op, \
2624 transfer_size, wb); \
2626 case (DMA_REGION_VRAM | (DMA_REGION_OAM_RAM << 4)): \
2627 dma_transfer_loop_region(vram, oam_ram, src_op, dest_op, \
2628 transfer_size, wb); \
2630 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_OAM_RAM << 4)): \
2631 dma_transfer_loop_region(palette_ram, oam_ram, src_op, dest_op, \
2632 transfer_size, wb); \
2634 case (DMA_REGION_OAM_RAM | (DMA_REGION_OAM_RAM << 4)): \
2635 dma_transfer_loop_region(oam_ram, oam_ram, src_op, dest_op, \
2636 transfer_size, wb); \
2638 case (DMA_REGION_IO | (DMA_REGION_OAM_RAM << 4)): \
2639 dma_transfer_loop_region(io, oam_ram, src_op, dest_op, \
2640 transfer_size, wb); \
2642 case (DMA_REGION_GAMEPAK | (DMA_REGION_OAM_RAM << 4)): \
2643 dma_transfer_loop_region(gamepak, oam_ram, src_op, dest_op, \
2644 transfer_size, wb); \
2646 case (DMA_REGION_EXT | (DMA_REGION_OAM_RAM << 4)): \
2647 dma_transfer_loop_region(ext, oam_ram, src_op, dest_op, \
2648 transfer_size, wb); \
2650 case (DMA_REGION_BIOS | (DMA_REGION_IO << 4)): \
2651 dma_transfer_loop_region(bios, io, src_op, dest_op, \
2652 transfer_size, wb); \
2654 case (DMA_REGION_IWRAM | (DMA_REGION_IO << 4)): \
2655 dma_transfer_loop_region(iwram, io, src_op, dest_op, \
2656 transfer_size, wb); \
2658 case (DMA_REGION_EWRAM | (DMA_REGION_IO << 4)): \
2659 dma_transfer_loop_region(ewram, io, src_op, dest_op, \
2660 transfer_size, wb); \
2662 case (DMA_REGION_VRAM | (DMA_REGION_IO << 4)): \
2663 dma_transfer_loop_region(vram, io, src_op, dest_op, \
2664 transfer_size, wb); \
2666 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IO << 4)): \
2667 dma_transfer_loop_region(palette_ram, io, src_op, dest_op, \
2668 transfer_size, wb); \
2670 case (DMA_REGION_OAM_RAM | (DMA_REGION_IO << 4)): \
2671 dma_transfer_loop_region(oam_ram, io, src_op, dest_op, \
2672 transfer_size, wb); \
2674 case (DMA_REGION_IO | (DMA_REGION_IO << 4)): \
2675 dma_transfer_loop_region(io, io, src_op, dest_op, \
2676 transfer_size, wb); \
2678 case (DMA_REGION_GAMEPAK | (DMA_REGION_IO << 4)): \
2679 dma_transfer_loop_region(gamepak, io, src_op, dest_op, \
2680 transfer_size, wb); \
2682 case (DMA_REGION_EXT | (DMA_REGION_IO << 4)): \
2683 dma_transfer_loop_region(ext, io, src_op, dest_op, \
2684 transfer_size, wb); \
2686 case (DMA_REGION_BIOS | (DMA_REGION_EXT << 4)): \
2687 dma_transfer_loop_region(bios, ext, src_op, dest_op, \
2688 transfer_size, wb); \
2690 case (DMA_REGION_IWRAM | (DMA_REGION_EXT << 4)): \
2691 dma_transfer_loop_region(iwram, ext, src_op, dest_op, \
2692 transfer_size, wb); \
2694 case (DMA_REGION_EWRAM | (DMA_REGION_EXT << 4)): \
2695 dma_transfer_loop_region(ewram, ext, src_op, dest_op, \
2696 transfer_size, wb); \
2698 case (DMA_REGION_VRAM | (DMA_REGION_EXT << 4)): \
2699 dma_transfer_loop_region(vram, ext, src_op, dest_op, \
2700 transfer_size, wb); \
2702 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EXT << 4)): \
2703 dma_transfer_loop_region(palette_ram, ext, src_op, dest_op, \
2704 transfer_size, wb); \
2706 case (DMA_REGION_OAM_RAM | (DMA_REGION_EXT << 4)): \
2707 dma_transfer_loop_region(oam_ram, ext, src_op, dest_op, \
2708 transfer_size, wb); \
2710 case (DMA_REGION_IO | (DMA_REGION_EXT << 4)): \
2711 dma_transfer_loop_region(io, ext, src_op, dest_op, \
2712 transfer_size, wb); \
2714 case (DMA_REGION_GAMEPAK | (DMA_REGION_EXT << 4)): \
2715 dma_transfer_loop_region(gamepak, ext, src_op, dest_op, \
2716 transfer_size, wb); \
2718 case (DMA_REGION_EXT | (DMA_REGION_EXT << 3)): \
2719 dma_transfer_loop_region(ext, ext, src_op, dest_op, \
2720 transfer_size, wb); \
2725 #define dma_transfer_expand(transfer_size) \
2726 switch((dma->dest_direction << 2) | dma->source_direction) \
2729 dma_transfer_loop(inc, inc, transfer_size, writeback); \
2732 dma_transfer_loop(dec, inc, transfer_size, writeback); \
2735 dma_transfer_loop(fix, inc, transfer_size, writeback); \
2741 dma_transfer_loop(inc, dec, transfer_size, writeback); \
2744 dma_transfer_loop(dec, dec, transfer_size, writeback); \
2747 dma_transfer_loop(fix, dec, transfer_size, writeback); \
2753 dma_transfer_loop(inc, fix, transfer_size, writeback); \
2756 dma_transfer_loop(dec, fix, transfer_size, writeback); \
2759 dma_transfer_loop(fix, fix, transfer_size, writeback); \
2765 dma_transfer_loop(inc, inc, transfer_size, reload); \
2768 dma_transfer_loop(dec, inc, transfer_size, reload); \
2771 dma_transfer_loop(fix, inc, transfer_size, reload); \
2777 cpu_alert_type dma_transfer(dma_transfer_type *dma)
2780 u32 length = dma->length;
2782 u32 src_ptr = dma->source_address;
2783 u32 dest_ptr = dma->dest_address;
2784 cpu_alert_type return_value = CPU_ALERT_NONE;
2786 // Technically this should be done for source and destination, but
2787 // chances are this is only ever used (probably mistakingly!) for dest.
2788 // The only game I know of that requires this is Lucky Luke.
2789 if((dest_ptr >> 24) != ((dest_ptr + length - 1) >> 24))
2791 u32 first_length = ((dest_ptr & 0xFF000000) + 0x1000000) - dest_ptr;
2792 u32 second_length = length - first_length;
2793 dma->length = first_length;
2797 dma->length = length;
2799 length = second_length;
2800 dest_ptr += first_length;
2801 src_ptr += first_length;
2804 if(dma->length_type == DMA_16BIT)
2808 cycle_dma16_words += length;
2809 dma_transfer_expand(16);
2815 cycle_dma32_words += length;
2816 dma_transfer_expand(32);
2819 if((dma->repeat_type == DMA_NO_REPEAT) ||
2820 (dma->start_type == DMA_START_IMMEDIATELY))
2822 dma->start_type = DMA_INACTIVE;
2823 address16(io_registers, (dma->dma_channel * 12) + 0xBA) &=
2829 raise_interrupt(IRQ_DMA0 << dma->dma_channel);
2830 return_value = CPU_ALERT_IRQ;
2833 return return_value;
2836 // Be sure to do this after loading ROMs.
2838 #define map_region(type, start, end, mirror_blocks, region) \
2839 for(map_offset = (start) / 0x8000; map_offset < \
2840 ((end) / 0x8000); map_offset++) \
2842 memory_map_##type[map_offset] = \
2843 ((u8 *)region) + ((map_offset % mirror_blocks) * 0x8000); \
2846 #define map_null(type, start, end) \
2847 for(map_offset = start / 0x8000; map_offset < (end / 0x8000); \
2850 memory_map_##type[map_offset] = NULL; \
2853 #define map_ram_region(type, start, end, mirror_blocks, region) \
2854 for(map_offset = (start) / 0x8000; map_offset < \
2855 ((end) / 0x8000); map_offset++) \
2857 memory_map_##type[map_offset] = \
2858 ((u8 *)region) + ((map_offset % mirror_blocks) * 0x10000) + 0x8000; \
2861 #define map_vram(type) \
2862 for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \
2865 memory_map_##type[map_offset] = vram; \
2866 memory_map_##type[map_offset + 1] = vram + 0x8000; \
2867 memory_map_##type[map_offset + 2] = vram + (0x8000 * 2); \
2868 memory_map_##type[map_offset + 3] = vram + (0x8000 * 2); \
2871 #define map_vram_firstpage(type) \
2872 for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \
2875 memory_map_##type[map_offset] = vram; \
2876 memory_map_##type[map_offset + 1] = NULL; \
2877 memory_map_##type[map_offset + 2] = NULL; \
2878 memory_map_##type[map_offset + 3] = NULL; \
2882 // Picks a page to evict
2885 u32 evict_gamepak_page()
2887 // Find the one with the smallest frame timestamp
2890 u32 smallest = gamepak_memory_map[0].page_timestamp;
2893 for(i = 1; i < gamepak_ram_pages; i++)
2895 if(gamepak_memory_map[i].page_timestamp <= smallest)
2897 smallest = gamepak_memory_map[i].page_timestamp;
2902 physical_index = gamepak_memory_map[page_index].physical_index;
2904 memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = NULL;
2905 memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = NULL;
2906 memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = NULL;
2911 u8 *load_gamepak_page(u32 physical_index)
2913 if(physical_index >= (gamepak_size >> 15))
2916 u32 page_index = evict_gamepak_page();
2917 u32 page_offset = page_index * (32 * 1024);
2918 u8 *swap_location = gamepak_rom + page_offset;
2920 gamepak_memory_map[page_index].page_timestamp = page_time;
2921 gamepak_memory_map[page_index].physical_index = physical_index;
2924 file_seek(gamepak_file_large, physical_index * (32 * 1024), SEEK_SET);
2925 file_read(gamepak_file_large, swap_location, (32 * 1024));
2926 memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = swap_location;
2927 memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = swap_location;
2928 memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = swap_location;
2930 // If RTC is active page the RTC register bytes so they can be read
2931 if((rtc_state != RTC_DISABLED) && (physical_index == 0))
2933 memcpy(swap_location + 0xC4, rtc_registers, sizeof(rtc_registers));
2936 return swap_location;
2939 void init_memory_gamepak()
2943 if(gamepak_size > gamepak_ram_buffer_size)
2945 // Large ROMs get special treatment because they
2946 // can't fit into the 16MB ROM buffer.
2948 for(i = 0; i < gamepak_ram_pages; i++)
2950 gamepak_memory_map[i].page_timestamp = 0;
2951 gamepak_memory_map[i].physical_index = 0;
2954 map_null(read, 0x8000000, 0xD000000);
2958 map_region(read, 0x8000000, 0x8000000 + gamepak_size, 1024, gamepak_rom);
2959 map_null(read, 0x8000000 + gamepak_size, 0xA000000);
2960 map_region(read, 0xA000000, 0xA000000 + gamepak_size, 1024, gamepak_rom);
2961 map_null(read, 0xA000000 + gamepak_size, 0xC000000);
2962 map_region(read, 0xC000000, 0xC000000 + gamepak_size, 1024, gamepak_rom);
2963 map_null(read, 0xC000000 + gamepak_size, 0xE000000);
2967 void init_gamepak_buffer()
2969 // Try to initialize 32MB (this is mainly for non-PSP platforms)
2972 gamepak_ram_buffer_size = 32 * 1024 * 1024;
2973 gamepak_rom = malloc(gamepak_ram_buffer_size);
2975 if(gamepak_rom == NULL)
2977 // Try 16MB, for PSP, then lower in 2MB increments
2978 gamepak_ram_buffer_size = 16 * 1024 * 1024;
2979 gamepak_rom = malloc(gamepak_ram_buffer_size);
2981 while(gamepak_rom == NULL)
2983 gamepak_ram_buffer_size -= (2 * 1024 * 1024);
2984 gamepak_rom = malloc(gamepak_ram_buffer_size);
2988 // Here's assuming we'll have enough memory left over for this,
2989 // and that the above succeeded (if not we're in trouble all around)
2990 gamepak_ram_pages = gamepak_ram_buffer_size / (32 * 1024);
2991 gamepak_memory_map = malloc(sizeof(gamepak_swap_entry_type) *
3000 memory_regions[0x00] = (u8 *)bios_rom;
3001 memory_regions[0x01] = (u8 *)bios_rom;
3002 memory_regions[0x02] = (u8 *)ewram;
3003 memory_regions[0x03] = (u8 *)iwram + 0x8000;
3004 memory_regions[0x04] = (u8 *)io_registers;
3005 memory_regions[0x05] = (u8 *)palette_ram;
3006 memory_regions[0x06] = (u8 *)vram;
3007 memory_regions[0x07] = (u8 *)oam_ram;
3008 memory_regions[0x08] = (u8 *)gamepak_rom;
3009 memory_regions[0x09] = (u8 *)(gamepak_rom + 0xFFFFFF);
3010 memory_regions[0x0A] = (u8 *)gamepak_rom;
3011 memory_regions[0x0B] = (u8 *)(gamepak_rom + 0xFFFFFF);
3012 memory_regions[0x0C] = (u8 *)gamepak_rom;
3013 memory_regions[0x0D] = (u8 *)(gamepak_rom + 0xFFFFFF);
3014 memory_regions[0x0E] = (u8 *)gamepak_backup;
3016 memory_limits[0x00] = 0x3FFF;
3017 memory_limits[0x01] = 0x3FFF;
3018 memory_limits[0x02] = 0x3FFFF;
3019 memory_limits[0x03] = 0x7FFF;
3020 memory_limits[0x04] = 0x7FFF;
3021 memory_limits[0x05] = 0x3FF;
3022 memory_limits[0x06] = 0x17FFF;
3023 memory_limits[0x07] = 0x3FF;
3024 memory_limits[0x08] = 0x1FFFFFF;
3025 memory_limits[0x09] = 0x1FFFFFF;
3026 memory_limits[0x0A] = 0x1FFFFFF;
3027 memory_limits[0x0B] = 0x1FFFFFF;
3028 memory_limits[0x0C] = 0x1FFFFFF;
3029 memory_limits[0x0D] = 0x1FFFFFF;
3030 memory_limits[0x0E] = 0xFFFF;
3032 // Fill memory map regions, areas marked as NULL must be checked directly
3033 map_region(read, 0x0000000, 0x1000000, 1, bios_rom);
3034 map_null(read, 0x1000000, 0x2000000);
3035 map_ram_region(read, 0x2000000, 0x3000000, 8, ewram);
3036 map_ram_region(read, 0x3000000, 0x4000000, 1, iwram);
3037 map_region(read, 0x4000000, 0x5000000, 1, io_registers);
3038 map_null(read, 0x5000000, 0x6000000);
3039 map_null(read, 0x6000000, 0x7000000);
3041 map_null(read, 0x7000000, 0x8000000);
3042 init_memory_gamepak();
3043 map_null(read, 0xE000000, 0x10000000);
3045 // Fill memory map regions, areas marked as NULL must be checked directly
3046 map_null(write, 0x0000000, 0x2000000);
3047 map_ram_region(write, 0x2000000, 0x3000000, 8, ewram);
3048 map_ram_region(write, 0x3000000, 0x4000000, 1, iwram);
3049 map_null(write, 0x4000000, 0x5000000);
3050 map_null(write, 0x5000000, 0x6000000);
3052 // The problem here is that the current method of handling self-modifying code
3053 // requires writeable memory to be proceeded by 32KB SMC data areas or be
3054 // indirectly writeable. It's possible to get around this if you turn off the SMC
3055 // check altogether, but this will make a good number of ROMs crash (perhaps most
3056 // of the ones that actually need it? This has yet to be determined).
3058 // This is because VRAM cannot be efficiently made incontiguous, and still allow
3059 // the renderer to work as efficiently. It would, at the very least, require a
3060 // lot of hacking of the renderer which I'm not prepared to do.
3062 // However, it IS possible to directly map the first page no matter what because
3063 // there's 32kb of blank stuff sitting beneath it.
3070 map_null(write, 0x6000000, 0x7000000);
3073 map_null(write, 0x7000000, 0x8000000);
3074 map_null(write, 0x8000000, 0xE000000);
3075 map_null(write, 0xE000000, 0x10000000);
3077 memset(io_registers, 0, 0x8000);
3078 memset(oam_ram, 0, 0x400);
3079 memset(palette_ram, 0, 0x400);
3080 memset(iwram, 0, 0x10000);
3081 memset(ewram, 0, 0x80000);
3082 memset(vram, 0, 0x18000);
3084 io_registers[REG_DISPCNT] = 0x80;
3085 io_registers[REG_P1] = 0x3FF;
3086 io_registers[REG_BG2PA] = 0x100;
3087 io_registers[REG_BG2PD] = 0x100;
3088 io_registers[REG_BG3PA] = 0x100;
3089 io_registers[REG_BG3PD] = 0x100;
3090 io_registers[REG_RCNT] = 0x8000;
3092 backup_type = BACKUP_NONE;
3094 sram_size = SRAM_SIZE_32KB;
3095 flash_size = FLASH_SIZE_64KB;
3097 flash_bank_ptr = gamepak_backup;
3098 flash_command_position = 0;
3099 eeprom_size = EEPROM_512_BYTE;
3100 eeprom_mode = EEPROM_BASE_MODE;
3104 flash_mode = FLASH_BASE_MODE;
3106 rtc_state = RTC_DISABLED;
3107 memset(rtc_registers, 0, sizeof(rtc_registers));
3108 bios_read_protect = 0xe129f000;
3111 void bios_region_read_allow()
3113 memory_map_read[0] = bios_rom;
3116 void bios_region_read_protect()
3119 memory_map_read[0] = NULL;
3124 #define savestate_block(type) \
3125 cpu_##type##_savestate(savestate_file); \
3126 input_##type##_savestate(savestate_file); \
3127 main_##type##_savestate(savestate_file); \
3128 memory_##type##_savestate(savestate_file); \
3129 sound_##type##_savestate(savestate_file); \
3130 video_##type##_savestate(savestate_file) \
3132 void load_state(char *savestate_filename)
3134 file_open(savestate_file, savestate_filename, read);
3135 if(file_check_valid(savestate_file))
3137 char current_gamepak_filename[512];
3138 char savestate_gamepak_filename[512];
3142 file_seek(savestate_file, (240 * 160 * 2) + sizeof(time_t), SEEK_SET);
3144 strcpy(current_gamepak_filename, gamepak_filename);
3146 savestate_block(read);
3148 file_close(savestate_file);
3150 flush_translation_cache_ram();
3151 flush_translation_cache_rom();
3152 flush_translation_cache_bios();
3155 gbc_sound_update = 1;
3156 if(strcmp(current_gamepak_filename, gamepak_filename))
3158 u32 dot_position = strcspn(current_gamepak_filename, ".");
3160 // We'll let it slide if the filenames of the savestate and
3161 // the gamepak are similar enough.
3162 strcpy(gamepak_filename, current_gamepak_filename);
3163 if(strncmp(savestate_filename, current_gamepak_filename, dot_position))
3165 if(load_gamepak(gamepak_filename) != -1)
3168 // Okay, so this takes a while, but for now it works.
3169 load_state(savestate_filename);
3180 for(i = 0; i < 512; i++)
3182 current_color = palette_ram[i];
3183 palette_ram_converted[i] =
3184 convert_palette(current_color);
3187 // Oops, these contain raw pointers
3188 for(i = 0; i < 4; i++)
3190 gbc_sound_channel[i].sample_data = square_pattern_duty[2];
3192 current_debug_state = STEP;
3193 instruction_count = 0;
3195 reg[CHANGED_PC_STATUS] = 1;
3199 u8 savestate_write_buffer[506947];
3202 void save_state(char *savestate_filename, u16 *screen_capture)
3204 write_mem_ptr = savestate_write_buffer;
3205 file_open(savestate_file, savestate_filename, write);
3206 if(file_check_valid(savestate_file))
3208 time_t current_time;
3209 file_write_mem(savestate_file, screen_capture, 240 * 160 * 2);
3211 time(¤t_time);
3212 file_write_mem_variable(savestate_file, current_time);
3214 savestate_block(write_mem);
3215 file_write(savestate_file, savestate_write_buffer,
3216 sizeof(savestate_write_buffer));
3218 file_close(savestate_file);
3223 #define memory_savestate_builder(type) \
3224 void memory_##type##_savestate(file_tag_type savestate_file) \
3228 file_##type##_variable(savestate_file, backup_type); \
3229 file_##type##_variable(savestate_file, sram_size); \
3230 file_##type##_variable(savestate_file, flash_mode); \
3231 file_##type##_variable(savestate_file, flash_command_position); \
3232 file_##type##_variable(savestate_file, flash_bank_ptr); \
3233 file_##type##_variable(savestate_file, flash_device_id); \
3234 file_##type##_variable(savestate_file, flash_manufacturer_id); \
3235 file_##type##_variable(savestate_file, flash_size); \
3236 file_##type##_variable(savestate_file, eeprom_size); \
3237 file_##type##_variable(savestate_file, eeprom_mode); \
3238 file_##type##_variable(savestate_file, eeprom_address_length); \
3239 file_##type##_variable(savestate_file, eeprom_address); \
3240 file_##type##_variable(savestate_file, eeprom_counter); \
3241 file_##type##_variable(savestate_file, rtc_state); \
3242 file_##type##_variable(savestate_file, rtc_write_mode); \
3243 file_##type##_array(savestate_file, rtc_registers); \
3244 file_##type##_variable(savestate_file, rtc_command); \
3245 file_##type##_array(savestate_file, rtc_data); \
3246 file_##type##_variable(savestate_file, rtc_status); \
3247 file_##type##_variable(savestate_file, rtc_data_bytes); \
3248 file_##type##_variable(savestate_file, rtc_bit_count); \
3249 file_##type##_array(savestate_file, eeprom_buffer); \
3250 file_##type##_array(savestate_file, gamepak_filename); \
3251 file_##type##_array(savestate_file, dma); \
3253 file_##type(savestate_file, iwram + 0x8000, 0x8000); \
3254 for(i = 0; i < 8; i++) \
3256 file_##type(savestate_file, ewram + (i * 0x10000) + 0x8000, 0x8000); \
3258 file_##type(savestate_file, vram, 0x18000); \
3259 file_##type(savestate_file, oam_ram, 0x400); \
3260 file_##type(savestate_file, palette_ram, 0x400); \
3261 file_##type(savestate_file, io_registers, 0x8000); \
3263 /* This is a hack, for now. */ \
3264 if((flash_bank_ptr < gamepak_backup) || \
3265 (flash_bank_ptr > (gamepak_backup + (1024 * 64)))) \
3267 flash_bank_ptr = gamepak_backup; \
3271 memory_savestate_builder(read);
3272 memory_savestate_builder(write_mem);