3 * Copyright (C) 2006 Exophase <exophase@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 // This table is configured for sequential access on system defaults
25 u32 waitstate_cycles_sequential[16][3] =
28 { 1, 1, 1 }, // Invalid
29 { 3, 3, 6 }, // EWRAM (default settings)
31 { 1, 1, 1 }, // IO Registers
32 { 1, 1, 2 }, // Palette RAM
35 { 3, 3, 6 }, // Gamepak (wait 0)
36 { 3, 3, 6 }, // Gamepak (wait 0)
37 { 5, 5, 9 }, // Gamepak (wait 1)
38 { 5, 5, 9 }, // Gamepak (wait 1)
39 { 9, 9, 17 }, // Gamepak (wait 2)
40 { 9, 9, 17 }, // Gamepak (wait 2)
43 // Different settings for gamepak ws0-2 sequential (2nd) access
45 u32 gamepak_waitstate_sequential[2][3][3] =
61 u16 palette_ram_converted[512];
62 u16 io_registers[1024 * 16];
63 u8 ewram[1024 * 256 * 2];
64 u8 iwram[1024 * 32 * 2];
65 u8 vram[1024 * 96 * 2];
67 u8 bios_rom[1024 * 32];
68 u32 bios_read_protect;
70 // Up to 128kb, store SRAM, flash ROM, or EEPROM here.
71 u8 gamepak_backup[1024 * 128];
73 // Keeps us knowing how much we have left.
77 dma_transfer_type dma[4];
79 u8 *memory_regions[16];
80 u32 memory_limits[16];
86 } gamepak_swap_entry_type;
88 u32 gamepak_ram_buffer_size;
89 u32 gamepak_ram_pages;
91 // Enough to map the gamepak RAM space.
92 gamepak_swap_entry_type *gamepak_memory_map;
94 // This is global so that it can be kept open for large ROMs to swap
95 // pages from, so there's no slowdown with opening and closing the file
99 file_tag_type gamepak_file_large = -1;
103 file_tag_type gamepak_file_large = NULL;
107 u32 direct_map_vram = 0;
109 // Writes to these respective locations should trigger an update
110 // so the related subsystem may react to it.
112 // If OAM is written to:
115 // If GBC audio is written to:
116 u32 gbc_sound_update = 0;
118 // If the GBC audio waveform is modified:
119 u32 gbc_sound_wave_update = 0;
121 // If the backup space is written (only update once this hits 0)
122 u32 backup_update = 0;
124 // Write out backup file this many cycles after the most recent
126 const u32 write_backup_delay = 10;
143 // Keep it 32KB until the upper 64KB is accessed, then make it 64KB.
145 backup_type_type backup_type = BACKUP_NONE;
146 sram_size_type sram_size = SRAM_SIZE_32KB;
154 FLASH_BANKSWITCH_MODE
163 flash_mode_type flash_mode = FLASH_BASE_MODE;
164 u32 flash_command_position = 0;
165 u8 *flash_bank_ptr = gamepak_backup;
167 flash_device_id_type flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
168 flash_manufacturer_id_type flash_manufacturer_id =
169 FLASH_MANUFACTURER_MACRONIX;
170 flash_size_type flash_size = FLASH_SIZE_64KB;
172 u8 read_backup(u32 address)
176 if(backup_type == BACKUP_NONE)
177 backup_type = BACKUP_SRAM;
179 if(backup_type == BACKUP_SRAM)
181 value = gamepak_backup[address];
185 if(flash_mode == FLASH_ID_MODE)
187 /* ID manufacturer type */
188 if(address == 0x0000)
189 value = flash_manufacturer_id;
193 if(address == 0x0001)
194 value = flash_device_id;
198 value = flash_bank_ptr[address];
204 #define read_backup8() \
205 value = read_backup(address & 0xFFFF) \
207 #define read_backup16() \
210 #define read_backup32() \
214 // EEPROM is 512 bytes by default; it is autodetecte as 8KB if
215 // 14bit address DMAs are made (this is done in the DMA handler).
227 EEPROM_READ_HEADER_MODE,
230 EEPROM_WRITE_ADDRESS_MODE,
231 EEPROM_ADDRESS_FOOTER_MODE,
232 EEPROM_WRITE_FOOTER_MODE
236 eeprom_size_type eeprom_size = EEPROM_512_BYTE;
237 eeprom_mode_type eeprom_mode = EEPROM_BASE_MODE;
238 u32 eeprom_address_length;
239 u32 eeprom_address = 0;
240 s32 eeprom_counter = 0;
244 void function_cc write_eeprom(u32 address, u32 value)
248 case EEPROM_BASE_MODE:
249 backup_type = BACKUP_EEPROM;
250 eeprom_buffer[0] |= (value & 0x01) << (1 - eeprom_counter);
252 if(eeprom_counter == 2)
254 if(eeprom_size == EEPROM_512_BYTE)
255 eeprom_address_length = 6;
257 eeprom_address_length = 14;
261 switch(eeprom_buffer[0] & 0x03)
264 eeprom_mode = EEPROM_WRITE_ADDRESS_MODE;
268 eeprom_mode = EEPROM_ADDRESS_MODE;
271 address16(eeprom_buffer, 0) = 0;
275 case EEPROM_ADDRESS_MODE:
276 case EEPROM_WRITE_ADDRESS_MODE:
277 eeprom_buffer[eeprom_counter / 8]
278 |= (value & 0x01) << (7 - (eeprom_counter % 8));
280 if(eeprom_counter == eeprom_address_length)
282 if(eeprom_size == EEPROM_512_BYTE)
285 (address16(eeprom_buffer, 0) >> 2) * 8;
289 eeprom_address = (((u32)eeprom_buffer[1] >> 2) |
290 ((u32)eeprom_buffer[0] << 6)) * 8;
293 address16(eeprom_buffer, 0) = 0;
296 if(eeprom_mode == EEPROM_ADDRESS_MODE)
298 eeprom_mode = EEPROM_ADDRESS_FOOTER_MODE;
302 eeprom_mode = EEPROM_WRITE_MODE;
303 memset(gamepak_backup + eeprom_address, 0, 8);
308 case EEPROM_WRITE_MODE:
309 gamepak_backup[eeprom_address + (eeprom_counter / 8)] |=
310 (value & 0x01) << (7 - (eeprom_counter % 8));
312 if(eeprom_counter == 64)
314 backup_update = write_backup_delay;
316 eeprom_mode = EEPROM_WRITE_FOOTER_MODE;
320 case EEPROM_ADDRESS_FOOTER_MODE:
321 case EEPROM_WRITE_FOOTER_MODE:
323 if(eeprom_mode == EEPROM_ADDRESS_FOOTER_MODE)
325 eeprom_mode = EEPROM_READ_HEADER_MODE;
329 eeprom_mode = EEPROM_BASE_MODE;
338 #define read_memory_gamepak(type) \
339 u32 gamepak_index = address >> 15; \
340 u8 *map = memory_map_read[gamepak_index]; \
343 map = load_gamepak_page(gamepak_index & 0x3FF); \
345 value = address##type(map, address & 0x7FFF) \
347 #define read_open8() \
348 if(!(reg[REG_CPSR] & 0x20)) \
349 value = read_memory8(reg[REG_PC] + 4 + (address & 0x03)); \
351 value = read_memory8(reg[REG_PC] + 2 + (address & 0x01)) \
353 #define read_open16() \
354 if(!(reg[REG_CPSR] & 0x20)) \
355 value = read_memory16(reg[REG_PC] + 4 + (address & 0x02)); \
357 value = read_memory16(reg[REG_PC] + 2) \
359 #define read_open32() \
360 if(!(reg[REG_CPSR] & 0x20)) \
362 value = read_memory32(reg[REG_PC] + 4); \
366 u32 current_instruction = read_memory16(reg[REG_PC] + 2); \
367 value = current_instruction | (current_instruction << 16); \
370 u32 function_cc read_eeprom()
376 case EEPROM_BASE_MODE:
380 case EEPROM_READ_MODE:
381 value = (gamepak_backup[eeprom_address + (eeprom_counter / 8)] >>
382 (7 - (eeprom_counter % 8))) & 0x01;
384 if(eeprom_counter == 64)
387 eeprom_mode = EEPROM_BASE_MODE;
391 case EEPROM_READ_HEADER_MODE:
394 if(eeprom_counter == 4)
396 eeprom_mode = EEPROM_READ_MODE;
410 #define read_memory(type) \
411 switch(address >> 24) \
415 if(reg[REG_PC] >= 0x4000) \
416 value = address##type(&bios_read_protect, address & 0x03); \
418 value = address##type(bios_rom, address & 0x3FFF); \
422 /* external work RAM */ \
423 address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
424 value = address##type(ewram, address); \
428 /* internal work RAM */ \
429 value = address##type(iwram, (address & 0x7FFF) + 0x8000); \
433 /* I/O registers */ \
434 value = address##type(io_registers, address & 0x3FF); \
439 value = address##type(palette_ram, address & 0x3FF); \
444 address &= 0x1FFFF; \
445 if(address > 0x18000) \
448 value = address##type(vram, address); \
453 value = address##type(oam_ram, address & 0x3FF); \
462 if((address & 0x1FFFFFF) >= gamepak_size) \
468 read_memory_gamepak(type); \
473 if((address & 0x1FFFFFF) < gamepak_size) \
475 read_memory_gamepak(type); \
479 value = read_eeprom(); \
486 read_backup##type(); \
494 #define trigger_dma(dma_number) \
497 if(dma[dma_number].start_type == DMA_INACTIVE) \
499 u32 start_type = (value >> 12) & 0x03; \
500 u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) & \
503 dma[dma_number].dma_channel = dma_number; \
504 dma[dma_number].source_address = \
505 address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF; \
506 dma[dma_number].dest_address = dest_address; \
507 dma[dma_number].source_direction = (value >> 7) & 0x03; \
508 dma[dma_number].repeat_type = (value >> 9) & 0x01; \
509 dma[dma_number].start_type = start_type; \
510 dma[dma_number].irq = (value >> 14) & 0x01; \
512 /* If it is sound FIFO DMA make sure the settings are a certain way */ \
513 if((dma_number >= 1) && (dma_number <= 2) && \
514 (start_type == DMA_START_SPECIAL)) \
516 dma[dma_number].length_type = DMA_32BIT; \
517 dma[dma_number].length = 4; \
518 dma[dma_number].dest_direction = DMA_FIXED; \
519 if(dest_address == 0x40000A4) \
520 dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B; \
522 dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A; \
527 address16(io_registers, (dma_number * 12) + 0xB8); \
529 if((dma_number == 3) && ((dest_address >> 24) == 0x0D) && \
530 ((length & 0x1F) == 17)) \
532 eeprom_size = EEPROM_8_KBYTE; \
540 if(dma_number == 3) \
546 dma[dma_number].length = length; \
547 dma[dma_number].length_type = (value >> 10) & 0x01; \
548 dma[dma_number].dest_direction = (value >> 5) & 0x03; \
551 address16(io_registers, (dma_number * 12) + 0xBA) = value; \
552 if(start_type == DMA_START_IMMEDIATELY) \
553 return dma_transfer(dma + dma_number); \
558 dma[dma_number].start_type = DMA_INACTIVE; \
559 dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND; \
560 address16(io_registers, (dma_number * 12) + 0xBA) = value; \
564 #define access_register8_high(address) \
565 value = (value << 8) | (address8(io_registers, address)) \
567 #define access_register8_low(address) \
568 value = ((address8(io_registers, address + 1)) << 8) | value \
570 #define access_register16_high(address) \
571 value = (value << 16) | (address16(io_registers, address)) \
573 #define access_register16_low(address) \
574 value = ((address16(io_registers, address + 2)) << 16) | value \
576 cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
582 u32 dispcnt = io_registers[REG_DISPCNT];
584 if((value & 0x07) != (dispcnt & 0x07))
587 address8(io_registers, 0x00) = value;
591 // DISPSTAT (lower byte)
593 address8(io_registers, 0x04) =
594 (address8(io_registers, 0x04) & 0x07) | (value & ~0x07);
604 access_register8_low(0x28);
605 access_register16_low(0x28);
606 affine_reference_x[0] = (s32)(value << 4) >> 4;
607 address32(io_registers, 0x28) = value;
611 access_register8_high(0x28);
612 access_register16_low(0x28);
613 affine_reference_x[0] = (s32)(value << 4) >> 4;
614 address32(io_registers, 0x28) = value;
618 access_register8_low(0x2A);
619 access_register16_high(0x28);
620 affine_reference_x[0] = (s32)(value << 4) >> 4;
621 address32(io_registers, 0x28) = value;
625 access_register8_high(0x2A);
626 access_register16_high(0x28);
627 affine_reference_x[0] = (s32)(value << 4) >> 4;
628 address32(io_registers, 0x28) = value;
633 access_register8_low(0x2C);
634 access_register16_low(0x2C);
635 affine_reference_y[0] = (s32)(value << 4) >> 4;
636 address32(io_registers, 0x2C) = value;
640 access_register8_high(0x2C);
641 access_register16_low(0x2C);
642 affine_reference_y[0] = (s32)(value << 4) >> 4;
643 address32(io_registers, 0x2C) = value;
647 access_register8_low(0x2E);
648 access_register16_high(0x2C);
649 affine_reference_y[0] = (s32)(value << 4) >> 4;
650 address32(io_registers, 0x2C) = value;
654 access_register8_high(0x2E);
655 access_register16_high(0x2C);
656 affine_reference_y[0] = (s32)(value << 4) >> 4;
657 address32(io_registers, 0x2C) = value;
662 access_register8_low(0x38);
663 access_register16_low(0x38);
664 affine_reference_x[1] = (s32)(value << 4) >> 4;
665 address32(io_registers, 0x38) = value;
669 access_register8_high(0x38);
670 access_register16_low(0x38);
671 affine_reference_x[1] = (s32)(value << 4) >> 4;
672 address32(io_registers, 0x38) = value;
676 access_register8_low(0x3A);
677 access_register16_high(0x38);
678 affine_reference_x[1] = (s32)(value << 4) >> 4;
679 address32(io_registers, 0x38) = value;
683 access_register8_high(0x3A);
684 access_register16_high(0x38);
685 affine_reference_x[1] = (s32)(value << 4) >> 4;
686 address32(io_registers, 0x38) = value;
691 access_register8_low(0x3C);
692 access_register16_low(0x3C);
693 affine_reference_y[1] = (s32)(value << 4) >> 4;
694 address32(io_registers, 0x3C) = value;
698 access_register8_high(0x3C);
699 access_register16_low(0x3C);
700 affine_reference_y[1] = (s32)(value << 4) >> 4;
701 address32(io_registers, 0x3C) = value;
705 access_register8_low(0x3E);
706 access_register16_high(0x3C);
707 affine_reference_y[1] = (s32)(value << 4) >> 4;
708 address32(io_registers, 0x3C) = value;
712 access_register8_high(0x3E);
713 access_register16_high(0x3C);
714 affine_reference_y[1] = (s32)(value << 4) >> 4;
715 address32(io_registers, 0x3C) = value;
718 // Sound 1 control sweep
720 access_register8_low(0x60);
721 gbc_sound_tone_control_sweep();
725 access_register8_low(0x60);
726 gbc_sound_tone_control_sweep();
729 // Sound 1 control duty/length/envelope
731 access_register8_low(0x62);
732 gbc_sound_tone_control_low(0, 0x62);
736 access_register8_high(0x62);
737 gbc_sound_tone_control_low(0, 0x62);
740 // Sound 1 control frequency
742 access_register8_low(0x64);
743 gbc_sound_tone_control_high(0, 0x64);
747 access_register8_high(0x64);
748 gbc_sound_tone_control_high(0, 0x64);
751 // Sound 2 control duty/length/envelope
753 access_register8_low(0x68);
754 gbc_sound_tone_control_low(1, 0x68);
758 access_register8_high(0x68);
759 gbc_sound_tone_control_low(1, 0x68);
762 // Sound 2 control frequency
764 access_register8_low(0x6C);
765 gbc_sound_tone_control_high(1, 0x6C);
769 access_register8_high(0x6C);
770 gbc_sound_tone_control_high(1, 0x6C);
773 // Sound 3 control wave
775 access_register8_low(0x70);
776 gbc_sound_wave_control();
780 access_register8_high(0x70);
781 gbc_sound_wave_control();
784 // Sound 3 control length/volume
786 access_register8_low(0x72);
787 gbc_sound_tone_control_low_wave();
791 access_register8_high(0x72);
792 gbc_sound_tone_control_low_wave();
795 // Sound 3 control frequency
797 access_register8_low(0x74);
798 gbc_sound_tone_control_high_wave();
802 access_register8_high(0x74);
803 gbc_sound_tone_control_high_wave();
806 // Sound 4 control length/envelope
808 access_register8_low(0x78);
809 gbc_sound_tone_control_low(3, 0x78);
813 access_register8_high(0x78);
814 gbc_sound_tone_control_low(3, 0x78);
817 // Sound 4 control frequency
819 access_register8_low(0x7C);
820 gbc_sound_noise_control();
824 access_register8_high(0x7C);
825 gbc_sound_noise_control();
830 access_register8_low(0x80);
835 access_register8_high(0x80);
841 access_register8_low(0x82);
846 access_register8_high(0x82);
857 gbc_sound_wave_update = 1;
858 address8(io_registers, address) = value;
863 sound_timer_queue8(0, value);
868 sound_timer_queue8(1, value);
871 // DMA control (trigger byte)
873 access_register8_low(0xBA);
878 access_register8_low(0xC6);
883 access_register8_low(0xD2);
888 access_register8_low(0xDE);
894 access_register8_low(0x100);
899 access_register8_high(0x100);
904 access_register8_low(0x104);
909 access_register8_high(0x104);
914 access_register8_low(0x108);
919 access_register8_high(0x108);
924 access_register8_low(0x10C);
929 access_register8_high(0x10C);
933 // Timer control (trigger byte)
935 access_register8_low(0x102);
940 access_register8_low(0x106);
945 access_register8_low(0x10A);
950 access_register8_low(0x10E);
956 address8(io_registers, 0x202) &= ~value;
960 address8(io_registers, 0x203) &= ~value;
965 if((value & 0x01) == 0)
966 reg[CPU_HALT_STATE] = CPU_HALT;
968 reg[CPU_HALT_STATE] = CPU_STOP;
970 return CPU_ALERT_HALT;
974 address8(io_registers, address) = value;
978 return CPU_ALERT_NONE;
981 cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
987 u32 dispcnt = io_registers[REG_DISPCNT];
988 if((value & 0x07) != (dispcnt & 0x07))
991 address16(io_registers, 0x00) = value;
997 address16(io_registers, 0x04) =
998 (address16(io_registers, 0x04) & 0x07) | (value & ~0x07);
1007 access_register16_low(0x28);
1008 affine_reference_x[0] = (s32)(value << 4) >> 4;
1009 address32(io_registers, 0x28) = value;
1013 access_register16_high(0x28);
1014 affine_reference_x[0] = (s32)(value << 4) >> 4;
1015 address32(io_registers, 0x28) = value;
1020 access_register16_low(0x2C);
1021 affine_reference_y[0] = (s32)(value << 4) >> 4;
1022 address32(io_registers, 0x2C) = value;
1026 access_register16_high(0x2C);
1027 affine_reference_y[0] = (s32)(value << 4) >> 4;
1028 address32(io_registers, 0x2C) = value;
1034 access_register16_low(0x38);
1035 affine_reference_x[1] = (s32)(value << 4) >> 4;
1036 address32(io_registers, 0x38) = value;
1040 access_register16_high(0x38);
1041 affine_reference_x[1] = (s32)(value << 4) >> 4;
1042 address32(io_registers, 0x38) = value;
1047 access_register16_low(0x3C);
1048 affine_reference_y[1] = (s32)(value << 4) >> 4;
1049 address32(io_registers, 0x3C) = value;
1053 access_register16_high(0x3C);
1054 affine_reference_y[1] = (s32)(value << 4) >> 4;
1055 address32(io_registers, 0x3C) = value;
1058 // Sound 1 control sweep
1060 gbc_sound_tone_control_sweep();
1063 // Sound 1 control duty/length/envelope
1065 gbc_sound_tone_control_low(0, 0x62);
1068 // Sound 1 control frequency
1070 gbc_sound_tone_control_high(0, 0x64);
1073 // Sound 2 control duty/length/envelope
1075 gbc_sound_tone_control_low(1, 0x68);
1078 // Sound 2 control frequency
1080 gbc_sound_tone_control_high(1, 0x6C);
1083 // Sound 3 control wave
1085 gbc_sound_wave_control();
1088 // Sound 3 control length/volume
1090 gbc_sound_tone_control_low_wave();
1093 // Sound 3 control frequency
1095 gbc_sound_tone_control_high_wave();
1098 // Sound 4 control length/envelope
1100 gbc_sound_tone_control_low(3, 0x78);
1103 // Sound 4 control frequency
1105 gbc_sound_noise_control();
1110 gbc_trigger_sound();
1125 gbc_sound_wave_update = 1;
1126 address16(io_registers, address) = value;
1131 sound_timer_queue16(0, value);
1136 sound_timer_queue16(1, value);
1196 address16(io_registers, 0x202) &= ~value;
1205 if(((value >> 8) & 0x01) == 0)
1206 reg[CPU_HALT_STATE] = CPU_HALT;
1208 reg[CPU_HALT_STATE] = CPU_STOP;
1210 return CPU_ALERT_HALT;
1213 address16(io_registers, address) = value;
1217 return CPU_ALERT_NONE;
1221 cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
1227 affine_reference_x[0] = (s32)(value << 4) >> 4;
1228 address32(io_registers, 0x28) = value;
1233 affine_reference_y[0] = (s32)(value << 4) >> 4;
1234 address32(io_registers, 0x2C) = value;
1239 affine_reference_x[1] = (s32)(value << 4) >> 4;
1240 address32(io_registers, 0x38) = value;
1245 affine_reference_y[1] = (s32)(value << 4) >> 4;
1246 address32(io_registers, 0x3C) = value;
1251 sound_timer_queue32(0, value);
1256 sound_timer_queue32(1, value);
1261 cpu_alert_type alert_low =
1262 write_io_register16(address, value & 0xFFFF);
1264 cpu_alert_type alert_high =
1265 write_io_register16(address + 2, value >> 16);
1274 return CPU_ALERT_NONE;
1277 #define write_palette8(address, value) \
1279 #define write_palette16(address, value) \
1281 u32 palette_address = address; \
1282 address16(palette_ram, palette_address) = value; \
1283 convert_palette(value); \
1284 address16(palette_ram_converted, palette_address) = value; \
1287 #define write_palette32(address, value) \
1289 u32 palette_address = address; \
1290 u32 value_high = value >> 16; \
1291 u32 value_low = value & 0xFFFF; \
1292 address32(palette_ram, palette_address) = value; \
1293 convert_palette(value_high); \
1294 convert_palette(value_low); \
1295 value = (value_high << 16) | value_low; \
1296 address32(palette_ram_converted, palette_address) = value; \
1300 void function_cc write_backup(u32 address, u32 value)
1304 if(backup_type == BACKUP_NONE)
1305 backup_type = BACKUP_SRAM;
1308 // gamepak SRAM or Flash ROM
1309 if((address == 0x5555) && (flash_mode != FLASH_WRITE_MODE))
1311 if((flash_command_position == 0) && (value == 0xAA))
1313 backup_type = BACKUP_FLASH;
1314 flash_command_position = 1;
1317 if(flash_command_position == 2)
1322 // Enter ID mode, this also tells the emulator that we're using
1325 if(flash_mode == FLASH_BASE_MODE)
1326 flash_mode = FLASH_ID_MODE;
1332 if(flash_mode == FLASH_BASE_MODE)
1333 flash_mode = FLASH_ERASE_MODE;
1337 // Terminate ID mode
1338 if(flash_mode == FLASH_ID_MODE)
1339 flash_mode = FLASH_BASE_MODE;
1344 if(flash_mode == FLASH_BASE_MODE)
1345 flash_mode = FLASH_WRITE_MODE;
1350 // Here the chip is now officially 128KB.
1351 flash_size = FLASH_SIZE_128KB;
1352 if(flash_mode == FLASH_BASE_MODE)
1353 flash_mode = FLASH_BANKSWITCH_MODE;
1358 if(flash_mode == FLASH_ERASE_MODE)
1360 if(flash_size == FLASH_SIZE_64KB)
1361 memset(gamepak_backup, 0xFF, 1024 * 64);
1363 memset(gamepak_backup, 0xFF, 1024 * 128);
1364 backup_update = write_backup_delay;
1365 flash_mode = FLASH_BASE_MODE;
1372 flash_command_position = 0;
1374 if(backup_type == BACKUP_SRAM)
1375 gamepak_backup[0x5555] = value;
1379 if((address == 0x2AAA) && (value == 0x55) &&
1380 (flash_command_position == 1))
1382 flash_command_position = 2;
1386 if((flash_command_position == 2) &&
1387 (flash_mode == FLASH_ERASE_MODE) && (value == 0x30))
1390 memset(flash_bank_ptr + (address & 0xF000), 0xFF, 1024 * 4);
1391 backup_update = write_backup_delay;
1392 flash_mode = FLASH_BASE_MODE;
1393 flash_command_position = 0;
1397 if((flash_command_position == 0) &&
1398 (flash_mode == FLASH_BANKSWITCH_MODE) && (address == 0x0000) &&
1399 (flash_size == FLASH_SIZE_128KB))
1401 flash_bank_ptr = gamepak_backup + ((value & 0x01) * (1024 * 64));
1402 flash_mode = FLASH_BASE_MODE;
1406 if((flash_command_position == 0) && (flash_mode == FLASH_WRITE_MODE))
1408 // Write value to flash ROM
1409 backup_update = write_backup_delay;
1410 flash_bank_ptr[address] = value;
1411 flash_mode = FLASH_BASE_MODE;
1415 if(backup_type == BACKUP_SRAM)
1417 // Write value to SRAM
1418 backup_update = write_backup_delay;
1419 // Hit 64KB territory?
1420 if(address >= 0x8000)
1421 sram_size = SRAM_SIZE_64KB;
1422 gamepak_backup[address] = value;
1427 #define write_backup8() \
1428 write_backup(address & 0xFFFF, value) \
1430 #define write_backup16() \
1432 #define write_backup32() \
1434 #define write_vram8() \
1436 address16(vram, address) = ((value << 8) | value) \
1438 #define write_vram16() \
1439 address16(vram, address) = value \
1441 #define write_vram32() \
1442 address32(vram, address) = value \
1444 // RTC code derived from VBA's (due to lack of any real publically available
1445 // documentation...)
1458 RTC_COMMAND_RESET = 0x60,
1459 RTC_COMMAND_WRITE_STATUS = 0x62,
1460 RTC_COMMAND_READ_STATUS = 0x63,
1461 RTC_COMMAND_OUTPUT_TIME_FULL = 0x65,
1462 RTC_COMMAND_OUTPUT_TIME = 0x67
1468 RTC_WRITE_TIME_FULL,
1470 } rtc_write_mode_type;
1472 rtc_state_type rtc_state = RTC_DISABLED;
1473 rtc_write_mode_type rtc_write_mode;
1474 u8 rtc_registers[3];
1477 u32 rtc_status = 0x40;
1481 u32 encode_bcd(u8 value)
1483 return ((value / 10) << 4) | (value % 10);
1486 #define write_rtc_register(index, _value) \
1487 update_address = 0x80000C4 + (index * 2); \
1488 rtc_registers[index] = _value; \
1489 rtc_page_index = update_address >> 15; \
1490 map = memory_map_read[rtc_page_index]; \
1493 map = load_gamepak_page(rtc_page_index & 0x3FF); \
1495 address16(map, update_address & 0x7FFF) = _value \
1497 void function_cc write_rtc(u32 address, u32 value)
1508 // Bit 0: SCHK, perform action
1509 // Bit 1: IO, input/output command data
1510 // Bit 2: CS, select input/output? If high make I/O write only
1512 if(rtc_state == RTC_DISABLED)
1513 rtc_state = RTC_IDLE;
1514 if(!(rtc_registers[0] & 0x04))
1515 value = (rtc_registers[0] & 0x02) | (value & ~0x02);
1516 if(rtc_registers[2] & 0x01)
1518 // To begin writing a command 1, 5 must be written to the command
1520 if((rtc_state == RTC_IDLE) && (rtc_registers[0] == 0x01) &&
1523 // We're now ready to begin receiving a command.
1524 write_rtc_register(0, value);
1525 rtc_state = RTC_COMMAND;
1531 write_rtc_register(0, value);
1534 // Accumulate RTC command by receiving the next bit, and if we
1535 // have accumulated enough bits to form a complete command
1538 if(rtc_registers[0] & 0x01)
1540 rtc_command |= ((value & 0x02) >> 1) << rtc_bit_count;
1544 // Have we received a full RTC command? If so execute it.
1545 if(rtc_bit_count < 0)
1550 case RTC_COMMAND_RESET:
1551 rtc_state = RTC_IDLE;
1552 memset(rtc_registers, 0, sizeof(rtc_registers));
1555 // Sets status of RTC
1556 case RTC_COMMAND_WRITE_STATUS:
1557 rtc_state = RTC_INPUT_DATA;
1559 rtc_write_mode = RTC_WRITE_STATUS;
1562 // Outputs current status of RTC
1563 case RTC_COMMAND_READ_STATUS:
1564 rtc_state = RTC_OUTPUT_DATA;
1566 rtc_data[0] = rtc_status;
1569 // Actually outputs the time, all of it
1570 case RTC_COMMAND_OUTPUT_TIME_FULL:
1572 struct tm *current_time;
1573 time_t current_time_flat;
1576 time(¤t_time_flat);
1577 current_time = localtime(¤t_time_flat);
1579 day_of_week = current_time->tm_wday;
1580 if(day_of_week == 0)
1585 rtc_state = RTC_OUTPUT_DATA;
1587 rtc_data[0] = encode_bcd(current_time->tm_year % 100);
1588 rtc_data[1] = encode_bcd(current_time->tm_mon + 1);
1589 rtc_data[2] = encode_bcd(current_time->tm_mday);
1590 rtc_data[3] = encode_bcd(day_of_week);
1591 rtc_data[4] = encode_bcd(current_time->tm_hour);
1592 rtc_data[5] = encode_bcd(current_time->tm_min);
1593 rtc_data[6] = encode_bcd(current_time->tm_sec);
1598 // Only outputs the current time of day.
1599 case RTC_COMMAND_OUTPUT_TIME:
1601 struct tm *current_time;
1602 time_t current_time_flat;
1604 time(¤t_time_flat);
1605 current_time = localtime(¤t_time_flat);
1607 rtc_state = RTC_OUTPUT_DATA;
1609 rtc_data[0] = encode_bcd(current_time->tm_hour);
1610 rtc_data[1] = encode_bcd(current_time->tm_min);
1611 rtc_data[2] = encode_bcd(current_time->tm_sec);
1619 // Receive parameters from the game as input to the RTC
1620 // for a given command. Read one bit at a time.
1621 case RTC_INPUT_DATA:
1622 // Bit 1 of parameter A must be high for input
1623 if(rtc_registers[1] & 0x02)
1625 // Read next bit for input
1628 rtc_data[rtc_bit_count >> 3] |=
1629 ((value & 0x01) << (7 - (rtc_bit_count & 0x07)));
1635 if(rtc_bit_count == (rtc_data_bytes * 8))
1637 rtc_state = RTC_IDLE;
1638 switch(rtc_write_mode)
1640 case RTC_WRITE_STATUS:
1641 rtc_status = rtc_data[0];
1652 case RTC_OUTPUT_DATA:
1653 // Bit 1 of parameter A must be low for output
1654 if(!(rtc_registers[1] & 0x02))
1656 // Write next bit to output, on bit 1 of parameter B
1659 u8 current_output_byte = rtc_registers[2];
1661 current_output_byte =
1662 (current_output_byte & ~0x02) |
1663 (((rtc_data[rtc_bit_count >> 3] >>
1664 (rtc_bit_count & 0x07)) & 0x01) << 1);
1666 write_rtc_register(0, current_output_byte);
1673 if(rtc_bit_count == (rtc_data_bytes * 8))
1675 rtc_state = RTC_IDLE;
1676 memset(rtc_registers, 0, sizeof(rtc_registers));
1689 write_rtc_register(2, value);
1693 // Write parameter A
1695 write_rtc_register(1, value);
1698 // Write parameter B
1700 write_rtc_register(2, value);
1705 #define write_rtc8() \
1707 #define write_rtc16() \
1708 write_rtc(address & 0xFF, value) \
1710 #define write_rtc32() \
1712 #define write_memory(type) \
1713 switch(address >> 24) \
1716 /* external work RAM */ \
1717 address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \
1718 address##type(ewram, address) = value; \
1722 /* internal work RAM */ \
1723 address##type(iwram, (address & 0x7FFF) + 0x8000) = value; \
1727 /* I/O registers */ \
1728 return write_io_register##type(address & 0x3FF, value); \
1732 write_palette##type(address & 0x3FF, value); \
1737 address &= 0x1FFFF; \
1738 if(address >= 0x18000) \
1739 address -= 0x8000; \
1741 write_vram##type(); \
1747 address##type(oam_ram, address & 0x3FF) = value; \
1751 /* gamepak ROM or RTC */ \
1752 write_rtc##type(); \
1755 case 0x09 ... 0x0C: \
1756 /* gamepak ROM space */ \
1760 write_eeprom(address, value); \
1764 write_backup##type(); \
1768 u8 function_cc read_memory8(u32 address)
1775 u16 function_cc read_memory16_signed(u32 address)
1781 return (s8)read_memory8(address);
1791 // unaligned reads are actually 32bit
1793 u32 function_cc read_memory16(u32 address)
1801 ror(value, value, 8);
1812 u32 function_cc read_memory32(u32 address)
1817 u32 rotate = (address & 0x03) * 8;
1820 ror(value, value, rotate);
1830 cpu_alert_type function_cc write_memory8(u32 address, u8 value)
1833 return CPU_ALERT_NONE;
1836 cpu_alert_type function_cc write_memory16(u32 address, u16 value)
1839 return CPU_ALERT_NONE;
1842 cpu_alert_type function_cc write_memory32(u32 address, u32 value)
1845 return CPU_ALERT_NONE;
1848 char backup_filename[512];
1850 u32 load_backup(char *name)
1852 file_open(backup_file, name, read);
1854 if(file_check_valid(backup_file))
1856 u32 backup_size = file_length(name, backup_file);
1858 file_read(backup_file, gamepak_backup, backup_size);
1860 file_close(backup_file);
1862 // The size might give away what kind of backup it is.
1866 backup_type = BACKUP_EEPROM;
1867 eeprom_size = EEPROM_512_BYTE;
1871 backup_type = BACKUP_EEPROM;
1872 eeprom_size = EEPROM_8_KBYTE;
1876 backup_type = BACKUP_SRAM;
1877 sram_size = SRAM_SIZE_32KB;
1880 // Could be either flash or SRAM, go with flash
1882 backup_type = BACKUP_FLASH;
1883 sram_size = FLASH_SIZE_64KB;
1887 backup_type = BACKUP_FLASH;
1888 flash_size = FLASH_SIZE_128KB;
1895 backup_type = BACKUP_NONE;
1896 memset(gamepak_backup, 0xFF, 1024 * 128);
1902 u32 save_backup(char *name)
1904 if(backup_type != BACKUP_NONE)
1906 file_open(backup_file, name, write);
1908 if(file_check_valid(backup_file))
1910 u32 backup_size = 0;
1915 if(sram_size == SRAM_SIZE_32KB)
1916 backup_size = 0x8000;
1918 backup_size = 0x10000;
1922 if(flash_size == FLASH_SIZE_64KB)
1923 backup_size = 0x10000;
1925 backup_size = 0x20000;
1929 if(eeprom_size == EEPROM_512_BYTE)
1930 backup_size = 0x200;
1932 backup_size = 0x2000;
1939 file_write(backup_file, gamepak_backup, backup_size);
1941 file_close(backup_file);
1949 void update_backup()
1951 if(backup_update != (write_backup_delay + 1))
1954 if(backup_update == 0)
1956 save_backup(backup_filename);
1957 backup_update = write_backup_delay + 1;
1961 void update_backup_force()
1963 save_backup(backup_filename);
1966 #define CONFIG_FILENAME "game_config.txt"
1968 char *skip_spaces(char *line_ptr)
1970 while(*line_ptr == ' ')
1976 s32 parse_config_line(char *current_line, char *current_variable, char *current_value)
1978 char *line_ptr = current_line;
1981 if((current_line[0] == 0) || (current_line[0] == '#'))
1984 line_ptr_new = strchr(line_ptr, ' ');
1985 if(line_ptr_new == NULL)
1989 strcpy(current_variable, line_ptr);
1990 line_ptr_new = skip_spaces(line_ptr_new + 1);
1992 if(*line_ptr_new != '=')
1995 line_ptr_new = skip_spaces(line_ptr_new + 1);
1996 strcpy(current_value, line_ptr_new);
1997 line_ptr_new = current_value + strlen(current_value) - 1;
1998 if(*line_ptr_new == '\n')
2004 if(*line_ptr_new == '\r')
2010 s32 load_game_config(char *gamepak_title, char *gamepak_code, char *gamepak_maker)
2012 char current_line[256];
2013 char current_variable[256];
2014 char current_value[256];
2015 char config_path[512];
2018 idle_loop_target_pc = 0xFFFFFFFF;
2019 iwram_stack_optimize = 1;
2020 bios_rom[0x39] = 0x00;
2021 bios_rom[0x2C] = 0x00;
2022 translation_gate_targets = 0;
2023 flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
2025 sprintf(config_path, "%s" PATH_SEPARATOR "%s", main_path, CONFIG_FILENAME);
2027 config_file = fopen(config_path, "rb");
2031 while(fgets(current_line, 256, config_file))
2033 if(parse_config_line(current_line, current_variable, current_value)
2036 if(strcmp(current_variable, "game_name") ||
2037 strcmp(current_value, gamepak_title))
2040 if(!fgets(current_line, 256, config_file) ||
2041 (parse_config_line(current_line, current_variable,
2042 current_value) == -1) ||
2043 strcmp(current_variable, "game_code") ||
2044 strcmp(current_value, gamepak_code))
2047 if(!fgets(current_line, 256, config_file) ||
2048 (parse_config_line(current_line, current_variable,
2049 current_value) == -1) ||
2050 strcmp(current_variable, "vender_code") ||
2051 strcmp(current_value, gamepak_maker))
2054 while(fgets(current_line, 256, config_file))
2056 if(parse_config_line(current_line, current_variable, current_value)
2059 if(!strcmp(current_variable, "game_name"))
2061 fclose(config_file);
2065 if(!strcmp(current_variable, "idle_loop_eliminate_target"))
2066 idle_loop_target_pc = strtol(current_value, NULL, 16);
2068 if(!strcmp(current_variable, "translation_gate_target"))
2070 if(translation_gate_targets < MAX_TRANSLATION_GATES)
2072 translation_gate_target_pc[translation_gate_targets] =
2073 strtol(current_value, NULL, 16);
2074 translation_gate_targets++;
2078 if(!strcmp(current_variable, "iwram_stack_optimize") &&
2079 !strcmp(current_value, "no\0")) /* \0 for broken toolchain workaround */
2081 iwram_stack_optimize = 0;
2084 if(!strcmp(current_variable, "flash_rom_type") &&
2085 !strcmp(current_value, "128KB"))
2087 flash_device_id = FLASH_DEVICE_MACRONIX_128KB;
2090 if(!strcmp(current_variable, "bios_rom_hack_39") &&
2091 !strcmp(current_value, "yes"))
2093 bios_rom[0x39] = 0xC0;
2096 if(!strcmp(current_variable, "bios_rom_hack_2C") &&
2097 !strcmp(current_value, "yes"))
2099 bios_rom[0x2C] = 0x02;
2104 fclose(config_file);
2109 fclose(config_file);
2113 printf("game config missing\n");
2118 s32 load_gamepak_raw(char *name)
2120 file_open(gamepak_file, name, read);
2122 if(file_check_valid(gamepak_file))
2124 u32 file_size = file_length(name, gamepak_file);
2126 // First, close the last one if it was open, we won't
2127 // be needing it anymore.
2128 if(file_check_valid(gamepak_file_large))
2129 file_close(gamepak_file_large);
2131 // If it's a big file size keep it, don't close it, we'll
2132 // probably want to load from it more later.
2133 if(file_size <= gamepak_ram_buffer_size)
2135 file_read(gamepak_file, gamepak_rom, file_size);
2137 file_close(gamepak_file);
2140 gamepak_file_large = -1;
2142 gamepak_file_large = NULL;
2147 // Read in just enough for the header
2148 file_read(gamepak_file, gamepak_rom, 0x100);
2149 gamepak_file_large = gamepak_file;
2158 char gamepak_title[13];
2159 char gamepak_code[5];
2160 char gamepak_maker[3];
2161 char gamepak_filename[512];
2163 u32 load_gamepak(char *name)
2165 char *dot_position = strrchr(name, '.');
2167 char cheats_filename[256];
2170 file_size = wiz_load_gamepak(name);
2172 if(!strcmp(dot_position, ".zip"))
2173 file_size = load_file_zip(name);
2175 file_size = load_gamepak_raw(name);
2178 // A dumb April fool's joke was here once :o
2182 gamepak_size = (file_size + 0x7FFF) & ~0x7FFF;
2184 strncpy(gamepak_filename, name, sizeof(gamepak_filename));
2185 gamepak_filename[sizeof(gamepak_filename) - 1] = 0;
2187 make_rpath(backup_filename, sizeof(backup_filename), ".sav");
2188 if (!load_backup(backup_filename))
2190 // try path used by older versions
2191 strcpy(backup_filename, name);
2192 change_ext(gamepak_filename, backup_filename, ".sav");
2193 load_backup(backup_filename);
2196 memcpy(gamepak_title, gamepak_rom + 0xA0, 12);
2197 memcpy(gamepak_code, gamepak_rom + 0xAC, 4);
2198 memcpy(gamepak_maker, gamepak_rom + 0xB0, 2);
2199 gamepak_title[12] = 0;
2200 gamepak_code[4] = 0;
2201 gamepak_maker[2] = 0;
2203 load_game_config(gamepak_title, gamepak_code, gamepak_maker);
2204 load_game_config_file();
2206 change_ext(gamepak_filename, cheats_filename, ".cht");
2207 add_cheats(cheats_filename);
2215 s32 load_bios(char *name)
2217 file_open(bios_file, name, read);
2219 if(file_check_valid(bios_file))
2221 file_read(bios_file, bios_rom, 0x4000);
2223 // This is a hack to get Zelda working, because emulating
2224 // the proper memory read behavior here is much too expensive.
2225 file_close(bios_file);
2232 // DMA memory regions can be one of the following:
2233 // IWRAM - 32kb offset from the contiguous iwram region.
2234 // EWRAM - like segmented but with self modifying code check.
2235 // VRAM - 96kb offset from the contiguous vram region, should take care
2236 // Palette RAM - Converts palette entries when written to.
2237 // OAM RAM - Sets OAM modified flag to true.
2238 // I/O registers - Uses the I/O register function.
2239 // of mirroring properly.
2240 // Segmented RAM/ROM - a region >= 32kb, the translated address has to
2241 // be reloaded if it wraps around the limit (cartride ROM)
2242 // Ext - should be handled by the memory read/write function.
2244 // The following map determines the region of each (assumes DMA access
2245 // is not done out of bounds)
2252 DMA_REGION_PALETTE_RAM,
2261 dma_region_type dma_region_map[16] =
2263 DMA_REGION_BIOS, // 0x00 - BIOS
2264 DMA_REGION_NULL, // 0x01 - Nothing
2265 DMA_REGION_EWRAM, // 0x02 - EWRAM
2266 DMA_REGION_IWRAM, // 0x03 - IWRAM
2267 DMA_REGION_IO, // 0x04 - I/O registers
2268 DMA_REGION_PALETTE_RAM, // 0x05 - palette RAM
2269 DMA_REGION_VRAM, // 0x06 - VRAM
2270 DMA_REGION_OAM_RAM, // 0x07 - OAM RAM
2271 DMA_REGION_GAMEPAK, // 0x08 - gamepak ROM
2272 DMA_REGION_GAMEPAK, // 0x09 - gamepak ROM
2273 DMA_REGION_GAMEPAK, // 0x0A - gamepak ROM
2274 DMA_REGION_GAMEPAK, // 0x0B - gamepak ROM
2275 DMA_REGION_GAMEPAK, // 0x0C - gamepak ROM
2276 DMA_REGION_EXT, // 0x0D - EEPROM
2277 DMA_REGION_EXT, // 0x0E - gamepak SRAM/flash ROM
2278 DMA_REGION_EXT // 0x0F - gamepak SRAM/flash ROM
2281 #define dma_adjust_ptr_inc(ptr, size) \
2284 #define dma_adjust_ptr_dec(ptr, size) \
2287 #define dma_adjust_ptr_fix(ptr, size) \
2289 #define dma_adjust_ptr_writeback() \
2290 dma->dest_address = dest_ptr \
2292 #define dma_adjust_ptr_reload() \
2294 #define dma_print(src_op, dest_op, transfer_size, wb) \
2295 printf("dma from %x (%s) to %x (%s) for %x (%s) (%s) (%d) (pc %x)\n", \
2296 src_ptr, #src_op, dest_ptr, #dest_op, length, #transfer_size, #wb, \
2297 dma->irq, reg[15]); \
2299 #define dma_smc_vars_src() \
2301 #define dma_smc_vars_dest() \
2302 u32 smc_trigger = 0 \
2304 #define dma_vars_iwram(type) \
2305 dma_smc_vars_##type() \
2307 #define dma_vars_vram(type) \
2309 #define dma_vars_palette_ram(type) \
2311 #define dma_oam_ram_src() \
2313 #define dma_oam_ram_dest() \
2316 #define dma_vars_oam_ram(type) \
2317 dma_oam_ram_##type() \
2319 #define dma_vars_io(type) \
2321 #define dma_segmented_load_src() \
2322 memory_map_read[src_current_region] \
2324 #define dma_segmented_load_dest() \
2325 memory_map_write[dest_current_region] \
2327 #define dma_vars_gamepak(type) \
2328 u32 type##_new_region; \
2329 u32 type##_current_region = type##_ptr >> 15; \
2330 u8 *type##_address_block = dma_segmented_load_##type(); \
2331 if(type##_address_block == NULL) \
2333 if((type##_ptr & 0x1FFFFFF) >= gamepak_size) \
2335 type##_address_block = load_gamepak_page(type##_current_region & 0x3FF); \
2338 #define dma_vars_ewram(type) \
2339 dma_smc_vars_##type(); \
2340 u32 type##_new_region; \
2341 u32 type##_current_region = type##_ptr >> 15; \
2342 u8 *type##_address_block = dma_segmented_load_##type() \
2344 #define dma_vars_bios(type) \
2346 #define dma_vars_ext(type) \
2348 #define dma_ewram_check_region(type) \
2349 type##_new_region = (type##_ptr >> 15); \
2350 if(type##_new_region != type##_current_region) \
2352 type##_current_region = type##_new_region; \
2353 type##_address_block = dma_segmented_load_##type(); \
2356 #define dma_gamepak_check_region(type) \
2357 type##_new_region = (type##_ptr >> 15); \
2358 if(type##_new_region != type##_current_region) \
2360 type##_current_region = type##_new_region; \
2361 type##_address_block = dma_segmented_load_##type(); \
2362 if(type##_address_block == NULL) \
2364 type##_address_block = \
2365 load_gamepak_page(type##_current_region & 0x3FF); \
2369 #define dma_read_iwram(type, transfer_size) \
2370 read_value = address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) \
2372 #define dma_read_vram(type, transfer_size) \
2373 read_value = address##transfer_size(vram, type##_ptr & 0x1FFFF) \
2375 #define dma_read_io(type, transfer_size) \
2376 read_value = address##transfer_size(io_registers, type##_ptr & 0x7FFF) \
2378 #define dma_read_oam_ram(type, transfer_size) \
2379 read_value = address##transfer_size(oam_ram, type##_ptr & 0x3FF) \
2381 #define dma_read_palette_ram(type, transfer_size) \
2382 read_value = address##transfer_size(palette_ram, type##_ptr & 0x3FF) \
2384 #define dma_read_ewram(type, transfer_size) \
2385 dma_ewram_check_region(type); \
2386 read_value = address##transfer_size(type##_address_block, \
2387 type##_ptr & 0x7FFF) \
2389 #define dma_read_gamepak(type, transfer_size) \
2390 dma_gamepak_check_region(type); \
2391 read_value = address##transfer_size(type##_address_block, \
2392 type##_ptr & 0x7FFF) \
2394 // DMAing from the BIOS is funny, just returns 0..
2396 #define dma_read_bios(type, transfer_size) \
2399 #define dma_read_ext(type, transfer_size) \
2400 read_value = read_memory##transfer_size(type##_ptr) \
2402 #define dma_write_iwram(type, transfer_size) \
2403 address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) = read_value; \
2404 smc_trigger |= address##transfer_size(iwram, type##_ptr & 0x7FFF) \
2406 #define dma_write_vram(type, transfer_size) \
2407 address##transfer_size(vram, type##_ptr & 0x1FFFF) = read_value \
2409 #define dma_write_io(type, transfer_size) \
2410 write_io_register##transfer_size(type##_ptr & 0x3FF, read_value) \
2412 #define dma_write_oam_ram(type, transfer_size) \
2413 address##transfer_size(oam_ram, type##_ptr & 0x3FF) = read_value \
2415 #define dma_write_palette_ram(type, transfer_size) \
2416 write_palette##transfer_size(type##_ptr & 0x3FF, read_value) \
2418 #define dma_write_ext(type, transfer_size) \
2419 write_memory##transfer_size(type##_ptr, read_value) \
2421 #define dma_write_ewram(type, transfer_size) \
2422 dma_ewram_check_region(type); \
2424 address##transfer_size(type##_address_block, type##_ptr & 0x7FFF) = \
2426 smc_trigger |= address##transfer_size(type##_address_block, \
2427 (type##_ptr & 0x7FFF) - 0x8000) \
2429 #define dma_epilogue_iwram() \
2432 /* Special return code indicating to retranslate to the CPU code */ \
2433 return_value = CPU_ALERT_SMC; \
2436 #define dma_epilogue_ewram() \
2439 /* Special return code indicating to retranslate to the CPU code */ \
2440 return_value = CPU_ALERT_SMC; \
2443 #define dma_epilogue_vram() \
2445 #define dma_epilogue_io() \
2447 #define dma_epilogue_oam_ram() \
2449 #define dma_epilogue_palette_ram() \
2451 #define dma_epilogue_GAMEPAK() \
2453 #define dma_epilogue_ext() \
2455 #define print_line() \
2456 dma_print(src_op, dest_op, transfer_size, wb); \
2458 #define dma_transfer_loop_region(src_region_type, dest_region_type, src_op, \
2459 dest_op, transfer_size, wb) \
2461 dma_vars_##src_region_type(src); \
2462 dma_vars_##dest_region_type(dest); \
2464 for(i = 0; i < length; i++) \
2466 dma_read_##src_region_type(src, transfer_size); \
2467 dma_write_##dest_region_type(dest, transfer_size); \
2468 dma_adjust_ptr_##src_op(src_ptr, transfer_size); \
2469 dma_adjust_ptr_##dest_op(dest_ptr, transfer_size); \
2471 dma->source_address = src_ptr; \
2472 dma_adjust_ptr_##wb(); \
2473 dma_epilogue_##dest_region_type(); \
2477 #define dma_transfer_loop(src_op, dest_op, transfer_size, wb); \
2479 u32 src_region = src_ptr >> 24; \
2480 u32 dest_region = dest_ptr >> 24; \
2481 dma_region_type src_region_type = dma_region_map[src_region]; \
2482 dma_region_type dest_region_type = dma_region_map[dest_region]; \
2484 switch(src_region_type | (dest_region_type << 4)) \
2486 case (DMA_REGION_BIOS | (DMA_REGION_IWRAM << 4)): \
2487 dma_transfer_loop_region(bios, iwram, src_op, dest_op, \
2488 transfer_size, wb); \
2490 case (DMA_REGION_IWRAM | (DMA_REGION_IWRAM << 4)): \
2491 dma_transfer_loop_region(iwram, iwram, src_op, dest_op, \
2492 transfer_size, wb); \
2494 case (DMA_REGION_EWRAM | (DMA_REGION_IWRAM << 4)): \
2495 dma_transfer_loop_region(ewram, iwram, src_op, dest_op, \
2496 transfer_size, wb); \
2498 case (DMA_REGION_VRAM | (DMA_REGION_IWRAM << 4)): \
2499 dma_transfer_loop_region(vram, iwram, src_op, dest_op, \
2500 transfer_size, wb); \
2502 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IWRAM << 4)): \
2503 dma_transfer_loop_region(palette_ram, iwram, src_op, dest_op, \
2504 transfer_size, wb); \
2506 case (DMA_REGION_OAM_RAM | (DMA_REGION_IWRAM << 4)): \
2507 dma_transfer_loop_region(oam_ram, iwram, src_op, dest_op, \
2508 transfer_size, wb); \
2510 case (DMA_REGION_IO | (DMA_REGION_IWRAM << 4)): \
2511 dma_transfer_loop_region(io, iwram, src_op, dest_op, \
2512 transfer_size, wb); \
2514 case (DMA_REGION_GAMEPAK | (DMA_REGION_IWRAM << 4)): \
2515 dma_transfer_loop_region(gamepak, iwram, src_op, dest_op, \
2516 transfer_size, wb); \
2518 case (DMA_REGION_EXT | (DMA_REGION_IWRAM << 4)): \
2519 dma_transfer_loop_region(ext, iwram, src_op, dest_op, \
2520 transfer_size, wb); \
2522 case (DMA_REGION_BIOS | (DMA_REGION_EWRAM << 4)): \
2523 dma_transfer_loop_region(bios, ewram, src_op, dest_op, \
2524 transfer_size, wb); \
2526 case (DMA_REGION_IWRAM | (DMA_REGION_EWRAM << 4)): \
2527 dma_transfer_loop_region(iwram, ewram, src_op, dest_op, \
2528 transfer_size, wb); \
2530 case (DMA_REGION_EWRAM | (DMA_REGION_EWRAM << 4)): \
2531 dma_transfer_loop_region(ewram, ewram, src_op, dest_op, \
2532 transfer_size, wb); \
2534 case (DMA_REGION_VRAM | (DMA_REGION_EWRAM << 4)): \
2535 dma_transfer_loop_region(vram, ewram, src_op, dest_op, \
2536 transfer_size, wb); \
2538 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EWRAM << 4)): \
2539 dma_transfer_loop_region(palette_ram, ewram, src_op, dest_op, \
2540 transfer_size, wb); \
2542 case (DMA_REGION_OAM_RAM | (DMA_REGION_EWRAM << 4)): \
2543 dma_transfer_loop_region(oam_ram, ewram, src_op, dest_op, \
2544 transfer_size, wb); \
2546 case (DMA_REGION_IO | (DMA_REGION_EWRAM << 4)): \
2547 dma_transfer_loop_region(io, ewram, src_op, dest_op, \
2548 transfer_size, wb); \
2550 case (DMA_REGION_GAMEPAK | (DMA_REGION_EWRAM << 4)): \
2551 dma_transfer_loop_region(gamepak, ewram, src_op, dest_op, \
2552 transfer_size, wb); \
2554 case (DMA_REGION_EXT | (DMA_REGION_EWRAM << 4)): \
2555 dma_transfer_loop_region(ext, ewram, src_op, dest_op, \
2556 transfer_size, wb); \
2558 case (DMA_REGION_BIOS | (DMA_REGION_VRAM << 4)): \
2559 dma_transfer_loop_region(bios, vram, src_op, dest_op, \
2560 transfer_size, wb); \
2562 case (DMA_REGION_IWRAM | (DMA_REGION_VRAM << 4)): \
2563 dma_transfer_loop_region(iwram, vram, src_op, dest_op, \
2564 transfer_size, wb); \
2566 case (DMA_REGION_EWRAM | (DMA_REGION_VRAM << 4)): \
2567 dma_transfer_loop_region(ewram, vram, src_op, dest_op, \
2568 transfer_size, wb); \
2570 case (DMA_REGION_VRAM | (DMA_REGION_VRAM << 4)): \
2571 dma_transfer_loop_region(vram, vram, src_op, dest_op, \
2572 transfer_size, wb); \
2574 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_VRAM << 4)): \
2575 dma_transfer_loop_region(palette_ram, vram, src_op, dest_op, \
2576 transfer_size, wb); \
2578 case (DMA_REGION_OAM_RAM | (DMA_REGION_VRAM << 4)): \
2579 dma_transfer_loop_region(oam_ram, vram, src_op, dest_op, \
2580 transfer_size, wb); \
2582 case (DMA_REGION_IO | (DMA_REGION_VRAM << 4)): \
2583 dma_transfer_loop_region(io, vram, src_op, dest_op, \
2584 transfer_size, wb); \
2586 case (DMA_REGION_GAMEPAK | (DMA_REGION_VRAM << 4)): \
2587 dma_transfer_loop_region(gamepak, vram, src_op, dest_op, \
2588 transfer_size, wb); \
2590 case (DMA_REGION_EXT | (DMA_REGION_VRAM << 4)): \
2591 dma_transfer_loop_region(ext, vram, src_op, dest_op, \
2592 transfer_size, wb); \
2594 case (DMA_REGION_BIOS | (DMA_REGION_PALETTE_RAM << 4)): \
2595 dma_transfer_loop_region(bios, palette_ram, src_op, dest_op, \
2596 transfer_size, wb); \
2598 case (DMA_REGION_IWRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2599 dma_transfer_loop_region(iwram, palette_ram, src_op, dest_op, \
2600 transfer_size, wb); \
2602 case (DMA_REGION_EWRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2603 dma_transfer_loop_region(ewram, palette_ram, src_op, dest_op, \
2604 transfer_size, wb); \
2606 case (DMA_REGION_VRAM | (DMA_REGION_PALETTE_RAM << 4)): \
2607 dma_transfer_loop_region(vram, palette_ram, src_op, dest_op, \
2608 transfer_size, wb); \
2610 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_PALETTE_RAM << 4)): \
2611 dma_transfer_loop_region(palette_ram, palette_ram, src_op, dest_op, \
2612 transfer_size, wb); \
2614 case (DMA_REGION_OAM_RAM | (DMA_REGION_PALETTE_RAM << 4)): \
2615 dma_transfer_loop_region(oam_ram, palette_ram, src_op, dest_op, \
2616 transfer_size, wb); \
2618 case (DMA_REGION_IO | (DMA_REGION_PALETTE_RAM << 4)): \
2619 dma_transfer_loop_region(io, palette_ram, src_op, dest_op, \
2620 transfer_size, wb); \
2622 case (DMA_REGION_GAMEPAK | (DMA_REGION_PALETTE_RAM << 4)): \
2623 dma_transfer_loop_region(gamepak, palette_ram, src_op, dest_op, \
2624 transfer_size, wb); \
2626 case (DMA_REGION_EXT | (DMA_REGION_PALETTE_RAM << 4)): \
2627 dma_transfer_loop_region(ext, palette_ram, src_op, dest_op, \
2628 transfer_size, wb); \
2630 case (DMA_REGION_BIOS | (DMA_REGION_OAM_RAM << 4)): \
2631 dma_transfer_loop_region(bios, oam_ram, src_op, dest_op, \
2632 transfer_size, wb); \
2634 case (DMA_REGION_IWRAM | (DMA_REGION_OAM_RAM << 4)): \
2635 dma_transfer_loop_region(iwram, oam_ram, src_op, dest_op, \
2636 transfer_size, wb); \
2638 case (DMA_REGION_EWRAM | (DMA_REGION_OAM_RAM << 4)): \
2639 dma_transfer_loop_region(ewram, oam_ram, src_op, dest_op, \
2640 transfer_size, wb); \
2642 case (DMA_REGION_VRAM | (DMA_REGION_OAM_RAM << 4)): \
2643 dma_transfer_loop_region(vram, oam_ram, src_op, dest_op, \
2644 transfer_size, wb); \
2646 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_OAM_RAM << 4)): \
2647 dma_transfer_loop_region(palette_ram, oam_ram, src_op, dest_op, \
2648 transfer_size, wb); \
2650 case (DMA_REGION_OAM_RAM | (DMA_REGION_OAM_RAM << 4)): \
2651 dma_transfer_loop_region(oam_ram, oam_ram, src_op, dest_op, \
2652 transfer_size, wb); \
2654 case (DMA_REGION_IO | (DMA_REGION_OAM_RAM << 4)): \
2655 dma_transfer_loop_region(io, oam_ram, src_op, dest_op, \
2656 transfer_size, wb); \
2658 case (DMA_REGION_GAMEPAK | (DMA_REGION_OAM_RAM << 4)): \
2659 dma_transfer_loop_region(gamepak, oam_ram, src_op, dest_op, \
2660 transfer_size, wb); \
2662 case (DMA_REGION_EXT | (DMA_REGION_OAM_RAM << 4)): \
2663 dma_transfer_loop_region(ext, oam_ram, src_op, dest_op, \
2664 transfer_size, wb); \
2666 case (DMA_REGION_BIOS | (DMA_REGION_IO << 4)): \
2667 dma_transfer_loop_region(bios, io, src_op, dest_op, \
2668 transfer_size, wb); \
2670 case (DMA_REGION_IWRAM | (DMA_REGION_IO << 4)): \
2671 dma_transfer_loop_region(iwram, io, src_op, dest_op, \
2672 transfer_size, wb); \
2674 case (DMA_REGION_EWRAM | (DMA_REGION_IO << 4)): \
2675 dma_transfer_loop_region(ewram, io, src_op, dest_op, \
2676 transfer_size, wb); \
2678 case (DMA_REGION_VRAM | (DMA_REGION_IO << 4)): \
2679 dma_transfer_loop_region(vram, io, src_op, dest_op, \
2680 transfer_size, wb); \
2682 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IO << 4)): \
2683 dma_transfer_loop_region(palette_ram, io, src_op, dest_op, \
2684 transfer_size, wb); \
2686 case (DMA_REGION_OAM_RAM | (DMA_REGION_IO << 4)): \
2687 dma_transfer_loop_region(oam_ram, io, src_op, dest_op, \
2688 transfer_size, wb); \
2690 case (DMA_REGION_IO | (DMA_REGION_IO << 4)): \
2691 dma_transfer_loop_region(io, io, src_op, dest_op, \
2692 transfer_size, wb); \
2694 case (DMA_REGION_GAMEPAK | (DMA_REGION_IO << 4)): \
2695 dma_transfer_loop_region(gamepak, io, src_op, dest_op, \
2696 transfer_size, wb); \
2698 case (DMA_REGION_EXT | (DMA_REGION_IO << 4)): \
2699 dma_transfer_loop_region(ext, io, src_op, dest_op, \
2700 transfer_size, wb); \
2702 case (DMA_REGION_BIOS | (DMA_REGION_EXT << 4)): \
2703 dma_transfer_loop_region(bios, ext, src_op, dest_op, \
2704 transfer_size, wb); \
2706 case (DMA_REGION_IWRAM | (DMA_REGION_EXT << 4)): \
2707 dma_transfer_loop_region(iwram, ext, src_op, dest_op, \
2708 transfer_size, wb); \
2710 case (DMA_REGION_EWRAM | (DMA_REGION_EXT << 4)): \
2711 dma_transfer_loop_region(ewram, ext, src_op, dest_op, \
2712 transfer_size, wb); \
2714 case (DMA_REGION_VRAM | (DMA_REGION_EXT << 4)): \
2715 dma_transfer_loop_region(vram, ext, src_op, dest_op, \
2716 transfer_size, wb); \
2718 case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EXT << 4)): \
2719 dma_transfer_loop_region(palette_ram, ext, src_op, dest_op, \
2720 transfer_size, wb); \
2722 case (DMA_REGION_OAM_RAM | (DMA_REGION_EXT << 4)): \
2723 dma_transfer_loop_region(oam_ram, ext, src_op, dest_op, \
2724 transfer_size, wb); \
2726 case (DMA_REGION_IO | (DMA_REGION_EXT << 4)): \
2727 dma_transfer_loop_region(io, ext, src_op, dest_op, \
2728 transfer_size, wb); \
2730 case (DMA_REGION_GAMEPAK | (DMA_REGION_EXT << 4)): \
2731 dma_transfer_loop_region(gamepak, ext, src_op, dest_op, \
2732 transfer_size, wb); \
2734 case (DMA_REGION_EXT | (DMA_REGION_EXT << 3)): \
2735 dma_transfer_loop_region(ext, ext, src_op, dest_op, \
2736 transfer_size, wb); \
2741 #define dma_transfer_expand(transfer_size) \
2742 switch((dma->dest_direction << 2) | dma->source_direction) \
2745 dma_transfer_loop(inc, inc, transfer_size, writeback); \
2748 dma_transfer_loop(dec, inc, transfer_size, writeback); \
2751 dma_transfer_loop(fix, inc, transfer_size, writeback); \
2757 dma_transfer_loop(inc, dec, transfer_size, writeback); \
2760 dma_transfer_loop(dec, dec, transfer_size, writeback); \
2763 dma_transfer_loop(fix, dec, transfer_size, writeback); \
2769 dma_transfer_loop(inc, fix, transfer_size, writeback); \
2772 dma_transfer_loop(dec, fix, transfer_size, writeback); \
2775 dma_transfer_loop(fix, fix, transfer_size, writeback); \
2781 dma_transfer_loop(inc, inc, transfer_size, reload); \
2784 dma_transfer_loop(dec, inc, transfer_size, reload); \
2787 dma_transfer_loop(fix, inc, transfer_size, reload); \
2793 cpu_alert_type dma_transfer(dma_transfer_type *dma)
2796 u32 length = dma->length;
2798 u32 src_ptr = dma->source_address;
2799 u32 dest_ptr = dma->dest_address;
2800 cpu_alert_type return_value = CPU_ALERT_NONE;
2802 // Technically this should be done for source and destination, but
2803 // chances are this is only ever used (probably mistakingly!) for dest.
2804 // The only game I know of that requires this is Lucky Luke.
2805 if((dest_ptr >> 24) != ((dest_ptr + length - 1) >> 24))
2807 u32 first_length = ((dest_ptr & 0xFF000000) + 0x1000000) - dest_ptr;
2808 u32 second_length = length - first_length;
2809 dma->length = first_length;
2813 dma->length = length;
2815 length = second_length;
2816 dest_ptr += first_length;
2817 src_ptr += first_length;
2820 if(dma->length_type == DMA_16BIT)
2824 cycle_dma16_words += length;
2825 dma_transfer_expand(16);
2831 cycle_dma32_words += length;
2832 dma_transfer_expand(32);
2835 if((dma->repeat_type == DMA_NO_REPEAT) ||
2836 (dma->start_type == DMA_START_IMMEDIATELY))
2838 dma->start_type = DMA_INACTIVE;
2839 address16(io_registers, (dma->dma_channel * 12) + 0xBA) &=
2845 raise_interrupt(IRQ_DMA0 << dma->dma_channel);
2846 return_value = CPU_ALERT_IRQ;
2849 return return_value;
2852 // Be sure to do this after loading ROMs.
2854 #define map_region(type, start, end, mirror_blocks, region) \
2855 for(map_offset = (start) / 0x8000; map_offset < \
2856 ((end) / 0x8000); map_offset++) \
2858 memory_map_##type[map_offset] = \
2859 ((u8 *)region) + ((map_offset % mirror_blocks) * 0x8000); \
2862 #define map_null(type, start, end) \
2863 for(map_offset = start / 0x8000; map_offset < (end / 0x8000); \
2866 memory_map_##type[map_offset] = NULL; \
2869 #define map_ram_region(type, start, end, mirror_blocks, region) \
2870 for(map_offset = (start) / 0x8000; map_offset < \
2871 ((end) / 0x8000); map_offset++) \
2873 memory_map_##type[map_offset] = \
2874 ((u8 *)region) + ((map_offset % mirror_blocks) * 0x10000) + 0x8000; \
2877 #define map_vram(type) \
2878 for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \
2881 memory_map_##type[map_offset] = vram; \
2882 memory_map_##type[map_offset + 1] = vram + 0x8000; \
2883 memory_map_##type[map_offset + 2] = vram + (0x8000 * 2); \
2884 memory_map_##type[map_offset + 3] = vram + (0x8000 * 2); \
2887 #define map_vram_firstpage(type) \
2888 for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \
2891 memory_map_##type[map_offset] = vram; \
2892 memory_map_##type[map_offset + 1] = NULL; \
2893 memory_map_##type[map_offset + 2] = NULL; \
2894 memory_map_##type[map_offset + 3] = NULL; \
2898 // Picks a page to evict
2901 u32 evict_gamepak_page()
2903 // Find the one with the smallest frame timestamp
2906 u32 smallest = gamepak_memory_map[0].page_timestamp;
2909 for(i = 1; i < gamepak_ram_pages; i++)
2911 if(gamepak_memory_map[i].page_timestamp <= smallest)
2913 smallest = gamepak_memory_map[i].page_timestamp;
2918 physical_index = gamepak_memory_map[page_index].physical_index;
2920 memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = NULL;
2921 memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = NULL;
2922 memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = NULL;
2927 u8 *load_gamepak_page(u32 physical_index)
2929 if(physical_index >= (gamepak_size >> 15))
2932 u32 page_index = evict_gamepak_page();
2933 u32 page_offset = page_index * (32 * 1024);
2934 u8 *swap_location = gamepak_rom + page_offset;
2936 gamepak_memory_map[page_index].page_timestamp = page_time;
2937 gamepak_memory_map[page_index].physical_index = physical_index;
2940 file_seek(gamepak_file_large, physical_index * (32 * 1024), SEEK_SET);
2941 file_read(gamepak_file_large, swap_location, (32 * 1024));
2942 memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = swap_location;
2943 memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = swap_location;
2944 memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = swap_location;
2946 // If RTC is active page the RTC register bytes so they can be read
2947 if((rtc_state != RTC_DISABLED) && (physical_index == 0))
2949 memcpy(swap_location + 0xC4, rtc_registers, sizeof(rtc_registers));
2952 return swap_location;
2955 void init_memory_gamepak()
2959 if(gamepak_size > gamepak_ram_buffer_size)
2961 // Large ROMs get special treatment because they
2962 // can't fit into the 16MB ROM buffer.
2964 for(i = 0; i < gamepak_ram_pages; i++)
2966 gamepak_memory_map[i].page_timestamp = 0;
2967 gamepak_memory_map[i].physical_index = 0;
2970 map_null(read, 0x8000000, 0xD000000);
2974 map_region(read, 0x8000000, 0x8000000 + gamepak_size, 1024, gamepak_rom);
2975 map_null(read, 0x8000000 + gamepak_size, 0xA000000);
2976 map_region(read, 0xA000000, 0xA000000 + gamepak_size, 1024, gamepak_rom);
2977 map_null(read, 0xA000000 + gamepak_size, 0xC000000);
2978 map_region(read, 0xC000000, 0xC000000 + gamepak_size, 1024, gamepak_rom);
2979 map_null(read, 0xC000000 + gamepak_size, 0xE000000);
2983 void init_gamepak_buffer()
2985 // Try to initialize 32MB (this is mainly for non-PSP platforms)
2988 gamepak_ram_buffer_size = 32 * 1024 * 1024;
2989 gamepak_rom = malloc(gamepak_ram_buffer_size);
2991 if(gamepak_rom == NULL)
2993 // Try 16MB, for PSP, then lower in 2MB increments
2994 gamepak_ram_buffer_size = 16 * 1024 * 1024;
2995 gamepak_rom = malloc(gamepak_ram_buffer_size);
2997 while(gamepak_rom == NULL)
2999 gamepak_ram_buffer_size -= (2 * 1024 * 1024);
3000 gamepak_rom = malloc(gamepak_ram_buffer_size);
3004 // Here's assuming we'll have enough memory left over for this,
3005 // and that the above succeeded (if not we're in trouble all around)
3006 gamepak_ram_pages = gamepak_ram_buffer_size / (32 * 1024);
3007 gamepak_memory_map = malloc(sizeof(gamepak_swap_entry_type) *
3015 memory_regions[0x00] = (u8 *)bios_rom;
3016 memory_regions[0x01] = (u8 *)bios_rom;
3017 memory_regions[0x02] = (u8 *)ewram;
3018 memory_regions[0x03] = (u8 *)iwram + 0x8000;
3019 memory_regions[0x04] = (u8 *)io_registers;
3020 memory_regions[0x05] = (u8 *)palette_ram;
3021 memory_regions[0x06] = (u8 *)vram;
3022 memory_regions[0x07] = (u8 *)oam_ram;
3023 memory_regions[0x08] = (u8 *)gamepak_rom;
3024 memory_regions[0x09] = (u8 *)(gamepak_rom + 0xFFFFFF);
3025 memory_regions[0x0A] = (u8 *)gamepak_rom;
3026 memory_regions[0x0B] = (u8 *)(gamepak_rom + 0xFFFFFF);
3027 memory_regions[0x0C] = (u8 *)gamepak_rom;
3028 memory_regions[0x0D] = (u8 *)(gamepak_rom + 0xFFFFFF);
3029 memory_regions[0x0E] = (u8 *)gamepak_backup;
3031 memory_limits[0x00] = 0x3FFF;
3032 memory_limits[0x01] = 0x3FFF;
3033 memory_limits[0x02] = 0x3FFFF;
3034 memory_limits[0x03] = 0x7FFF;
3035 memory_limits[0x04] = 0x7FFF;
3036 memory_limits[0x05] = 0x3FF;
3037 memory_limits[0x06] = 0x17FFF;
3038 memory_limits[0x07] = 0x3FF;
3039 memory_limits[0x08] = 0x1FFFFFF;
3040 memory_limits[0x09] = 0x1FFFFFF;
3041 memory_limits[0x0A] = 0x1FFFFFF;
3042 memory_limits[0x0B] = 0x1FFFFFF;
3043 memory_limits[0x0C] = 0x1FFFFFF;
3044 memory_limits[0x0D] = 0x1FFFFFF;
3045 memory_limits[0x0E] = 0xFFFF;
3047 // Fill memory map regions, areas marked as NULL must be checked directly
3048 map_region(read, 0x0000000, 0x1000000, 1, bios_rom);
3049 map_null(read, 0x1000000, 0x2000000);
3050 map_ram_region(read, 0x2000000, 0x3000000, 8, ewram);
3051 map_ram_region(read, 0x3000000, 0x4000000, 1, iwram);
3052 map_region(read, 0x4000000, 0x5000000, 1, io_registers);
3053 map_null(read, 0x5000000, 0x6000000);
3054 map_null(read, 0x6000000, 0x7000000);
3056 map_null(read, 0x7000000, 0x8000000);
3057 init_memory_gamepak();
3058 map_null(read, 0xE000000, 0x10000000);
3060 // Fill memory map regions, areas marked as NULL must be checked directly
3061 map_null(write, 0x0000000, 0x2000000);
3062 map_ram_region(write, 0x2000000, 0x3000000, 8, ewram);
3063 map_ram_region(write, 0x3000000, 0x4000000, 1, iwram);
3064 map_null(write, 0x4000000, 0x5000000);
3065 map_null(write, 0x5000000, 0x6000000);
3067 // The problem here is that the current method of handling self-modifying code
3068 // requires writeable memory to be proceeded by 32KB SMC data areas or be
3069 // indirectly writeable. It's possible to get around this if you turn off the SMC
3070 // check altogether, but this will make a good number of ROMs crash (perhaps most
3071 // of the ones that actually need it? This has yet to be determined).
3073 // This is because VRAM cannot be efficiently made incontiguous, and still allow
3074 // the renderer to work as efficiently. It would, at the very least, require a
3075 // lot of hacking of the renderer which I'm not prepared to do.
3077 // However, it IS possible to directly map the first page no matter what because
3078 // there's 32kb of blank stuff sitting beneath it.
3085 map_null(write, 0x6000000, 0x7000000);
3088 map_null(write, 0x7000000, 0x8000000);
3089 map_null(write, 0x8000000, 0xE000000);
3090 map_null(write, 0xE000000, 0x10000000);
3092 memset(io_registers, 0, 0x8000);
3093 memset(oam_ram, 0, 0x400);
3094 memset(palette_ram, 0, 0x400);
3095 memset(iwram, 0, 0x10000);
3096 memset(ewram, 0, 0x80000);
3097 memset(vram, 0, 0x18000);
3099 io_registers[REG_DISPCNT] = 0x80;
3100 io_registers[REG_P1] = 0x3FF;
3101 io_registers[REG_BG2PA] = 0x100;
3102 io_registers[REG_BG2PD] = 0x100;
3103 io_registers[REG_BG3PA] = 0x100;
3104 io_registers[REG_BG3PD] = 0x100;
3105 io_registers[REG_RCNT] = 0x8000;
3107 backup_type = BACKUP_NONE;
3109 sram_size = SRAM_SIZE_32KB;
3110 flash_size = FLASH_SIZE_64KB;
3112 flash_bank_ptr = gamepak_backup;
3113 flash_command_position = 0;
3114 eeprom_size = EEPROM_512_BYTE;
3115 eeprom_mode = EEPROM_BASE_MODE;
3119 flash_mode = FLASH_BASE_MODE;
3121 rtc_state = RTC_DISABLED;
3122 memset(rtc_registers, 0, sizeof(rtc_registers));
3123 bios_read_protect = 0xe129f000;
3126 void bios_region_read_allow()
3128 memory_map_read[0] = bios_rom;
3131 void bios_region_read_protect()
3133 memory_map_read[0] = NULL;
3137 #define savestate_block(type) \
3138 cpu_##type##_savestate(savestate_file); \
3139 input_##type##_savestate(savestate_file); \
3140 main_##type##_savestate(savestate_file); \
3141 memory_##type##_savestate(savestate_file); \
3142 sound_##type##_savestate(savestate_file); \
3143 video_##type##_savestate(savestate_file) \
3145 void load_state(char *savestate_filename)
3147 file_open(savestate_file, savestate_filename, read);
3148 if(file_check_valid(savestate_file))
3150 char current_gamepak_filename[512];
3154 file_seek(savestate_file, (240 * 160 * 2) + sizeof(time_t), SEEK_SET);
3156 strcpy(current_gamepak_filename, gamepak_filename);
3158 savestate_block(read);
3160 file_close(savestate_file);
3162 flush_translation_cache_ram();
3163 flush_translation_cache_rom();
3164 flush_translation_cache_bios();
3167 gbc_sound_update = 1;
3168 if(strcmp(current_gamepak_filename, gamepak_filename))
3170 u32 dot_position = strcspn(current_gamepak_filename, ".");
3172 // We'll let it slide if the filenames of the savestate and
3173 // the gamepak are similar enough.
3174 strcpy(gamepak_filename, current_gamepak_filename);
3175 if(strncmp(savestate_filename, current_gamepak_filename, dot_position))
3177 if(load_gamepak(gamepak_filename) != -1)
3180 // Okay, so this takes a while, but for now it works.
3181 load_state(savestate_filename);
3192 for(i = 0; i < 512; i++)
3194 current_color = palette_ram[i];
3195 palette_ram_converted[i] =
3196 convert_palette(current_color);
3199 // Oops, these contain raw pointers
3200 for(i = 0; i < 4; i++)
3202 gbc_sound_channel[i].sample_data = square_pattern_duty[2];
3204 current_debug_state = STEP;
3205 instruction_count = 0;
3207 reg[CHANGED_PC_STATUS] = 1;
3211 u8 savestate_write_buffer[506947];
3214 void save_state(char *savestate_filename, u16 *screen_capture)
3216 write_mem_ptr = savestate_write_buffer;
3217 file_open(savestate_file, savestate_filename, write);
3218 if(file_check_valid(savestate_file))
3220 time_t current_time;
3221 file_write_mem(savestate_file, screen_capture, 240 * 160 * 2);
3223 time(¤t_time);
3224 file_write_mem_variable(savestate_file, current_time);
3226 savestate_block(write_mem);
3227 file_write(savestate_file, savestate_write_buffer,
3228 sizeof(savestate_write_buffer));
3230 file_close(savestate_file);
3235 #define memory_savestate_builder(type) \
3236 void memory_##type##_savestate(file_tag_type savestate_file) \
3240 file_##type##_variable(savestate_file, backup_type); \
3241 file_##type##_variable(savestate_file, sram_size); \
3242 file_##type##_variable(savestate_file, flash_mode); \
3243 file_##type##_variable(savestate_file, flash_command_position); \
3244 file_##type##_variable(savestate_file, flash_bank_ptr); \
3245 file_##type##_variable(savestate_file, flash_device_id); \
3246 file_##type##_variable(savestate_file, flash_manufacturer_id); \
3247 file_##type##_variable(savestate_file, flash_size); \
3248 file_##type##_variable(savestate_file, eeprom_size); \
3249 file_##type##_variable(savestate_file, eeprom_mode); \
3250 file_##type##_variable(savestate_file, eeprom_address_length); \
3251 file_##type##_variable(savestate_file, eeprom_address); \
3252 file_##type##_variable(savestate_file, eeprom_counter); \
3253 file_##type##_variable(savestate_file, rtc_state); \
3254 file_##type##_variable(savestate_file, rtc_write_mode); \
3255 file_##type##_array(savestate_file, rtc_registers); \
3256 file_##type##_variable(savestate_file, rtc_command); \
3257 file_##type##_array(savestate_file, rtc_data); \
3258 file_##type##_variable(savestate_file, rtc_status); \
3259 file_##type##_variable(savestate_file, rtc_data_bytes); \
3260 file_##type##_variable(savestate_file, rtc_bit_count); \
3261 file_##type##_array(savestate_file, eeprom_buffer); \
3262 file_##type##_array(savestate_file, gamepak_filename); \
3263 file_##type##_array(savestate_file, dma); \
3265 file_##type(savestate_file, iwram + 0x8000, 0x8000); \
3266 for(i = 0; i < 8; i++) \
3268 file_##type(savestate_file, ewram + (i * 0x10000) + 0x8000, 0x8000); \
3270 file_##type(savestate_file, vram, 0x18000); \
3271 file_##type(savestate_file, oam_ram, 0x400); \
3272 file_##type(savestate_file, palette_ram, 0x400); \
3273 file_##type(savestate_file, io_registers, 0x8000); \
3275 /* This is a hack, for now. */ \
3276 if((flash_bank_ptr < gamepak_backup) || \
3277 (flash_bank_ptr > (gamepak_backup + (1024 * 64)))) \
3279 flash_bank_ptr = gamepak_backup; \
3283 memory_savestate_builder(read);
3284 memory_savestate_builder(write_mem);