1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
73 void set_jump_target(int addr,u_int target)
75 u_char *ptr=(u_char *)addr;
76 u_int *ptr2=(u_int *)ptr;
78 assert((target-(u_int)ptr2-8)<1024);
80 assert((target&3)==0);
81 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
82 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
84 else if(ptr[3]==0x72) {
85 // generated by emit_jno_unlikely
86 if((target-(u_int)ptr2-8)<1024) {
88 assert((target&3)==0);
89 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
91 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
93 assert((target&3)==0);
94 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
96 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
99 assert((ptr[3]&0x0e)==0xa);
100 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
104 // This optionally copies the instruction from the target of the branch into
105 // the space before the branch. Works, but the difference in speed is
106 // usually insignificant.
107 void set_jump_target_fillslot(int addr,u_int target,int copy)
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
111 assert(!copy||ptr2[-1]==0xe28dd000);
114 assert((target-(u_int)ptr2-8)<4096);
115 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
118 assert((ptr[3]&0x0e)==0xa);
119 u_int target_insn=*(u_int *)target;
120 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
123 if((target_insn&0x0c100000)==0x04100000) { // Load
126 if(target_insn&0x08000000) {
130 ptr2[-1]=target_insn;
133 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
138 add_literal(int addr,int val)
140 literals[literalcount][0]=addr;
141 literals[literalcount][1]=val;
145 void *kill_pointer(void *stub)
147 int *ptr=(int *)(stub+4);
148 assert((*ptr&0x0ff00000)==0x05900000);
149 u_int offset=*ptr&0xfff;
150 int **l_ptr=(void *)ptr+offset+8;
152 set_jump_target((int)i_ptr,(int)stub);
156 int get_pointer(void *stub)
158 //printf("get_pointer(%x)\n",(int)stub);
159 int *ptr=(int *)(stub+4);
160 assert((*ptr&0x0ff00000)==0x05900000);
161 u_int offset=*ptr&0xfff;
162 int **l_ptr=(void *)ptr+offset+8;
164 assert((*i_ptr&0x0f000000)==0x0a000000);
165 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
168 // Find the "clean" entry point from a "dirty" entry point
169 // by skipping past the call to verify_code
170 u_int get_clean_addr(int addr)
172 int *ptr=(int *)addr;
178 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
179 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
181 if((*ptr&0xFF000000)==0xea000000) {
182 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
187 int verify_dirty(int addr)
189 u_int *ptr=(u_int *)addr;
191 // get from literal pool
192 assert((*ptr&0xFFF00000)==0xe5900000);
193 u_int offset=*ptr&0xfff;
194 u_int *l_ptr=(void *)ptr+offset+8;
195 u_int source=l_ptr[0];
201 assert((*ptr&0xFFF00000)==0xe3000000);
202 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
203 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
204 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
207 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
208 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
209 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
210 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
211 unsigned int page=source>>12;
212 unsigned int map_value=memory_map[page];
213 if(map_value>=0x80000000) return 0;
214 while(page<((source+len-1)>>12)) {
215 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
217 source = source+(map_value<<2);
219 //printf("verify_dirty: %x %x %x\n",source,copy,len);
220 return !memcmp((void *)source,(void *)copy,len);
223 // This doesn't necessarily find all clean entry points, just
224 // guarantees that it's not dirty
225 int isclean(int addr)
228 int *ptr=((u_int *)addr)+4;
230 int *ptr=((u_int *)addr)+6;
232 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
233 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
234 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
235 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
236 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
240 void get_bounds(int addr,u_int *start,u_int *end)
242 u_int *ptr=(u_int *)addr;
244 // get from literal pool
245 assert((*ptr&0xFFF00000)==0xe5900000);
246 u_int offset=*ptr&0xfff;
247 u_int *l_ptr=(void *)ptr+offset+8;
248 u_int source=l_ptr[0];
249 //u_int copy=l_ptr[1];
254 assert((*ptr&0xFFF00000)==0xe3000000);
255 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
256 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
257 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
260 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
261 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
262 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
263 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
264 if(memory_map[source>>12]>=0x80000000) source = 0;
265 else source = source+(memory_map[source>>12]<<2);
271 /* Register allocation */
273 // Note: registers are allocated clean (unmodified state)
274 // if you intend to modify the register, you must call dirty_reg().
275 void alloc_reg(struct regstat *cur,int i,signed char reg)
278 int preferred_reg = (reg&7);
279 if(reg==CCREG) preferred_reg=HOST_CCREG;
280 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
282 // Don't allocate unused registers
283 if((cur->u>>reg)&1) return;
285 // see if it's already allocated
286 for(hr=0;hr<HOST_REGS;hr++)
288 if(cur->regmap[hr]==reg) return;
291 // Keep the same mapping if the register was already allocated in a loop
292 preferred_reg = loop_reg(i,reg,preferred_reg);
294 // Try to allocate the preferred register
295 if(cur->regmap[preferred_reg]==-1) {
296 cur->regmap[preferred_reg]=reg;
297 cur->dirty&=~(1<<preferred_reg);
298 cur->isconst&=~(1<<preferred_reg);
301 r=cur->regmap[preferred_reg];
302 if(r<64&&((cur->u>>r)&1)) {
303 cur->regmap[preferred_reg]=reg;
304 cur->dirty&=~(1<<preferred_reg);
305 cur->isconst&=~(1<<preferred_reg);
308 if(r>=64&&((cur->uu>>(r&63))&1)) {
309 cur->regmap[preferred_reg]=reg;
310 cur->dirty&=~(1<<preferred_reg);
311 cur->isconst&=~(1<<preferred_reg);
315 // Clear any unneeded registers
316 // We try to keep the mapping consistent, if possible, because it
317 // makes branches easier (especially loops). So we try to allocate
318 // first (see above) before removing old mappings. If this is not
319 // possible then go ahead and clear out the registers that are no
321 for(hr=0;hr<HOST_REGS;hr++)
326 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
330 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
334 // Try to allocate any available register, but prefer
335 // registers that have not been used recently.
337 for(hr=0;hr<HOST_REGS;hr++) {
338 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
339 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
341 cur->dirty&=~(1<<hr);
342 cur->isconst&=~(1<<hr);
348 // Try to allocate any available register
349 for(hr=0;hr<HOST_REGS;hr++) {
350 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
352 cur->dirty&=~(1<<hr);
353 cur->isconst&=~(1<<hr);
358 // Ok, now we have to evict someone
359 // Pick a register we hopefully won't need soon
360 u_char hsn[MAXREG+1];
361 memset(hsn,10,sizeof(hsn));
363 lsn(hsn,i,&preferred_reg);
364 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
365 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
367 // Don't evict the cycle count at entry points, otherwise the entry
368 // stub will have to write it.
369 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
370 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
373 // Alloc preferred register if available
374 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
375 for(hr=0;hr<HOST_REGS;hr++) {
376 // Evict both parts of a 64-bit register
377 if((cur->regmap[hr]&63)==r) {
379 cur->dirty&=~(1<<hr);
380 cur->isconst&=~(1<<hr);
383 cur->regmap[preferred_reg]=reg;
386 for(r=1;r<=MAXREG;r++)
388 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
389 for(hr=0;hr<HOST_REGS;hr++) {
390 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
391 if(cur->regmap[hr]==r+64) {
393 cur->dirty&=~(1<<hr);
394 cur->isconst&=~(1<<hr);
399 for(hr=0;hr<HOST_REGS;hr++) {
400 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
401 if(cur->regmap[hr]==r) {
403 cur->dirty&=~(1<<hr);
404 cur->isconst&=~(1<<hr);
415 for(r=1;r<=MAXREG;r++)
418 for(hr=0;hr<HOST_REGS;hr++) {
419 if(cur->regmap[hr]==r+64) {
421 cur->dirty&=~(1<<hr);
422 cur->isconst&=~(1<<hr);
426 for(hr=0;hr<HOST_REGS;hr++) {
427 if(cur->regmap[hr]==r) {
429 cur->dirty&=~(1<<hr);
430 cur->isconst&=~(1<<hr);
437 printf("This shouldn't happen (alloc_reg)");exit(1);
440 void alloc_reg64(struct regstat *cur,int i,signed char reg)
442 int preferred_reg = 8+(reg&1);
445 // allocate the lower 32 bits
446 alloc_reg(cur,i,reg);
448 // Don't allocate unused registers
449 if((cur->uu>>reg)&1) return;
451 // see if the upper half is already allocated
452 for(hr=0;hr<HOST_REGS;hr++)
454 if(cur->regmap[hr]==reg+64) return;
457 // Keep the same mapping if the register was already allocated in a loop
458 preferred_reg = loop_reg(i,reg,preferred_reg);
460 // Try to allocate the preferred register
461 if(cur->regmap[preferred_reg]==-1) {
462 cur->regmap[preferred_reg]=reg|64;
463 cur->dirty&=~(1<<preferred_reg);
464 cur->isconst&=~(1<<preferred_reg);
467 r=cur->regmap[preferred_reg];
468 if(r<64&&((cur->u>>r)&1)) {
469 cur->regmap[preferred_reg]=reg|64;
470 cur->dirty&=~(1<<preferred_reg);
471 cur->isconst&=~(1<<preferred_reg);
474 if(r>=64&&((cur->uu>>(r&63))&1)) {
475 cur->regmap[preferred_reg]=reg|64;
476 cur->dirty&=~(1<<preferred_reg);
477 cur->isconst&=~(1<<preferred_reg);
481 // Clear any unneeded registers
482 // We try to keep the mapping consistent, if possible, because it
483 // makes branches easier (especially loops). So we try to allocate
484 // first (see above) before removing old mappings. If this is not
485 // possible then go ahead and clear out the registers that are no
487 for(hr=HOST_REGS-1;hr>=0;hr--)
492 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
496 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
500 // Try to allocate any available register, but prefer
501 // registers that have not been used recently.
503 for(hr=0;hr<HOST_REGS;hr++) {
504 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
505 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
506 cur->regmap[hr]=reg|64;
507 cur->dirty&=~(1<<hr);
508 cur->isconst&=~(1<<hr);
514 // Try to allocate any available register
515 for(hr=0;hr<HOST_REGS;hr++) {
516 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
517 cur->regmap[hr]=reg|64;
518 cur->dirty&=~(1<<hr);
519 cur->isconst&=~(1<<hr);
524 // Ok, now we have to evict someone
525 // Pick a register we hopefully won't need soon
526 u_char hsn[MAXREG+1];
527 memset(hsn,10,sizeof(hsn));
529 lsn(hsn,i,&preferred_reg);
530 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
531 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
533 // Don't evict the cycle count at entry points, otherwise the entry
534 // stub will have to write it.
535 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
536 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
539 // Alloc preferred register if available
540 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
541 for(hr=0;hr<HOST_REGS;hr++) {
542 // Evict both parts of a 64-bit register
543 if((cur->regmap[hr]&63)==r) {
545 cur->dirty&=~(1<<hr);
546 cur->isconst&=~(1<<hr);
549 cur->regmap[preferred_reg]=reg|64;
552 for(r=1;r<=MAXREG;r++)
554 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
555 for(hr=0;hr<HOST_REGS;hr++) {
556 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
557 if(cur->regmap[hr]==r+64) {
558 cur->regmap[hr]=reg|64;
559 cur->dirty&=~(1<<hr);
560 cur->isconst&=~(1<<hr);
565 for(hr=0;hr<HOST_REGS;hr++) {
566 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
567 if(cur->regmap[hr]==r) {
568 cur->regmap[hr]=reg|64;
569 cur->dirty&=~(1<<hr);
570 cur->isconst&=~(1<<hr);
581 for(r=1;r<=MAXREG;r++)
584 for(hr=0;hr<HOST_REGS;hr++) {
585 if(cur->regmap[hr]==r+64) {
586 cur->regmap[hr]=reg|64;
587 cur->dirty&=~(1<<hr);
588 cur->isconst&=~(1<<hr);
592 for(hr=0;hr<HOST_REGS;hr++) {
593 if(cur->regmap[hr]==r) {
594 cur->regmap[hr]=reg|64;
595 cur->dirty&=~(1<<hr);
596 cur->isconst&=~(1<<hr);
603 printf("This shouldn't happen");exit(1);
606 // Allocate a temporary register. This is done without regard to
607 // dirty status or whether the register we request is on the unneeded list
608 // Note: This will only allocate one register, even if called multiple times
609 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
612 int preferred_reg = -1;
614 // see if it's already allocated
615 for(hr=0;hr<HOST_REGS;hr++)
617 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
620 // Try to allocate any available register
621 for(hr=HOST_REGS-1;hr>=0;hr--) {
622 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
624 cur->dirty&=~(1<<hr);
625 cur->isconst&=~(1<<hr);
630 // Find an unneeded register
631 for(hr=HOST_REGS-1;hr>=0;hr--)
637 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
639 cur->dirty&=~(1<<hr);
640 cur->isconst&=~(1<<hr);
647 if((cur->uu>>(r&63))&1) {
648 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
650 cur->dirty&=~(1<<hr);
651 cur->isconst&=~(1<<hr);
659 // Ok, now we have to evict someone
660 // Pick a register we hopefully won't need soon
661 // TODO: we might want to follow unconditional jumps here
662 // TODO: get rid of dupe code and make this into a function
663 u_char hsn[MAXREG+1];
664 memset(hsn,10,sizeof(hsn));
666 lsn(hsn,i,&preferred_reg);
667 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
669 // Don't evict the cycle count at entry points, otherwise the entry
670 // stub will have to write it.
671 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
672 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
675 for(r=1;r<=MAXREG;r++)
677 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
678 for(hr=0;hr<HOST_REGS;hr++) {
679 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
680 if(cur->regmap[hr]==r+64) {
682 cur->dirty&=~(1<<hr);
683 cur->isconst&=~(1<<hr);
688 for(hr=0;hr<HOST_REGS;hr++) {
689 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
690 if(cur->regmap[hr]==r) {
692 cur->dirty&=~(1<<hr);
693 cur->isconst&=~(1<<hr);
704 for(r=1;r<=MAXREG;r++)
707 for(hr=0;hr<HOST_REGS;hr++) {
708 if(cur->regmap[hr]==r+64) {
710 cur->dirty&=~(1<<hr);
711 cur->isconst&=~(1<<hr);
715 for(hr=0;hr<HOST_REGS;hr++) {
716 if(cur->regmap[hr]==r) {
718 cur->dirty&=~(1<<hr);
719 cur->isconst&=~(1<<hr);
726 printf("This shouldn't happen");exit(1);
728 // Allocate a specific ARM register.
729 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
733 // see if it's already allocated (and dealloc it)
734 for(n=0;n<HOST_REGS;n++)
736 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
740 cur->dirty&=~(1<<hr);
741 cur->isconst&=~(1<<hr);
744 // Alloc cycle count into dedicated register
745 alloc_cc(struct regstat *cur,int i)
747 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
755 char regname[16][4] = {
773 void output_byte(u_char byte)
777 void output_modrm(u_char mod,u_char rm,u_char ext)
782 u_char byte=(mod<<6)|(ext<<3)|rm;
785 void output_sib(u_char scale,u_char index,u_char base)
790 u_char byte=(scale<<6)|(index<<3)|base;
793 void output_w32(u_int word)
795 *((u_int *)out)=word;
798 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
803 return((rn<<16)|(rd<<12)|rm);
805 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
810 assert((shift&1)==0);
811 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
813 u_int genimm(u_int imm,u_int *encoded)
815 if(imm==0) {*encoded=0;return 1;}
820 *encoded=((i&30)<<7)|imm;
823 imm=(imm>>2)|(imm<<30);i-=2;
827 void genimm_checked(u_int imm,u_int *encoded)
829 u_int ret=genimm(imm,encoded);
832 u_int genjmp(u_int addr)
834 int offset=addr-(int)out-8;
835 if(offset<-33554432||offset>=33554432) {
837 printf("genjmp: out of range: %08x\n", offset);
842 return ((u_int)offset>>2)&0xffffff;
845 void emit_mov(int rs,int rt)
847 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
848 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
851 void emit_movs(int rs,int rt)
853 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
854 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
857 void emit_add(int rs1,int rs2,int rt)
859 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
860 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
863 void emit_adds(int rs1,int rs2,int rt)
865 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
866 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
869 void emit_adcs(int rs1,int rs2,int rt)
871 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
872 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
875 void emit_sbc(int rs1,int rs2,int rt)
877 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
878 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
881 void emit_sbcs(int rs1,int rs2,int rt)
883 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
884 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
887 void emit_neg(int rs, int rt)
889 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
890 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
893 void emit_negs(int rs, int rt)
895 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
896 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
899 void emit_sub(int rs1,int rs2,int rt)
901 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
902 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
905 void emit_subs(int rs1,int rs2,int rt)
907 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
908 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
911 void emit_zeroreg(int rt)
913 assem_debug("mov %s,#0\n",regname[rt]);
914 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
917 void emit_loadreg(int r, int hr)
921 printf("64bit load in 32bit mode!\n");
928 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
929 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
930 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
931 if(r==CCREG) addr=(int)&cycle_count;
932 if(r==CSREG) addr=(int)&Status;
933 if(r==FSREG) addr=(int)&FCR31;
934 if(r==INVCP) addr=(int)&invc_ptr;
935 u_int offset = addr-(u_int)&dynarec_local;
937 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
938 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
941 void emit_storereg(int r, int hr)
945 printf("64bit store in 32bit mode!\n");
949 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
950 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
951 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
952 if(r==CCREG) addr=(int)&cycle_count;
953 if(r==FSREG) addr=(int)&FCR31;
954 u_int offset = addr-(u_int)&dynarec_local;
956 assem_debug("str %s,fp+%d\n",regname[hr],offset);
957 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
960 void emit_test(int rs, int rt)
962 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
963 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
966 void emit_testimm(int rs,int imm)
969 assem_debug("tst %s,$%d\n",regname[rs],imm);
970 genimm_checked(imm,&armval);
971 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
974 void emit_testeqimm(int rs,int imm)
977 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
978 genimm_checked(imm,&armval);
979 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
982 void emit_not(int rs,int rt)
984 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
985 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
988 void emit_mvnmi(int rs,int rt)
990 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
991 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
994 void emit_and(u_int rs1,u_int rs2,u_int rt)
996 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
997 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1000 void emit_or(u_int rs1,u_int rs2,u_int rt)
1002 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1003 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1005 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1007 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1008 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1011 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1016 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1017 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1020 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1022 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1023 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1026 void emit_loadlp(u_int imm,u_int rt)
1028 add_literal((int)out,imm);
1029 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
1030 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
1032 void emit_movw(u_int imm,u_int rt)
1035 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
1036 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
1038 void emit_movt(u_int imm,u_int rt)
1040 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
1041 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
1043 void emit_movimm(u_int imm,u_int rt)
1046 if(genimm(imm,&armval)) {
1047 assem_debug("mov %s,#%d\n",regname[rt],imm);
1048 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
1049 }else if(genimm(~imm,&armval)) {
1050 assem_debug("mvn %s,#%d\n",regname[rt],imm);
1051 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
1052 }else if(imm<65536) {
1054 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1055 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1056 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1057 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1063 emit_loadlp(imm,rt);
1065 emit_movw(imm&0x0000FFFF,rt);
1066 emit_movt(imm&0xFFFF0000,rt);
1070 void emit_pcreladdr(u_int rt)
1072 assem_debug("add %s,pc,#?\n",regname[rt]);
1073 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1076 void emit_addimm(u_int rs,int imm,u_int rt)
1081 assert(imm>-65536&&imm<65536);
1083 if(genimm(imm,&armval)) {
1084 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1085 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1086 }else if(genimm(-imm,&armval)) {
1087 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1088 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1090 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1091 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1092 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1093 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1095 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1096 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1097 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1098 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1101 else if(rs!=rt) emit_mov(rs,rt);
1104 void emit_addimm_and_set_flags(int imm,int rt)
1106 assert(imm>-65536&&imm<65536);
1108 if(genimm(imm,&armval)) {
1109 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1110 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1111 }else if(genimm(-imm,&armval)) {
1112 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1113 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1115 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1116 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1117 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1118 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1120 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1121 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1122 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1123 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1126 void emit_addimm_no_flags(u_int imm,u_int rt)
1128 emit_addimm(rt,imm,rt);
1131 void emit_addnop(u_int r)
1134 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1135 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1138 void emit_adcimm(u_int rs,int imm,u_int rt)
1141 genimm_checked(imm,&armval);
1142 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1143 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1145 /*void emit_sbcimm(int imm,u_int rt)
1148 genimm_checked(imm,&armval);
1149 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1150 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1152 void emit_sbbimm(int imm,u_int rt)
1154 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1156 if(imm<128&&imm>=-128) {
1158 output_modrm(3,rt,3);
1164 output_modrm(3,rt,3);
1168 void emit_rscimm(int rs,int imm,u_int rt)
1172 genimm_checked(imm,&armval);
1173 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1174 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1177 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1179 // TODO: if(genimm(imm,&armval)) ...
1181 emit_movimm(imm,HOST_TEMPREG);
1182 emit_adds(HOST_TEMPREG,rsl,rtl);
1183 emit_adcimm(rsh,0,rth);
1186 void emit_sbb(int rs1,int rs2)
1188 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1190 output_modrm(3,rs1,rs2);
1193 void emit_andimm(int rs,int imm,int rt)
1196 if(genimm(imm,&armval)) {
1197 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1198 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1199 }else if(genimm(~imm,&armval)) {
1200 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1201 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1202 }else if(imm==65535) {
1204 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1205 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1206 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1207 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1209 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1210 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1213 assert(imm>0&&imm<65535);
1215 assem_debug("mov r14,#%d\n",imm&0xFF00);
1216 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1217 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1218 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1220 emit_movw(imm,HOST_TEMPREG);
1222 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1223 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1227 void emit_orimm(int rs,int imm,int rt)
1230 if(genimm(imm,&armval)) {
1231 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1232 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1234 assert(imm>0&&imm<65536);
1235 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1236 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1237 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1238 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1242 void emit_xorimm(int rs,int imm,int rt)
1245 if(genimm(imm,&armval)) {
1246 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1247 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1249 assert(imm>0&&imm<65536);
1250 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1251 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1252 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1253 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1257 void emit_shlimm(int rs,u_int imm,int rt)
1262 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1263 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1266 void emit_shrimm(int rs,u_int imm,int rt)
1270 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1271 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1274 void emit_sarimm(int rs,u_int imm,int rt)
1278 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1279 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1282 void emit_rorimm(int rs,u_int imm,int rt)
1286 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1287 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1290 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1292 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1296 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1297 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1298 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1299 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1302 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1304 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1308 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1309 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1310 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1311 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1314 void emit_signextend16(int rs,int rt)
1317 emit_shlimm(rs,16,rt);
1318 emit_sarimm(rt,16,rt);
1320 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1321 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1325 void emit_shl(u_int rs,u_int shift,u_int rt)
1331 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1332 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1334 void emit_shr(u_int rs,u_int shift,u_int rt)
1339 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1340 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1342 void emit_sar(u_int rs,u_int shift,u_int rt)
1347 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1348 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1350 void emit_shlcl(int r)
1352 assem_debug("shl %%%s,%%cl\n",regname[r]);
1355 void emit_shrcl(int r)
1357 assem_debug("shr %%%s,%%cl\n",regname[r]);
1360 void emit_sarcl(int r)
1362 assem_debug("sar %%%s,%%cl\n",regname[r]);
1366 void emit_shldcl(int r1,int r2)
1368 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1371 void emit_shrdcl(int r1,int r2)
1373 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1376 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1381 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1382 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1384 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1389 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1390 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1393 void emit_cmpimm(int rs,int imm)
1396 if(genimm(imm,&armval)) {
1397 assem_debug("cmp %s,$%d\n",regname[rs],imm);
1398 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1399 }else if(genimm(-imm,&armval)) {
1400 assem_debug("cmn %s,$%d\n",regname[rs],imm);
1401 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1405 emit_movimm(imm,HOST_TEMPREG);
1407 emit_movw(imm,HOST_TEMPREG);
1409 assem_debug("cmp %s,r14\n",regname[rs]);
1410 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1414 emit_movimm(-imm,HOST_TEMPREG);
1416 emit_movw(-imm,HOST_TEMPREG);
1418 assem_debug("cmn %s,r14\n",regname[rs]);
1419 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1423 void emit_cmovne(u_int *addr,int rt)
1425 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1428 void emit_cmovl(u_int *addr,int rt)
1430 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1433 void emit_cmovs(u_int *addr,int rt)
1435 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1438 void emit_cmovne_imm(int imm,int rt)
1440 assem_debug("movne %s,#%d\n",regname[rt],imm);
1442 genimm_checked(imm,&armval);
1443 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1445 void emit_cmovl_imm(int imm,int rt)
1447 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1449 genimm_checked(imm,&armval);
1450 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1452 void emit_cmovb_imm(int imm,int rt)
1454 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1456 genimm_checked(imm,&armval);
1457 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1459 void emit_cmovs_imm(int imm,int rt)
1461 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1463 genimm_checked(imm,&armval);
1464 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1466 void emit_cmove_reg(int rs,int rt)
1468 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1469 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1471 void emit_cmovne_reg(int rs,int rt)
1473 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1474 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1476 void emit_cmovl_reg(int rs,int rt)
1478 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1479 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1481 void emit_cmovs_reg(int rs,int rt)
1483 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1484 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1487 void emit_slti32(int rs,int imm,int rt)
1489 if(rs!=rt) emit_zeroreg(rt);
1490 emit_cmpimm(rs,imm);
1491 if(rs==rt) emit_movimm(0,rt);
1492 emit_cmovl_imm(1,rt);
1494 void emit_sltiu32(int rs,int imm,int rt)
1496 if(rs!=rt) emit_zeroreg(rt);
1497 emit_cmpimm(rs,imm);
1498 if(rs==rt) emit_movimm(0,rt);
1499 emit_cmovb_imm(1,rt);
1501 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1504 emit_slti32(rsl,imm,rt);
1508 emit_cmovne_imm(0,rt);
1509 emit_cmovs_imm(1,rt);
1513 emit_cmpimm(rsh,-1);
1514 emit_cmovne_imm(0,rt);
1515 emit_cmovl_imm(1,rt);
1518 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1521 emit_sltiu32(rsl,imm,rt);
1525 emit_cmovne_imm(0,rt);
1529 emit_cmpimm(rsh,-1);
1530 emit_cmovne_imm(1,rt);
1534 void emit_cmp(int rs,int rt)
1536 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1537 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1539 void emit_set_gz32(int rs, int rt)
1541 //assem_debug("set_gz32\n");
1544 emit_cmovl_imm(0,rt);
1546 void emit_set_nz32(int rs, int rt)
1548 //assem_debug("set_nz32\n");
1549 if(rs!=rt) emit_movs(rs,rt);
1550 else emit_test(rs,rs);
1551 emit_cmovne_imm(1,rt);
1553 void emit_set_gz64_32(int rsh, int rsl, int rt)
1555 //assem_debug("set_gz64\n");
1556 emit_set_gz32(rsl,rt);
1558 emit_cmovne_imm(1,rt);
1559 emit_cmovs_imm(0,rt);
1561 void emit_set_nz64_32(int rsh, int rsl, int rt)
1563 //assem_debug("set_nz64\n");
1564 emit_or_and_set_flags(rsh,rsl,rt);
1565 emit_cmovne_imm(1,rt);
1567 void emit_set_if_less32(int rs1, int rs2, int rt)
1569 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1570 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1572 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1573 emit_cmovl_imm(1,rt);
1575 void emit_set_if_carry32(int rs1, int rs2, int rt)
1577 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1578 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1580 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1581 emit_cmovb_imm(1,rt);
1583 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1585 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1590 emit_sbcs(u1,u2,HOST_TEMPREG);
1591 emit_cmovl_imm(1,rt);
1593 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1595 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1600 emit_sbcs(u1,u2,HOST_TEMPREG);
1601 emit_cmovb_imm(1,rt);
1604 void emit_call(int a)
1606 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1607 u_int offset=genjmp(a);
1608 output_w32(0xeb000000|offset);
1610 void emit_jmp(int a)
1612 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1613 u_int offset=genjmp(a);
1614 output_w32(0xea000000|offset);
1616 void emit_jne(int a)
1618 assem_debug("bne %x\n",a);
1619 u_int offset=genjmp(a);
1620 output_w32(0x1a000000|offset);
1622 void emit_jeq(int a)
1624 assem_debug("beq %x\n",a);
1625 u_int offset=genjmp(a);
1626 output_w32(0x0a000000|offset);
1630 assem_debug("bmi %x\n",a);
1631 u_int offset=genjmp(a);
1632 output_w32(0x4a000000|offset);
1634 void emit_jns(int a)
1636 assem_debug("bpl %x\n",a);
1637 u_int offset=genjmp(a);
1638 output_w32(0x5a000000|offset);
1642 assem_debug("blt %x\n",a);
1643 u_int offset=genjmp(a);
1644 output_w32(0xba000000|offset);
1646 void emit_jge(int a)
1648 assem_debug("bge %x\n",a);
1649 u_int offset=genjmp(a);
1650 output_w32(0xaa000000|offset);
1652 void emit_jno(int a)
1654 assem_debug("bvc %x\n",a);
1655 u_int offset=genjmp(a);
1656 output_w32(0x7a000000|offset);
1660 assem_debug("bcs %x\n",a);
1661 u_int offset=genjmp(a);
1662 output_w32(0x2a000000|offset);
1664 void emit_jcc(int a)
1666 assem_debug("bcc %x\n",a);
1667 u_int offset=genjmp(a);
1668 output_w32(0x3a000000|offset);
1671 void emit_pushimm(int imm)
1673 assem_debug("push $%x\n",imm);
1678 assem_debug("pusha\n");
1683 assem_debug("popa\n");
1686 void emit_pushreg(u_int r)
1688 assem_debug("push %%%s\n",regname[r]);
1691 void emit_popreg(u_int r)
1693 assem_debug("pop %%%s\n",regname[r]);
1696 void emit_callreg(u_int r)
1698 assem_debug("call *%%%s\n",regname[r]);
1701 void emit_jmpreg(u_int r)
1703 assem_debug("mov pc,%s\n",regname[r]);
1704 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1707 void emit_readword_indexed(int offset, int rs, int rt)
1709 assert(offset>-4096&&offset<4096);
1710 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1712 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1714 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1717 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1719 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1720 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1722 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1724 if(map<0) emit_readword_indexed(addr, rs, rt);
1727 emit_readword_dualindexedx4(rs, map, rt);
1730 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1733 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1734 emit_readword_indexed(addr+4, rs, rl);
1737 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1738 emit_addimm(map,1,map);
1739 emit_readword_indexed_tlb(addr, rs, map, rl);
1742 void emit_movsbl_indexed(int offset, int rs, int rt)
1744 assert(offset>-256&&offset<256);
1745 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1747 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1749 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1752 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1754 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1757 emit_shlimm(map,2,map);
1758 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1759 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1761 assert(addr>-256&&addr<256);
1762 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1763 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1764 emit_movsbl_indexed(addr, rt, rt);
1768 void emit_movswl_indexed(int offset, int rs, int rt)
1770 assert(offset>-256&&offset<256);
1771 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1773 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1775 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1778 void emit_movzbl_indexed(int offset, int rs, int rt)
1780 assert(offset>-4096&&offset<4096);
1781 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1783 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1785 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1788 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1790 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1791 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1793 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1795 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1798 emit_movzbl_dualindexedx4(rs, map, rt);
1800 emit_addimm(rs,addr,rt);
1801 emit_movzbl_dualindexedx4(rt, map, rt);
1805 void emit_movzwl_indexed(int offset, int rs, int rt)
1807 assert(offset>-256&&offset<256);
1808 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1810 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1812 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1815 void emit_readword(int addr, int rt)
1817 u_int offset = addr-(u_int)&dynarec_local;
1818 assert(offset<4096);
1819 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1820 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1822 void emit_movsbl(int addr, int rt)
1824 u_int offset = addr-(u_int)&dynarec_local;
1826 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1827 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1829 void emit_movswl(int addr, int rt)
1831 u_int offset = addr-(u_int)&dynarec_local;
1833 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1834 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1836 void emit_movzbl(int addr, int rt)
1838 u_int offset = addr-(u_int)&dynarec_local;
1839 assert(offset<4096);
1840 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1841 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1843 void emit_movzwl(int addr, int rt)
1845 u_int offset = addr-(u_int)&dynarec_local;
1847 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1848 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1850 void emit_movzwl_reg(int rs, int rt)
1852 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1856 void emit_xchg(int rs, int rt)
1858 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1861 void emit_writeword_indexed(int rt, int offset, int rs)
1863 assert(offset>-4096&&offset<4096);
1864 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1866 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1868 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1871 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1873 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1874 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1876 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1878 if(map<0) emit_writeword_indexed(rt, addr, rs);
1881 emit_writeword_dualindexedx4(rt, rs, map);
1884 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1887 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1888 emit_writeword_indexed(rl, addr+4, rs);
1891 if(temp!=rs) emit_addimm(map,1,temp);
1892 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1893 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1895 emit_addimm(rs,4,rs);
1896 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1900 void emit_writehword_indexed(int rt, int offset, int rs)
1902 assert(offset>-256&&offset<256);
1903 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1905 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1907 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1910 void emit_writebyte_indexed(int rt, int offset, int rs)
1912 assert(offset>-4096&&offset<4096);
1913 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1915 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1917 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1920 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1922 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1923 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1925 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1927 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1930 emit_writebyte_dualindexedx4(rt, rs, map);
1932 emit_addimm(rs,addr,temp);
1933 emit_writebyte_dualindexedx4(rt, temp, map);
1937 void emit_writeword(int rt, int addr)
1939 u_int offset = addr-(u_int)&dynarec_local;
1940 assert(offset<4096);
1941 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1942 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
1944 void emit_writehword(int rt, int addr)
1946 u_int offset = addr-(u_int)&dynarec_local;
1948 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
1949 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1951 void emit_writebyte(int rt, int addr)
1953 u_int offset = addr-(u_int)&dynarec_local;
1954 assert(offset<4096);
1955 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
1956 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
1958 void emit_writeword_imm(int imm, int addr)
1960 assem_debug("movl $%x,%x\n",imm,addr);
1963 void emit_writebyte_imm(int imm, int addr)
1965 assem_debug("movb $%x,%x\n",imm,addr);
1969 void emit_mul(int rs)
1971 assem_debug("mul %%%s\n",regname[rs]);
1974 void emit_imul(int rs)
1976 assem_debug("imul %%%s\n",regname[rs]);
1979 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1981 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1986 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1988 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1990 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
1995 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
1998 void emit_div(int rs)
2000 assem_debug("div %%%s\n",regname[rs]);
2003 void emit_idiv(int rs)
2005 assem_debug("idiv %%%s\n",regname[rs]);
2010 assem_debug("cdq\n");
2014 void emit_clz(int rs,int rt)
2016 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2017 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2020 void emit_subcs(int rs1,int rs2,int rt)
2022 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2023 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2026 void emit_shrcc_imm(int rs,u_int imm,int rt)
2030 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2031 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2034 void emit_negmi(int rs, int rt)
2036 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2037 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2040 void emit_negsmi(int rs, int rt)
2042 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2043 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2046 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2048 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2049 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2052 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2054 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2055 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2058 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2060 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2061 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2064 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2066 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2067 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2070 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2072 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2073 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2076 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2078 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2079 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2082 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2084 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2085 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2088 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2090 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2091 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2094 void emit_teq(int rs, int rt)
2096 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2097 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2100 void emit_rsbimm(int rs, int imm, int rt)
2103 genimm_checked(imm,&armval);
2104 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2105 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2108 // Load 2 immediates optimizing for small code size
2109 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2111 emit_movimm(imm1,rt1);
2113 if(genimm(imm2-imm1,&armval)) {
2114 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2115 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2116 }else if(genimm(imm1-imm2,&armval)) {
2117 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2118 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2120 else emit_movimm(imm2,rt2);
2123 // Conditionally select one of two immediates, optimizing for small code size
2124 // This will only be called if HAVE_CMOV_IMM is defined
2125 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2128 if(genimm(imm2-imm1,&armval)) {
2129 emit_movimm(imm1,rt);
2130 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2131 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2132 }else if(genimm(imm1-imm2,&armval)) {
2133 emit_movimm(imm1,rt);
2134 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2135 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2139 emit_movimm(imm1,rt);
2140 add_literal((int)out,imm2);
2141 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2142 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2144 emit_movw(imm1&0x0000FFFF,rt);
2145 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2146 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2147 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2149 emit_movt(imm1&0xFFFF0000,rt);
2150 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2151 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2152 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2158 // special case for checking invalid_code
2159 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2164 // special case for checking invalid_code
2165 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2167 assert(imm<128&&imm>=0);
2169 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2170 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2171 emit_cmpimm(HOST_TEMPREG,imm);
2174 // special case for tlb mapping
2175 void emit_addsr12(int rs1,int rs2,int rt)
2177 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2178 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2181 // Used to preload hash table entries
2182 void emit_prefetch(void *addr)
2184 assem_debug("prefetch %x\n",(int)addr);
2187 output_modrm(0,5,1);
2188 output_w32((int)addr);
2190 void emit_prefetchreg(int r)
2192 assem_debug("pld %s\n",regname[r]);
2193 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2196 // Special case for mini_ht
2197 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2199 assert(offset<4096);
2200 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2201 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2204 void emit_flds(int r,int sr)
2206 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2207 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2210 void emit_vldr(int r,int vr)
2212 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2213 output_w32(0xed900b00|(vr<<12)|(r<<16));
2216 void emit_fsts(int sr,int r)
2218 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2219 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2222 void emit_vstr(int vr,int r)
2224 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2225 output_w32(0xed800b00|(vr<<12)|(r<<16));
2228 void emit_ftosizs(int s,int d)
2230 assem_debug("ftosizs s%d,s%d\n",d,s);
2231 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2234 void emit_ftosizd(int s,int d)
2236 assem_debug("ftosizd s%d,d%d\n",d,s);
2237 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2240 void emit_fsitos(int s,int d)
2242 assem_debug("fsitos s%d,s%d\n",d,s);
2243 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2246 void emit_fsitod(int s,int d)
2248 assem_debug("fsitod d%d,s%d\n",d,s);
2249 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2252 void emit_fcvtds(int s,int d)
2254 assem_debug("fcvtds d%d,s%d\n",d,s);
2255 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2258 void emit_fcvtsd(int s,int d)
2260 assem_debug("fcvtsd s%d,d%d\n",d,s);
2261 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2264 void emit_fsqrts(int s,int d)
2266 assem_debug("fsqrts d%d,s%d\n",d,s);
2267 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2270 void emit_fsqrtd(int s,int d)
2272 assem_debug("fsqrtd s%d,d%d\n",d,s);
2273 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2276 void emit_fabss(int s,int d)
2278 assem_debug("fabss d%d,s%d\n",d,s);
2279 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2282 void emit_fabsd(int s,int d)
2284 assem_debug("fabsd s%d,d%d\n",d,s);
2285 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2288 void emit_fnegs(int s,int d)
2290 assem_debug("fnegs d%d,s%d\n",d,s);
2291 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2294 void emit_fnegd(int s,int d)
2296 assem_debug("fnegd s%d,d%d\n",d,s);
2297 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2300 void emit_fadds(int s1,int s2,int d)
2302 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2303 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2306 void emit_faddd(int s1,int s2,int d)
2308 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2309 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2312 void emit_fsubs(int s1,int s2,int d)
2314 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2315 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2318 void emit_fsubd(int s1,int s2,int d)
2320 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2321 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2324 void emit_fmuls(int s1,int s2,int d)
2326 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2327 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2330 void emit_fmuld(int s1,int s2,int d)
2332 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2333 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2336 void emit_fdivs(int s1,int s2,int d)
2338 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2339 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2342 void emit_fdivd(int s1,int s2,int d)
2344 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2345 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2348 void emit_fcmps(int x,int y)
2350 assem_debug("fcmps s14, s15\n");
2351 output_w32(0xeeb47a67);
2354 void emit_fcmpd(int x,int y)
2356 assem_debug("fcmpd d6, d7\n");
2357 output_w32(0xeeb46b47);
2362 assem_debug("fmstat\n");
2363 output_w32(0xeef1fa10);
2366 void emit_bicne_imm(int rs,int imm,int rt)
2369 genimm_checked(imm,&armval);
2370 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2371 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2374 void emit_biccs_imm(int rs,int imm,int rt)
2377 genimm_checked(imm,&armval);
2378 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2379 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2382 void emit_bicvc_imm(int rs,int imm,int rt)
2385 genimm_checked(imm,&armval);
2386 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2387 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2390 void emit_bichi_imm(int rs,int imm,int rt)
2393 genimm_checked(imm,&armval);
2394 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2395 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2398 void emit_orrvs_imm(int rs,int imm,int rt)
2401 genimm_checked(imm,&armval);
2402 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2403 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2406 void emit_orrne_imm(int rs,int imm,int rt)
2409 genimm_checked(imm,&armval);
2410 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2411 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2414 void emit_andne_imm(int rs,int imm,int rt)
2417 genimm_checked(imm,&armval);
2418 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2419 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2422 void emit_jno_unlikely(int a)
2425 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2426 output_w32(0x72800000|rd_rn_rm(15,15,0));
2429 // Save registers before function call
2430 void save_regs(u_int reglist)
2432 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2433 if(!reglist) return;
2434 assem_debug("stmia fp,{");
2435 if(reglist&1) assem_debug("r0, ");
2436 if(reglist&2) assem_debug("r1, ");
2437 if(reglist&4) assem_debug("r2, ");
2438 if(reglist&8) assem_debug("r3, ");
2439 if(reglist&0x1000) assem_debug("r12");
2441 output_w32(0xe88b0000|reglist);
2443 // Restore registers after function call
2444 void restore_regs(u_int reglist)
2446 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2447 if(!reglist) return;
2448 assem_debug("ldmia fp,{");
2449 if(reglist&1) assem_debug("r0, ");
2450 if(reglist&2) assem_debug("r1, ");
2451 if(reglist&4) assem_debug("r2, ");
2452 if(reglist&8) assem_debug("r3, ");
2453 if(reglist&0x1000) assem_debug("r12");
2455 output_w32(0xe89b0000|reglist);
2458 // Write back consts using r14 so we don't disturb the other registers
2459 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2462 for(hr=0;hr<HOST_REGS;hr++) {
2463 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2464 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2465 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2466 int value=constmap[i][hr];
2468 emit_zeroreg(HOST_TEMPREG);
2471 emit_movimm(value,HOST_TEMPREG);
2473 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2475 if((i_is32>>i_regmap[hr])&1) {
2476 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2477 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2486 /* Stubs/epilogue */
2488 void literal_pool(int n)
2490 if(!literalcount) return;
2492 if((int)out-literals[0][0]<4096-n) return;
2496 for(i=0;i<literalcount;i++)
2498 ptr=(u_int *)literals[i][0];
2499 u_int offset=(u_int)out-(u_int)ptr-8;
2500 assert(offset<4096);
2501 assert(!(offset&3));
2503 output_w32(literals[i][1]);
2508 void literal_pool_jumpover(int n)
2510 if(!literalcount) return;
2512 if((int)out-literals[0][0]<4096-n) return;
2517 set_jump_target(jaddr,(int)out);
2520 emit_extjump2(int addr, int target, int linker)
2522 u_char *ptr=(u_char *)addr;
2523 assert((ptr[3]&0x0e)==0xa);
2524 emit_loadlp(target,0);
2525 emit_loadlp(addr,1);
2526 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2527 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2529 #ifdef DEBUG_CYCLE_COUNT
2530 emit_readword((int)&last_count,ECX);
2531 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2532 emit_readword((int)&next_interupt,ECX);
2533 emit_writeword(HOST_CCREG,(int)&Count);
2534 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2535 emit_writeword(ECX,(int)&last_count);
2541 emit_extjump(int addr, int target)
2543 emit_extjump2(addr, target, (int)dyna_linker);
2545 emit_extjump_ds(int addr, int target)
2547 emit_extjump2(addr, target, (int)dyna_linker_ds);
2552 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2554 set_jump_target(stubs[n][1],(int)out);
2555 int type=stubs[n][0];
2558 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2559 u_int reglist=stubs[n][7];
2560 signed char *i_regmap=i_regs->regmap;
2561 int addr=get_reg(i_regmap,AGEN1+(i&1));
2564 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2565 rth=get_reg(i_regmap,FTEMP|64);
2566 rt=get_reg(i_regmap,FTEMP);
2568 rth=get_reg(i_regmap,rt1[i]|64);
2569 rt=get_reg(i_regmap,rt1[i]);
2574 // assume dummy read, no alloced reg
2575 addr=get_reg(i_regmap,-1);
2578 if(type==LOADB_STUB||type==LOADBU_STUB)
2579 ftable=(int)readmemb;
2580 if(type==LOADH_STUB||type==LOADHU_STUB)
2581 ftable=(int)readmemh;
2582 if(type==LOADW_STUB)
2583 ftable=(int)readmem;
2585 if(type==LOADD_STUB)
2586 ftable=(int)readmemd;
2589 emit_writeword(rs,(int)&address);
2592 ds=i_regs!=®s[i];
2593 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2594 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2595 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2596 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2597 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2598 emit_shrimm(rs,16,1);
2599 int cc=get_reg(i_regmap,CCREG);
2601 emit_loadreg(CCREG,2);
2603 emit_movimm(ftable,0);
2604 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2605 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2606 //emit_readword((int)&last_count,temp);
2607 //emit_add(cc,temp,cc);
2608 //emit_writeword(cc,(int)&Count);
2610 emit_call((int)&indirect_jump_indexed);
2612 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2613 // We really shouldn't need to update the count here,
2614 // but not doing so causes random crashes...
2615 emit_readword((int)&Count,HOST_TEMPREG);
2616 emit_readword((int)&next_interupt,2);
2617 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2618 emit_writeword(2,(int)&last_count);
2619 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2621 emit_storereg(CCREG,HOST_TEMPREG);
2624 restore_regs(reglist);
2625 //if((cc=get_reg(regmap,CCREG))>=0) {
2626 // emit_loadreg(CCREG,cc);
2628 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2630 if(type==LOADB_STUB)
2631 emit_movsbl((int)&readmem_dword,rt);
2632 if(type==LOADBU_STUB)
2633 emit_movzbl((int)&readmem_dword,rt);
2634 if(type==LOADH_STUB)
2635 emit_movswl((int)&readmem_dword,rt);
2636 if(type==LOADHU_STUB)
2637 emit_movzwl((int)&readmem_dword,rt);
2638 if(type==LOADW_STUB)
2639 emit_readword((int)&readmem_dword,rt);
2640 if(type==LOADD_STUB) {
2641 emit_readword((int)&readmem_dword,rt);
2642 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2645 emit_jmp(stubs[n][2]); // return address
2648 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2650 int rs=get_reg(regmap,target);
2651 int rth=get_reg(regmap,target|64);
2652 int rt=get_reg(regmap,target);
2656 if(type==LOADB_STUB||type==LOADBU_STUB)
2657 ftable=(int)readmemb;
2658 if(type==LOADH_STUB||type==LOADHU_STUB)
2659 ftable=(int)readmemh;
2660 if(type==LOADW_STUB)
2661 ftable=(int)readmem;
2663 if(type==LOADD_STUB)
2664 ftable=(int)readmemd;
2667 emit_writeword(rs,(int)&address);
2670 //emit_shrimm(rs,16,1);
2671 int cc=get_reg(regmap,CCREG);
2673 emit_loadreg(CCREG,2);
2675 //emit_movimm(ftable,0);
2676 emit_movimm(((u_int *)ftable)[addr>>16],0);
2677 //emit_readword((int)&last_count,12);
2678 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2679 if((signed int)addr>=(signed int)0xC0000000) {
2680 // Pagefault address
2681 int ds=regmap!=regs[i].regmap;
2682 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2685 //emit_writeword(2,(int)&Count);
2686 //emit_call(((u_int *)ftable)[addr>>16]);
2687 emit_call((int)&indirect_jump);
2688 // We really shouldn't need to update the count here,
2689 // but not doing so causes random crashes...
2690 emit_readword((int)&Count,HOST_TEMPREG);
2691 emit_readword((int)&next_interupt,2);
2692 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2693 emit_writeword(2,(int)&last_count);
2694 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2696 emit_storereg(CCREG,HOST_TEMPREG);
2699 restore_regs(reglist);
2700 if(type==LOADB_STUB)
2701 emit_movsbl((int)&readmem_dword,rt);
2702 if(type==LOADBU_STUB)
2703 emit_movzbl((int)&readmem_dword,rt);
2704 if(type==LOADH_STUB)
2705 emit_movswl((int)&readmem_dword,rt);
2706 if(type==LOADHU_STUB)
2707 emit_movzwl((int)&readmem_dword,rt);
2708 if(type==LOADW_STUB)
2709 emit_readword((int)&readmem_dword,rt);
2710 if(type==LOADD_STUB) {
2711 emit_readword((int)&readmem_dword,rt);
2712 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2718 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2720 set_jump_target(stubs[n][1],(int)out);
2721 int type=stubs[n][0];
2724 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2725 u_int reglist=stubs[n][7];
2726 signed char *i_regmap=i_regs->regmap;
2727 int addr=get_reg(i_regmap,AGEN1+(i&1));
2730 if(itype[i]==C1LS||itype[i]==C2LS) {
2731 rth=get_reg(i_regmap,FTEMP|64);
2732 rt=get_reg(i_regmap,r=FTEMP);
2734 rth=get_reg(i_regmap,rs2[i]|64);
2735 rt=get_reg(i_regmap,r=rs2[i]);
2739 if(addr<0) addr=get_reg(i_regmap,-1);
2742 if(type==STOREB_STUB)
2743 ftable=(int)writememb;
2744 if(type==STOREH_STUB)
2745 ftable=(int)writememh;
2746 if(type==STOREW_STUB)
2747 ftable=(int)writemem;
2749 if(type==STORED_STUB)
2750 ftable=(int)writememd;
2753 emit_writeword(rs,(int)&address);
2754 //emit_shrimm(rs,16,rs);
2755 //emit_movmem_indexedx4(ftable,rs,rs);
2756 if(type==STOREB_STUB)
2757 emit_writebyte(rt,(int)&byte);
2758 if(type==STOREH_STUB)
2759 emit_writehword(rt,(int)&hword);
2760 if(type==STOREW_STUB)
2761 emit_writeword(rt,(int)&word);
2762 if(type==STORED_STUB) {
2764 emit_writeword(rt,(int)&dword);
2765 emit_writeword(r?rth:rt,(int)&dword+4);
2767 printf("STORED_STUB\n");
2772 ds=i_regs!=®s[i];
2773 int real_rs=get_reg(i_regmap,rs1[i]);
2774 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2775 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2776 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2777 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2778 emit_shrimm(rs,16,1);
2779 int cc=get_reg(i_regmap,CCREG);
2781 emit_loadreg(CCREG,2);
2783 emit_movimm(ftable,0);
2784 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2785 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2786 //emit_readword((int)&last_count,temp);
2787 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2788 //emit_add(cc,temp,cc);
2789 //emit_writeword(cc,(int)&Count);
2790 emit_call((int)&indirect_jump_indexed);
2792 emit_readword((int)&Count,HOST_TEMPREG);
2793 emit_readword((int)&next_interupt,2);
2794 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2795 emit_writeword(2,(int)&last_count);
2796 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2798 emit_storereg(CCREG,HOST_TEMPREG);
2801 restore_regs(reglist);
2802 //if((cc=get_reg(regmap,CCREG))>=0) {
2803 // emit_loadreg(CCREG,cc);
2805 emit_jmp(stubs[n][2]); // return address
2808 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2810 int rs=get_reg(regmap,-1);
2811 int rth=get_reg(regmap,target|64);
2812 int rt=get_reg(regmap,target);
2816 if(type==STOREB_STUB)
2817 ftable=(int)writememb;
2818 if(type==STOREH_STUB)
2819 ftable=(int)writememh;
2820 if(type==STOREW_STUB)
2821 ftable=(int)writemem;
2823 if(type==STORED_STUB)
2824 ftable=(int)writememd;
2827 emit_writeword(rs,(int)&address);
2828 //emit_shrimm(rs,16,rs);
2829 //emit_movmem_indexedx4(ftable,rs,rs);
2830 if(type==STOREB_STUB)
2831 emit_writebyte(rt,(int)&byte);
2832 if(type==STOREH_STUB)
2833 emit_writehword(rt,(int)&hword);
2834 if(type==STOREW_STUB)
2835 emit_writeword(rt,(int)&word);
2836 if(type==STORED_STUB) {
2838 emit_writeword(rt,(int)&dword);
2839 emit_writeword(target?rth:rt,(int)&dword+4);
2841 printf("STORED_STUB\n");
2846 //emit_shrimm(rs,16,1);
2847 int cc=get_reg(regmap,CCREG);
2849 emit_loadreg(CCREG,2);
2851 //emit_movimm(ftable,0);
2852 emit_movimm(((u_int *)ftable)[addr>>16],0);
2853 //emit_readword((int)&last_count,12);
2854 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2855 if((signed int)addr>=(signed int)0xC0000000) {
2856 // Pagefault address
2857 int ds=regmap!=regs[i].regmap;
2858 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2861 //emit_writeword(2,(int)&Count);
2862 //emit_call(((u_int *)ftable)[addr>>16]);
2863 emit_call((int)&indirect_jump);
2864 emit_readword((int)&Count,HOST_TEMPREG);
2865 emit_readword((int)&next_interupt,2);
2866 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2867 emit_writeword(2,(int)&last_count);
2868 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2870 emit_storereg(CCREG,HOST_TEMPREG);
2873 restore_regs(reglist);
2876 do_unalignedwritestub(int n)
2878 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2880 set_jump_target(stubs[n][1],(int)out);
2883 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2884 int addr=stubs[n][5];
2885 u_int reglist=stubs[n][7];
2886 signed char *i_regmap=i_regs->regmap;
2887 int temp2=get_reg(i_regmap,FTEMP);
2890 rt=get_reg(i_regmap,rs2[i]);
2893 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2895 reglist&=~(1<<temp2);
2897 emit_andimm(addr,0xfffffffc,temp2);
2898 emit_writeword(temp2,(int)&address);
2901 ds=i_regs!=®s[i];
2902 real_rs=get_reg(i_regmap,rs1[i]);
2903 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2904 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2905 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2906 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2907 emit_shrimm(addr,16,1);
2908 int cc=get_reg(i_regmap,CCREG);
2910 emit_loadreg(CCREG,2);
2912 emit_movimm((u_int)readmem,0);
2913 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2914 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd?
2915 emit_call((int)&indirect_jump_indexed);
2916 restore_regs(reglist);
2918 emit_readword((int)&readmem_dword,temp2);
2919 int temp=addr; //hmh
2920 emit_shlimm(addr,3,temp);
2921 emit_andimm(temp,24,temp);
2922 #ifdef BIG_ENDIAN_MIPS
2923 if (opcode[i]==0x2e) // SWR
2925 if (opcode[i]==0x2a) // SWL
2927 emit_xorimm(temp,24,temp);
2928 emit_movimm(-1,HOST_TEMPREG);
2929 if (opcode[i]==0x2a) { // SWL
2930 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2931 emit_orrshr(rt,temp,temp2);
2933 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2934 emit_orrshl(rt,temp,temp2);
2936 emit_readword((int)&address,addr);
2937 emit_writeword(temp2,(int)&word);
2938 //save_regs(reglist); // don't need to, no state changes
2939 emit_shrimm(addr,16,1);
2940 emit_movimm((u_int)writemem,0);
2941 //emit_call((int)&indirect_jump_indexed);
2943 emit_readword_dualindexedx4(0,1,15);
2944 emit_readword((int)&Count,HOST_TEMPREG);
2945 emit_readword((int)&next_interupt,2);
2946 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2947 emit_writeword(2,(int)&last_count);
2948 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2950 emit_storereg(CCREG,HOST_TEMPREG);
2952 restore_regs(reglist);
2953 emit_jmp(stubs[n][2]); // return address
2956 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
2958 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
2964 u_int reglist=stubs[n][3];
2965 set_jump_target(stubs[n][1],(int)out);
2967 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2968 emit_call((int)&invalidate_addr);
2969 restore_regs(reglist);
2970 emit_jmp(stubs[n][2]); // return address
2973 int do_dirty_stub(int i)
2975 assem_debug("do_dirty_stub %x\n",start+i*4);
2976 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
2980 // Careful about the code output here, verify_dirty needs to parse it.
2982 emit_loadlp(addr,1);
2983 emit_loadlp((int)copy,2);
2984 emit_loadlp(slen*4,3);
2986 emit_movw(addr&0x0000FFFF,1);
2987 emit_movw(((u_int)copy)&0x0000FFFF,2);
2988 emit_movt(addr&0xFFFF0000,1);
2989 emit_movt(((u_int)copy)&0xFFFF0000,2);
2990 emit_movw(slen*4,3);
2992 emit_movimm(start+i*4,0);
2993 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2996 if(entry==(int)out) entry=instr_addr[i];
2997 emit_jmp(instr_addr[i]);
3001 void do_dirty_stub_ds()
3003 // Careful about the code output here, verify_dirty needs to parse it.
3005 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3006 emit_loadlp((int)copy,2);
3007 emit_loadlp(slen*4,3);
3009 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3010 emit_movw(((u_int)copy)&0x0000FFFF,2);
3011 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3012 emit_movt(((u_int)copy)&0xFFFF0000,2);
3013 emit_movw(slen*4,3);
3015 emit_movimm(start+1,0);
3016 emit_call((int)&verify_code_ds);
3022 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3023 set_jump_target(stubs[n][1],(int)out);
3025 // int rs=stubs[n][4];
3026 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3029 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3030 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3032 //else {printf("fp exception in delay slot\n");}
3033 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3034 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3035 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3036 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3037 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3042 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3045 if((signed int)addr>=(signed int)0xC0000000) {
3046 // address_generation already loaded the const
3047 emit_readword_dualindexedx4(FP,map,map);
3050 return -1; // No mapping
3054 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3055 emit_addsr12(map,s,map);
3056 // Schedule this while we wait on the load
3057 //if(x) emit_xorimm(s,x,ar);
3058 if(shift>=0) emit_shlimm(s,3,shift);
3059 if(~a) emit_andimm(s,a,ar);
3060 emit_readword_dualindexedx4(FP,map,map);
3064 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3066 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3074 int gen_tlb_addr_r(int ar, int map) {
3076 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3077 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3081 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3084 if(addr<0x80800000||addr>=0xC0000000) {
3085 // address_generation already loaded the const
3086 emit_readword_dualindexedx4(FP,map,map);
3089 return -1; // No mapping
3093 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3094 emit_addsr12(map,s,map);
3095 // Schedule this while we wait on the load
3096 //if(x) emit_xorimm(s,x,ar);
3097 emit_readword_dualindexedx4(FP,map,map);
3101 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3103 if(!c||addr<0x80800000||addr>=0xC0000000) {
3104 emit_testimm(map,0x40000000);
3110 int gen_tlb_addr_w(int ar, int map) {
3112 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3113 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3117 // Generate the address of the memory_map entry, relative to dynarec_local
3118 generate_map_const(u_int addr,int reg) {
3119 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3120 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3125 void shift_assemble_arm(int i,struct regstat *i_regs)
3128 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3130 signed char s,t,shift;
3131 t=get_reg(i_regs->regmap,rt1[i]);
3132 s=get_reg(i_regs->regmap,rs1[i]);
3133 shift=get_reg(i_regs->regmap,rs2[i]);
3142 if(s!=t) emit_mov(s,t);
3146 emit_andimm(shift,31,HOST_TEMPREG);
3147 if(opcode2[i]==4) // SLLV
3149 emit_shl(s,HOST_TEMPREG,t);
3151 if(opcode2[i]==6) // SRLV
3153 emit_shr(s,HOST_TEMPREG,t);
3155 if(opcode2[i]==7) // SRAV
3157 emit_sar(s,HOST_TEMPREG,t);
3161 } else { // DSLLV/DSRLV/DSRAV
3162 signed char sh,sl,th,tl,shift;
3163 th=get_reg(i_regs->regmap,rt1[i]|64);
3164 tl=get_reg(i_regs->regmap,rt1[i]);
3165 sh=get_reg(i_regs->regmap,rs1[i]|64);
3166 sl=get_reg(i_regs->regmap,rs1[i]);
3167 shift=get_reg(i_regs->regmap,rs2[i]);
3172 if(th>=0) emit_zeroreg(th);
3177 if(sl!=tl) emit_mov(sl,tl);
3178 if(th>=0&&sh!=th) emit_mov(sh,th);
3182 // FIXME: What if shift==tl ?
3184 int temp=get_reg(i_regs->regmap,-1);
3186 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3189 emit_andimm(shift,31,HOST_TEMPREG);
3190 if(opcode2[i]==0x14) // DSLLV
3192 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3193 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3194 emit_orrshr(sl,HOST_TEMPREG,th);
3195 emit_andimm(shift,31,HOST_TEMPREG);
3196 emit_testimm(shift,32);
3197 emit_shl(sl,HOST_TEMPREG,tl);
3198 if(th>=0) emit_cmovne_reg(tl,th);
3199 emit_cmovne_imm(0,tl);
3201 if(opcode2[i]==0x16) // DSRLV
3204 emit_shr(sl,HOST_TEMPREG,tl);
3205 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3206 emit_orrshl(sh,HOST_TEMPREG,tl);
3207 emit_andimm(shift,31,HOST_TEMPREG);
3208 emit_testimm(shift,32);
3209 emit_shr(sh,HOST_TEMPREG,th);
3210 emit_cmovne_reg(th,tl);
3211 if(real_th>=0) emit_cmovne_imm(0,th);
3213 if(opcode2[i]==0x17) // DSRAV
3216 emit_shr(sl,HOST_TEMPREG,tl);
3217 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3220 emit_sarimm(th,31,temp);
3222 emit_orrshl(sh,HOST_TEMPREG,tl);
3223 emit_andimm(shift,31,HOST_TEMPREG);
3224 emit_testimm(shift,32);
3225 emit_sar(sh,HOST_TEMPREG,th);
3226 emit_cmovne_reg(th,tl);
3227 if(real_th>=0) emit_cmovne_reg(temp,th);
3234 #define shift_assemble shift_assemble_arm
3236 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3238 int s,th,tl,temp,temp2,addr,map=-1;
3243 th=get_reg(i_regs->regmap,rt1[i]|64);
3244 tl=get_reg(i_regs->regmap,rt1[i]);
3245 s=get_reg(i_regs->regmap,rs1[i]);
3246 temp=get_reg(i_regs->regmap,-1);
3247 temp2=get_reg(i_regs->regmap,FTEMP);
3248 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3251 for(hr=0;hr<HOST_REGS;hr++) {
3252 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3255 if(offset||s<0||c) addr=temp2;
3258 c=(i_regs->wasconst>>s)&1;
3259 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3260 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3267 emit_shlimm(addr,3,temp);
3268 if (opcode[i]==0x22||opcode[i]==0x26) {
3269 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3271 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3273 emit_cmpimm(addr,RAM_SIZE);
3278 if (opcode[i]==0x22||opcode[i]==0x26) {
3279 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3281 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3288 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3289 a=0xFFFFFFFC; // LWL/LWR
3291 a=0xFFFFFFF8; // LDL/LDR
3293 map=get_reg(i_regs->regmap,TLREG);
3295 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3297 if (opcode[i]==0x22||opcode[i]==0x26) {
3298 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3300 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3303 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3305 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3307 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3308 emit_readword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2);
3309 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3312 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3313 emit_andimm(temp,24,temp);
3314 #ifdef BIG_ENDIAN_MIPS
3315 if (opcode[i]==0x26) // LWR
3317 if (opcode[i]==0x22) // LWL
3319 emit_xorimm(temp,24,temp);
3320 emit_movimm(-1,HOST_TEMPREG);
3321 if (opcode[i]==0x26) {
3322 emit_shr(temp2,temp,temp2);
3323 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3325 emit_shl(temp2,temp,temp2);
3326 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3328 emit_or(temp2,tl,tl);
3329 //emit_storereg(rt1[i],tl); // DEBUG
3331 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3332 // FIXME: little endian
3333 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3335 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3336 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3337 emit_readdword_indexed_tlb((int)rdram-0x80000000,temp2,map,temp2h,temp2);
3338 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3341 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3342 emit_testimm(temp,32);
3343 emit_andimm(temp,24,temp);
3344 if (opcode[i]==0x1A) { // LDL
3345 emit_rsbimm(temp,32,HOST_TEMPREG);
3346 emit_shl(temp2h,temp,temp2h);
3347 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3348 emit_movimm(-1,HOST_TEMPREG);
3349 emit_shl(temp2,temp,temp2);
3350 emit_cmove_reg(temp2h,th);
3351 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3352 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3353 emit_orreq(temp2,tl,tl);
3354 emit_orrne(temp2,th,th);
3356 if (opcode[i]==0x1B) { // LDR
3357 emit_xorimm(temp,24,temp);
3358 emit_rsbimm(temp,32,HOST_TEMPREG);
3359 emit_shr(temp2,temp,temp2);
3360 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3361 emit_movimm(-1,HOST_TEMPREG);
3362 emit_shr(temp2h,temp,temp2h);
3363 emit_cmovne_reg(temp2,tl);
3364 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3365 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3366 emit_orrne(temp2h,th,th);
3367 emit_orreq(temp2h,tl,tl);
3372 #define loadlr_assemble loadlr_assemble_arm
3374 void cop0_assemble(int i,struct regstat *i_regs)
3376 if(opcode2[i]==0) // MFC0
3378 signed char t=get_reg(i_regs->regmap,rt1[i]);
3379 char copr=(source[i]>>11)&0x1f;
3380 //assert(t>=0); // Why does this happen? OOT is weird
3381 if(t>=0&&rt1[i]!=0) {
3383 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3384 emit_movimm((source[i]>>11)&0x1f,1);
3385 emit_writeword(0,(int)&PC);
3386 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3388 emit_readword((int)&last_count,ECX);
3389 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3390 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3391 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3392 emit_writeword(HOST_CCREG,(int)&Count);
3394 emit_call((int)MFC0);
3395 emit_readword((int)&readmem_dword,t);
3397 emit_readword((int)®_cop0+copr*4,t);
3401 else if(opcode2[i]==4) // MTC0
3403 signed char s=get_reg(i_regs->regmap,rs1[i]);
3404 char copr=(source[i]>>11)&0x1f;
3406 emit_writeword(s,(int)&readmem_dword);
3407 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3408 #ifdef MUPEN64 /// FIXME
3409 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3410 emit_movimm((source[i]>>11)&0x1f,1);
3411 emit_writeword(0,(int)&PC);
3412 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3415 emit_movimm(source[i],0);
3416 emit_writeword(0,(int)&psxRegs.code);
3418 if(copr==9||copr==11||copr==12||copr==13) {
3419 emit_readword((int)&last_count,ECX);
3420 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3421 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3422 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3423 emit_writeword(HOST_CCREG,(int)&Count);
3425 // What a mess. The status register (12) can enable interrupts,
3426 // so needs a special case to handle a pending interrupt.
3427 // The interrupt must be taken immediately, because a subsequent
3428 // instruction might disable interrupts again.
3429 if(copr==12||copr==13) {
3430 emit_movimm(start+i*4+4,0);
3432 emit_writeword(0,(int)&pcaddr);
3433 emit_writeword(1,(int)&pending_exception);
3435 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3437 emit_call((int)MTC0);
3438 if(copr==9||copr==11||copr==12||copr==13) {
3439 emit_readword((int)&Count,HOST_CCREG);
3440 emit_readword((int)&next_interupt,ECX);
3441 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3442 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3443 emit_writeword(ECX,(int)&last_count);
3444 emit_storereg(CCREG,HOST_CCREG);
3446 if(copr==12||copr==13) {
3447 assert(!is_delayslot);
3448 emit_readword((int)&pending_exception,14);
3450 emit_loadreg(rs1[i],s);
3451 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3452 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3453 if(copr==12||copr==13) {
3455 emit_jne((int)&do_interrupt);
3461 assert(opcode2[i]==0x10);
3463 if((source[i]&0x3f)==0x01) // TLBR
3464 emit_call((int)TLBR);
3465 if((source[i]&0x3f)==0x02) // TLBWI
3466 emit_call((int)TLBWI_new);
3467 if((source[i]&0x3f)==0x06) { // TLBWR
3468 // The TLB entry written by TLBWR is dependent on the count,
3469 // so update the cycle count
3470 emit_readword((int)&last_count,ECX);
3471 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3472 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3473 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3474 emit_writeword(HOST_CCREG,(int)&Count);
3475 emit_call((int)TLBWR_new);
3477 if((source[i]&0x3f)==0x08) // TLBP
3478 emit_call((int)TLBP);
3481 if((source[i]&0x3f)==0x10) // RFE
3483 emit_readword((int)&Status,0);
3484 emit_andimm(0,0x3c,1);
3485 emit_andimm(0,~0xf,0);
3486 emit_orrshr_imm(1,2,0);
3487 emit_writeword(0,(int)&Status);
3490 if((source[i]&0x3f)==0x18) // ERET
3493 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3494 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3495 emit_jmp((int)jump_eret);
3501 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3511 emit_readword((int)®_cop2d[copr],tl);
3512 emit_signextend16(tl,tl);
3513 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3520 emit_readword((int)®_cop2d[copr],tl);
3521 emit_andimm(tl,0xffff,tl);
3522 emit_writeword(tl,(int)®_cop2d[copr]);
3525 emit_readword((int)®_cop2d[14],tl); // SXY2
3526 emit_writeword(tl,(int)®_cop2d[copr]);
3533 emit_readword((int)®_cop2d[9],temp);
3534 emit_testimm(temp,0x8000); // do we need this?
3535 emit_andimm(temp,0xf80,temp);
3536 emit_andne_imm(temp,0,temp);
3537 emit_shr(temp,7,tl);
3538 emit_readword((int)®_cop2d[10],temp);
3539 emit_testimm(temp,0x8000);
3540 emit_andimm(temp,0xf80,temp);
3541 emit_andne_imm(temp,0,temp);
3542 emit_orrshr(temp,2,tl);
3543 emit_readword((int)®_cop2d[11],temp);
3544 emit_testimm(temp,0x8000);
3545 emit_andimm(temp,0xf80,temp);
3546 emit_andne_imm(temp,0,temp);
3547 emit_orrshl(temp,3,tl);
3548 emit_writeword(tl,(int)®_cop2d[copr]);
3551 emit_readword((int)®_cop2d[copr],tl);
3556 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3560 emit_readword((int)®_cop2d[13],temp); // SXY1
3561 emit_writeword(sl,(int)®_cop2d[copr]);
3562 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3563 emit_readword((int)®_cop2d[14],temp); // SXY2
3564 emit_writeword(sl,(int)®_cop2d[14]);
3565 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3568 emit_andimm(sl,0x001f,temp);
3569 emit_shl(temp,7,temp);
3570 emit_writeword(temp,(int)®_cop2d[9]);
3571 emit_andimm(sl,0x03e0,temp);
3572 emit_shl(temp,2,temp);
3573 emit_writeword(temp,(int)®_cop2d[10]);
3574 emit_andimm(sl,0x7c00,temp);
3575 emit_shr(temp,3,temp);
3576 emit_writeword(temp,(int)®_cop2d[11]);
3577 emit_writeword(sl,(int)®_cop2d[28]);
3581 emit_mvnmi(temp,temp);
3582 emit_clz(temp,temp);
3583 emit_writeword(sl,(int)®_cop2d[30]);
3584 emit_writeword(temp,(int)®_cop2d[31]);
3591 emit_writeword(sl,(int)®_cop2d[copr]);
3596 void cop2_assemble(int i,struct regstat *i_regs)
3598 u_int copr=(source[i]>>11)&0x1f;
3599 signed char temp=get_reg(i_regs->regmap,-1);
3600 if (opcode2[i]==0) { // MFC2
3601 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3602 if(tl>=0&&rt1[i]!=0)
3603 cop2_get_dreg(copr,tl,temp);
3605 else if (opcode2[i]==4) { // MTC2
3606 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3607 cop2_put_dreg(copr,sl,temp);
3609 else if (opcode2[i]==2) // CFC2
3611 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3612 if(tl>=0&&rt1[i]!=0)
3613 emit_readword((int)®_cop2c[copr],tl);
3615 else if (opcode2[i]==6) // CTC2
3617 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3626 emit_signextend16(sl,temp);
3629 //value = value & 0x7ffff000;
3630 //if (value & 0x7f87e000) value |= 0x80000000;
3631 emit_shrimm(sl,12,temp);
3632 emit_shlimm(temp,12,temp);
3633 emit_testimm(temp,0x7f000000);
3634 emit_testeqimm(temp,0x00870000);
3635 emit_testeqimm(temp,0x0000e000);
3636 emit_orrne_imm(temp,0x80000000,temp);
3642 emit_writeword(temp,(int)®_cop2c[copr]);
3647 void c2op_assemble(int i,struct regstat *i_regs)
3649 signed char temp=get_reg(i_regs->regmap,-1);
3650 u_int c2op=source[i]&0x3f;
3652 for(hr=0;hr<HOST_REGS;hr++) {
3653 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3655 if(i==0||itype[i-1]!=C2OP)
3658 if (gte_handlers[c2op]!=NULL) {
3659 int cc=get_reg(i_regs->regmap,CCREG);
3660 emit_movimm(source[i],temp); // opcode
3661 if (cc>=0&>e_cycletab[c2op])
3662 emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj?
3663 emit_writeword(temp,(int)&psxRegs.code);
3664 emit_call((int)gte_handlers[c2op]);
3667 if(i>=slen-1||itype[i+1]!=C2OP)
3668 restore_regs(reglist);
3671 void cop1_unusable(int i,struct regstat *i_regs)
3673 // XXX: should just just do the exception instead
3677 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3682 void cop1_assemble(int i,struct regstat *i_regs)
3684 #ifndef DISABLE_COP1
3685 // Check cop1 unusable
3687 signed char rs=get_reg(i_regs->regmap,CSREG);
3689 emit_testimm(rs,0x20000000);
3692 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3695 if (opcode2[i]==0) { // MFC1
3696 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3698 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3699 emit_readword_indexed(0,tl,tl);
3702 else if (opcode2[i]==1) { // DMFC1
3703 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3704 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3706 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3707 if(th>=0) emit_readword_indexed(4,tl,th);
3708 emit_readword_indexed(0,tl,tl);
3711 else if (opcode2[i]==4) { // MTC1
3712 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3713 signed char temp=get_reg(i_regs->regmap,-1);
3714 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3715 emit_writeword_indexed(sl,0,temp);
3717 else if (opcode2[i]==5) { // DMTC1
3718 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3719 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3720 signed char temp=get_reg(i_regs->regmap,-1);
3721 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3722 emit_writeword_indexed(sh,4,temp);
3723 emit_writeword_indexed(sl,0,temp);
3725 else if (opcode2[i]==2) // CFC1
3727 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3729 u_int copr=(source[i]>>11)&0x1f;
3730 if(copr==0) emit_readword((int)&FCR0,tl);
3731 if(copr==31) emit_readword((int)&FCR31,tl);
3734 else if (opcode2[i]==6) // CTC1
3736 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3737 u_int copr=(source[i]>>11)&0x1f;
3741 emit_writeword(sl,(int)&FCR31);
3742 // Set the rounding mode
3744 //char temp=get_reg(i_regs->regmap,-1);
3745 //emit_andimm(sl,3,temp);
3746 //emit_fldcw_indexed((int)&rounding_modes,temp);
3750 cop1_unusable(i, i_regs);
3754 void fconv_assemble_arm(int i,struct regstat *i_regs)
3756 #ifndef DISABLE_COP1
3757 signed char temp=get_reg(i_regs->regmap,-1);
3759 // Check cop1 unusable
3761 signed char rs=get_reg(i_regs->regmap,CSREG);
3763 emit_testimm(rs,0x20000000);
3766 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3770 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3771 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3772 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3774 emit_ftosizs(15,15); // float->int, truncate
3775 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3776 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3780 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3781 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3783 emit_ftosizd(7,13); // double->int, truncate
3784 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3789 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3790 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3792 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3793 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3798 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3799 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3801 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3807 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3808 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3810 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3815 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3816 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3818 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3828 for(hr=0;hr<HOST_REGS;hr++) {
3829 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3833 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3834 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3835 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3836 emit_call((int)cvt_s_w);
3838 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3839 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3840 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3841 emit_call((int)cvt_d_w);
3843 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3844 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3845 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3846 emit_call((int)cvt_s_l);
3848 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3849 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3850 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3851 emit_call((int)cvt_d_l);
3854 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
3855 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3856 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3857 emit_call((int)cvt_d_s);
3859 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
3860 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3861 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3862 emit_call((int)cvt_w_s);
3864 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
3865 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3866 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3867 emit_call((int)cvt_l_s);
3870 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
3871 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3872 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3873 emit_call((int)cvt_s_d);
3875 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
3876 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3877 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3878 emit_call((int)cvt_w_d);
3880 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
3881 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3882 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3883 emit_call((int)cvt_l_d);
3886 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
3887 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3888 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3889 emit_call((int)round_l_s);
3891 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
3892 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3893 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3894 emit_call((int)trunc_l_s);
3896 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
3897 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3898 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3899 emit_call((int)ceil_l_s);
3901 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
3902 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3903 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3904 emit_call((int)floor_l_s);
3906 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
3907 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3908 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3909 emit_call((int)round_w_s);
3911 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
3912 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3913 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3914 emit_call((int)trunc_w_s);
3916 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
3917 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3918 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3919 emit_call((int)ceil_w_s);
3921 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
3922 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3923 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3924 emit_call((int)floor_w_s);
3927 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
3928 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3929 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3930 emit_call((int)round_l_d);
3932 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
3933 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3934 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3935 emit_call((int)trunc_l_d);
3937 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
3938 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3939 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3940 emit_call((int)ceil_l_d);
3942 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
3943 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3944 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3945 emit_call((int)floor_l_d);
3947 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
3948 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3949 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3950 emit_call((int)round_w_d);
3952 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
3953 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3954 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3955 emit_call((int)trunc_w_d);
3957 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
3958 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3959 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3960 emit_call((int)ceil_w_d);
3962 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
3963 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3964 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3965 emit_call((int)floor_w_d);
3968 restore_regs(reglist);
3970 cop1_unusable(i, i_regs);
3973 #define fconv_assemble fconv_assemble_arm
3975 void fcomp_assemble(int i,struct regstat *i_regs)
3977 #ifndef DISABLE_COP1
3978 signed char fs=get_reg(i_regs->regmap,FSREG);
3979 signed char temp=get_reg(i_regs->regmap,-1);
3981 // Check cop1 unusable
3983 signed char cs=get_reg(i_regs->regmap,CSREG);
3985 emit_testimm(cs,0x20000000);
3988 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
3992 if((source[i]&0x3f)==0x30) {
3993 emit_andimm(fs,~0x800000,fs);
3997 if((source[i]&0x3e)==0x38) {
3998 // sf/ngle - these should throw exceptions for NaNs
3999 emit_andimm(fs,~0x800000,fs);
4003 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4004 if(opcode2[i]==0x10) {
4005 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4006 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4007 emit_orimm(fs,0x800000,fs);
4009 emit_flds(HOST_TEMPREG,15);
4012 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4013 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4014 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4015 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4016 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4017 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4018 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4019 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4020 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4021 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4022 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4023 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4024 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
4027 if(opcode2[i]==0x11) {
4028 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4029 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4030 emit_orimm(fs,0x800000,fs);
4032 emit_vldr(HOST_TEMPREG,7);
4035 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4036 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4037 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4038 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4039 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4040 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4041 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4042 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4043 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4044 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4045 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4046 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4047 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4055 for(hr=0;hr<HOST_REGS;hr++) {
4056 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4060 if(opcode2[i]==0x10) {
4061 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4062 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4063 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4064 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4065 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4066 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4067 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4068 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4069 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4070 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4071 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4072 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4073 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4074 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4075 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
4076 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
4077 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
4078 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
4080 if(opcode2[i]==0x11) {
4081 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4082 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4083 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
4084 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
4085 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
4086 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
4087 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
4088 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
4089 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
4090 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
4091 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
4092 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
4093 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
4094 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
4095 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
4096 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
4097 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
4098 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
4100 restore_regs(reglist);
4101 emit_loadreg(FSREG,fs);
4103 cop1_unusable(i, i_regs);
4107 void float_assemble(int i,struct regstat *i_regs)
4109 #ifndef DISABLE_COP1
4110 signed char temp=get_reg(i_regs->regmap,-1);
4112 // Check cop1 unusable
4114 signed char cs=get_reg(i_regs->regmap,CSREG);
4116 emit_testimm(cs,0x20000000);
4119 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4123 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4124 if((source[i]&0x3f)==6) // mov
4126 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4127 if(opcode2[i]==0x10) {
4128 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4129 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
4130 emit_readword_indexed(0,temp,temp);
4131 emit_writeword_indexed(temp,0,HOST_TEMPREG);
4133 if(opcode2[i]==0x11) {
4134 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4135 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
4137 emit_vstr(7,HOST_TEMPREG);
4143 if((source[i]&0x3f)>3)
4145 if(opcode2[i]==0x10) {
4146 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4148 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4149 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4151 if((source[i]&0x3f)==4) // sqrt
4153 if((source[i]&0x3f)==5) // abs
4155 if((source[i]&0x3f)==7) // neg
4159 if(opcode2[i]==0x11) {
4160 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4162 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4163 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4165 if((source[i]&0x3f)==4) // sqrt
4167 if((source[i]&0x3f)==5) // abs
4169 if((source[i]&0x3f)==7) // neg
4175 if((source[i]&0x3f)<4)
4177 if(opcode2[i]==0x10) {
4178 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4180 if(opcode2[i]==0x11) {
4181 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4183 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
4184 if(opcode2[i]==0x10) {
4185 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4187 emit_flds(HOST_TEMPREG,13);
4188 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4189 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4190 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4193 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
4194 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
4195 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
4196 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
4197 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4198 emit_fsts(15,HOST_TEMPREG);
4203 else if(opcode2[i]==0x11) {
4204 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4206 emit_vldr(HOST_TEMPREG,6);
4207 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4208 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4209 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4212 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
4213 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
4214 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
4215 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
4216 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4217 emit_vstr(7,HOST_TEMPREG);
4224 if(opcode2[i]==0x10) {
4226 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4227 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4229 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
4230 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
4231 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
4232 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
4235 else if(opcode2[i]==0x11) {
4237 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4238 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4240 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
4241 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
4242 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
4243 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
4252 for(hr=0;hr<HOST_REGS;hr++) {
4253 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4255 if(opcode2[i]==0x10) { // Single precision
4257 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4258 if((source[i]&0x3f)<4) {
4259 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4260 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
4262 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4264 switch(source[i]&0x3f)
4266 case 0x00: emit_call((int)add_s);break;
4267 case 0x01: emit_call((int)sub_s);break;
4268 case 0x02: emit_call((int)mul_s);break;
4269 case 0x03: emit_call((int)div_s);break;
4270 case 0x04: emit_call((int)sqrt_s);break;
4271 case 0x05: emit_call((int)abs_s);break;
4272 case 0x06: emit_call((int)mov_s);break;
4273 case 0x07: emit_call((int)neg_s);break;
4275 restore_regs(reglist);
4277 if(opcode2[i]==0x11) { // Double precision
4279 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4280 if((source[i]&0x3f)<4) {
4281 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4282 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
4284 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4286 switch(source[i]&0x3f)
4288 case 0x00: emit_call((int)add_d);break;
4289 case 0x01: emit_call((int)sub_d);break;
4290 case 0x02: emit_call((int)mul_d);break;
4291 case 0x03: emit_call((int)div_d);break;
4292 case 0x04: emit_call((int)sqrt_d);break;
4293 case 0x05: emit_call((int)abs_d);break;
4294 case 0x06: emit_call((int)mov_d);break;
4295 case 0x07: emit_call((int)neg_d);break;
4297 restore_regs(reglist);
4300 cop1_unusable(i, i_regs);
4304 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4311 // case 0x1D: DMULTU
4316 if((opcode2[i]&4)==0) // 32-bit
4318 if(opcode2[i]==0x18) // MULT
4320 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4321 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4322 signed char hi=get_reg(i_regs->regmap,HIREG);
4323 signed char lo=get_reg(i_regs->regmap,LOREG);
4328 emit_smull(m1,m2,hi,lo);
4330 if(opcode2[i]==0x19) // MULTU
4332 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4333 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4334 signed char hi=get_reg(i_regs->regmap,HIREG);
4335 signed char lo=get_reg(i_regs->regmap,LOREG);
4340 emit_umull(m1,m2,hi,lo);
4342 if(opcode2[i]==0x1A) // DIV
4344 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4345 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4348 signed char quotient=get_reg(i_regs->regmap,LOREG);
4349 signed char remainder=get_reg(i_regs->regmap,HIREG);
4350 assert(quotient>=0);
4351 assert(remainder>=0);
4352 emit_movs(d1,remainder);
4353 emit_negmi(remainder,remainder);
4354 emit_movs(d2,HOST_TEMPREG);
4355 emit_jeq((int)out+52); // Division by zero
4356 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
4357 emit_clz(HOST_TEMPREG,quotient);
4358 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4359 emit_orimm(quotient,1<<31,quotient);
4360 emit_shr(quotient,quotient,quotient);
4361 emit_cmp(remainder,HOST_TEMPREG);
4362 emit_subcs(remainder,HOST_TEMPREG,remainder);
4363 emit_adcs(quotient,quotient,quotient);
4364 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4365 emit_jcc((int)out-16); // -4
4367 emit_negmi(quotient,quotient);
4369 emit_negmi(remainder,remainder);
4371 if(opcode2[i]==0x1B) // DIVU
4373 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4374 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4377 signed char quotient=get_reg(i_regs->regmap,LOREG);
4378 signed char remainder=get_reg(i_regs->regmap,HIREG);
4379 assert(quotient>=0);
4380 assert(remainder>=0);
4382 emit_jeq((int)out+44); // Division by zero
4383 emit_clz(d2,HOST_TEMPREG);
4384 emit_movimm(1<<31,quotient);
4385 emit_shl(d2,HOST_TEMPREG,d2);
4386 emit_mov(d1,remainder);
4387 emit_shr(quotient,HOST_TEMPREG,quotient);
4388 emit_cmp(remainder,d2);
4389 emit_subcs(remainder,d2,remainder);
4390 emit_adcs(quotient,quotient,quotient);
4391 emit_shrcc_imm(d2,1,d2);
4392 emit_jcc((int)out-16); // -4
4397 if(opcode2[i]==0x1C) // DMULT
4399 assert(opcode2[i]!=0x1C);
4400 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4401 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4402 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4403 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4412 emit_call((int)&mult64);
4417 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4418 signed char hil=get_reg(i_regs->regmap,HIREG);
4419 if(hih>=0) emit_loadreg(HIREG|64,hih);
4420 if(hil>=0) emit_loadreg(HIREG,hil);
4421 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4422 signed char lol=get_reg(i_regs->regmap,LOREG);
4423 if(loh>=0) emit_loadreg(LOREG|64,loh);
4424 if(lol>=0) emit_loadreg(LOREG,lol);
4426 if(opcode2[i]==0x1D) // DMULTU
4428 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4429 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4430 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4431 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4437 if(m1l!=0) emit_mov(m1l,0);
4438 if(m1h==0) emit_readword((int)&dynarec_local,1);
4439 else if(m1h>1) emit_mov(m1h,1);
4440 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
4441 else if(m2l>2) emit_mov(m2l,2);
4442 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
4443 else if(m2h>3) emit_mov(m2h,3);
4444 emit_call((int)&multu64);
4445 restore_regs(0x100f);
4446 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4447 signed char hil=get_reg(i_regs->regmap,HIREG);
4448 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4449 signed char lol=get_reg(i_regs->regmap,LOREG);
4450 /*signed char temp=get_reg(i_regs->regmap,-1);
4451 signed char rh=get_reg(i_regs->regmap,HIREG|64);
4452 signed char rl=get_reg(i_regs->regmap,HIREG);
4458 //emit_mov(m1l,EAX);
4460 emit_umull(rl,rh,m1l,m2l);
4461 emit_storereg(LOREG,rl);
4463 //emit_mov(m1h,EAX);
4465 emit_umull(rl,rh,m1h,m2l);
4466 emit_adds(rl,temp,temp);
4467 emit_adcimm(rh,0,rh);
4468 emit_storereg(HIREG,rh);
4469 //emit_mov(m2h,EAX);
4471 emit_umull(rl,rh,m1l,m2h);
4472 emit_adds(rl,temp,temp);
4473 emit_adcimm(rh,0,rh);
4474 emit_storereg(LOREG|64,temp);
4476 //emit_mov(m2h,EAX);
4478 emit_umull(rl,rh,m1h,m2h);
4479 emit_adds(rl,temp,rl);
4480 emit_loadreg(HIREG,temp);
4481 emit_adcimm(rh,0,rh);
4482 emit_adds(rl,temp,rl);
4483 emit_adcimm(rh,0,rh);
4490 emit_call((int)&multu64);
4495 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4496 signed char hil=get_reg(i_regs->regmap,HIREG);
4497 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
4498 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
4500 // Shouldn't be necessary
4501 //char loh=get_reg(i_regs->regmap,LOREG|64);
4502 //char lol=get_reg(i_regs->regmap,LOREG);
4503 //if(loh>=0) emit_loadreg(LOREG|64,loh);
4504 //if(lol>=0) emit_loadreg(LOREG,lol);
4506 if(opcode2[i]==0x1E) // DDIV
4508 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4509 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4510 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4511 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4517 if(d1l!=0) emit_mov(d1l,0);
4518 if(d1h==0) emit_readword((int)&dynarec_local,1);
4519 else if(d1h>1) emit_mov(d1h,1);
4520 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4521 else if(d2l>2) emit_mov(d2l,2);
4522 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4523 else if(d2h>3) emit_mov(d2h,3);
4524 emit_call((int)&div64);
4525 restore_regs(0x100f);
4526 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4527 signed char hil=get_reg(i_regs->regmap,HIREG);
4528 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4529 signed char lol=get_reg(i_regs->regmap,LOREG);
4530 if(hih>=0) emit_loadreg(HIREG|64,hih);
4531 if(hil>=0) emit_loadreg(HIREG,hil);
4532 if(loh>=0) emit_loadreg(LOREG|64,loh);
4533 if(lol>=0) emit_loadreg(LOREG,lol);
4535 if(opcode2[i]==0x1F) // DDIVU
4537 //u_int hr,reglist=0;
4538 //for(hr=0;hr<HOST_REGS;hr++) {
4539 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
4541 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4542 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4543 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4544 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4550 if(d1l!=0) emit_mov(d1l,0);
4551 if(d1h==0) emit_readword((int)&dynarec_local,1);
4552 else if(d1h>1) emit_mov(d1h,1);
4553 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4554 else if(d2l>2) emit_mov(d2l,2);
4555 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4556 else if(d2h>3) emit_mov(d2h,3);
4557 emit_call((int)&divu64);
4558 restore_regs(0x100f);
4559 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4560 signed char hil=get_reg(i_regs->regmap,HIREG);
4561 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4562 signed char lol=get_reg(i_regs->regmap,LOREG);
4563 if(hih>=0) emit_loadreg(HIREG|64,hih);
4564 if(hil>=0) emit_loadreg(HIREG,hil);
4565 if(loh>=0) emit_loadreg(LOREG|64,loh);
4566 if(lol>=0) emit_loadreg(LOREG,lol);
4572 // Multiply by zero is zero.
4573 // MIPS does not have a divide by zero exception.
4574 // The result is undefined, we return zero.
4575 signed char hr=get_reg(i_regs->regmap,HIREG);
4576 signed char lr=get_reg(i_regs->regmap,LOREG);
4577 if(hr>=0) emit_zeroreg(hr);
4578 if(lr>=0) emit_zeroreg(lr);
4581 #define multdiv_assemble multdiv_assemble_arm
4583 void do_preload_rhash(int r) {
4584 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4585 // register. On ARM the hash can be done with a single instruction (below)
4588 void do_preload_rhtbl(int ht) {
4589 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4592 void do_rhash(int rs,int rh) {
4593 emit_andimm(rs,0xf8,rh);
4596 void do_miniht_load(int ht,int rh) {
4597 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4598 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4601 void do_miniht_jump(int rs,int rh,int ht) {
4603 emit_ldreq_indexed(ht,4,15);
4604 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4606 emit_jmp(jump_vaddr_reg[7]);
4608 emit_jmp(jump_vaddr_reg[rs]);
4612 void do_miniht_insert(u_int return_address,int rt,int temp) {
4614 emit_movimm(return_address,rt); // PC into link register
4615 add_to_linker((int)out,return_address,1);
4616 emit_pcreladdr(temp);
4617 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4618 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4620 emit_movw(return_address&0x0000FFFF,rt);
4621 add_to_linker((int)out,return_address,1);
4622 emit_pcreladdr(temp);
4623 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4624 emit_movt(return_address&0xFFFF0000,rt);
4625 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4629 // Sign-extend to 64 bits and write out upper half of a register
4630 // This is useful where we have a 32-bit value in a register, and want to
4631 // keep it in a 32-bit register, but can't guarantee that it won't be read
4632 // as a 64-bit value later.
4633 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
4636 if(is32_pre==is32) return;
4638 for(hr=0;hr<HOST_REGS;hr++) {
4639 if(hr!=EXCLUDE_REG) {
4640 //if(pre[hr]==entry[hr]) {
4641 if((reg=pre[hr])>=0) {
4643 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
4644 emit_sarimm(hr,31,HOST_TEMPREG);
4645 emit_storereg(reg|64,HOST_TEMPREG);
4655 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4657 //if(dirty_pre==dirty) return;
4659 for(hr=0;hr<HOST_REGS;hr++) {
4660 if(hr!=EXCLUDE_REG) {
4662 if(((~u)>>(reg&63))&1) {
4663 if(reg==entry[hr]||(reg>0&&entry[hr]<0)) {
4664 if(((dirty_pre&~dirty)>>hr)&1) {
4666 emit_storereg(reg,hr);
4667 if( ((is32_pre&~uu)>>reg)&1 ) {
4668 emit_sarimm(hr,31,HOST_TEMPREG);
4669 emit_storereg(reg|64,HOST_TEMPREG);
4673 emit_storereg(reg,hr);
4677 else // Check if register moved to a different register
4678 if((new_hr=get_reg(entry,reg))>=0) {
4679 if((dirty_pre>>hr)&(~dirty>>new_hr)&1) {
4681 emit_storereg(reg,hr);
4682 if( ((is32_pre&~uu)>>reg)&1 ) {
4683 emit_sarimm(hr,31,HOST_TEMPREG);
4684 emit_storereg(reg|64,HOST_TEMPREG);
4688 emit_storereg(reg,hr);
4698 /* using strd could possibly help but you'd have to allocate registers in pairs
4699 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4703 for(hr=HOST_REGS-1;hr>=0;hr--) {
4704 if(hr!=EXCLUDE_REG) {
4705 if(pre[hr]!=entry[hr]) {
4708 if(get_reg(entry,pre[hr])<0) {
4710 if(!((u>>pre[hr])&1)) {
4711 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4712 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4713 emit_sarimm(hr,31,hr+1);
4714 emit_strdreg(pre[hr],hr);
4717 emit_storereg(pre[hr],hr);
4719 emit_storereg(pre[hr],hr);
4720 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4721 emit_sarimm(hr,31,hr);
4722 emit_storereg(pre[hr]|64,hr);
4727 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4728 emit_storereg(pre[hr],hr);
4738 for(hr=0;hr<HOST_REGS;hr++) {
4739 if(hr!=EXCLUDE_REG) {
4740 if(pre[hr]!=entry[hr]) {
4743 if((nr=get_reg(entry,pre[hr]))>=0) {
4751 #define wb_invalidate wb_invalidate_arm
4754 // CPU-architecture-specific initialization
4756 #ifndef DISABLE_COP1
4757 rounding_modes[0]=0x0<<22; // round
4758 rounding_modes[1]=0x3<<22; // trunc
4759 rounding_modes[2]=0x1<<22; // ceil
4760 rounding_modes[3]=0x2<<22; // floor
4764 // vim:shiftwidth=2:expandtab