2 * (C) GraÅžvydas "notaz" Ignotas, 2010
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
15 //#define memprintf printf
16 #define memprintf(...)
18 static void read_mem8()
20 memprintf("ari64_read_mem8 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
21 readmem_word = psxMemRead8(address) & 0xff;
24 static void read_mem16()
26 memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
27 readmem_word = psxMemRead16(address) & 0xffff;
30 static void read_mem32()
32 memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
33 readmem_word = psxMemRead32(address);
36 static void write_mem8()
38 memprintf("ari64_write_mem8 %08x, %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
39 psxMemWrite8(address, byte);
42 static void write_mem16()
44 memprintf("ari64_write_mem16 %08x, %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
45 psxMemWrite16(address, hword);
48 static void write_mem32()
50 memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
51 psxMemWrite32(address, word);
54 static void read_mem_dummy()
59 static void write_mem_dummy()
63 extern void ari_read_ram8();
64 extern void ari_read_ram16();
65 extern void ari_read_ram32();
66 extern void ari_read_ram_mirror8();
67 extern void ari_read_ram_mirror16();
68 extern void ari_read_ram_mirror32();
69 extern void ari_write_ram8();
70 extern void ari_write_ram16();
71 extern void ari_write_ram32();
72 extern void ari_write_ram_mirror8();
73 extern void ari_write_ram_mirror16();
74 extern void ari_write_ram_mirror32();
75 extern void ari_read_io8();
76 extern void ari_read_io16();
77 extern void ari_read_io32();
78 extern void ari_write_io8();
79 extern void ari_write_io16();
80 extern void ari_write_io32();
82 void (*readmem[0x10000])();
83 void (*readmemb[0x10000])();
84 void (*readmemh[0x10000])();
85 void (*writemem[0x10000])();
86 void (*writememb[0x10000])();
87 void (*writememh[0x10000])();
90 static u32 io_read_sio16()
92 return sioRead8() | (sioRead8() << 8);
95 static u32 io_read_sio32()
97 return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
100 static void io_write_sio16(u32 value)
102 sioWrite8((unsigned char)value);
103 sioWrite8((unsigned char)(value>>8));
106 static void io_write_sio32(u32 value)
108 sioWrite8((unsigned char)value);
109 sioWrite8((unsigned char)((value&0xff) >> 8));
110 sioWrite8((unsigned char)((value&0xff) >> 16));
111 sioWrite8((unsigned char)((value&0xff) >> 24));
114 #define make_rcnt_funcs(i) \
115 static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
116 static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
117 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
118 static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
119 static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); } \
120 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
126 static void io_write_ireg16(u32 value)
128 if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
129 if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
130 psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
133 static void io_write_imask16(u32 value)
135 psxHu16ref(0x1074) = value;
136 if (psxHu16ref(0x1070) & value)
137 new_dyna_set_event(6, 1);
140 static void io_write_ireg32(u32 value)
142 if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
143 if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
144 psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
147 static void io_write_imask32(u32 value)
149 psxHu32ref(0x1074) = value;
150 if (psxHu32ref(0x1070) & value)
151 new_dyna_set_event(6, 1);
154 static void io_write_dma_icr32(u32 value)
156 u32 tmp = ~value & HW_DMA_ICR;
157 HW_DMA_ICR = ((tmp ^ value) & 0xffffff) ^ tmp;
160 #define make_dma_func(n) \
161 static void io_write_chcr##n(u32 value) \
163 HW_DMA##n##_CHCR = value; \
164 if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
165 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
176 /* IO tables for 1000-1880 */
177 #define IOADR8(a) ((a) & 0xfff)
178 #define IOADR16(a) (((a) & 0xfff) >> 1)
179 #define IOADR32(a) (((a) & 0xfff) >> 2)
181 static const void *io_read8 [0x880] = {
182 [IOADR8(0x1040)] = sioRead8,
183 [IOADR8(0x1800)] = cdrRead0,
184 [IOADR8(0x1801)] = cdrRead1,
185 [IOADR8(0x1802)] = cdrRead2,
186 [IOADR8(0x1803)] = cdrRead3,
188 static const void *io_read16[0x880/2] = {
189 [IOADR16(0x1040)] = io_read_sio16,
190 [IOADR16(0x1044)] = sioReadStat16,
191 [IOADR16(0x1048)] = sioReadMode16,
192 [IOADR16(0x104a)] = sioReadCtrl16,
193 [IOADR16(0x104e)] = sioReadBaud16,
194 [IOADR16(0x1100)] = io_rcnt_read_count0,
195 [IOADR16(0x1104)] = io_rcnt_read_mode0,
196 [IOADR16(0x1108)] = io_rcnt_read_target0,
197 [IOADR16(0x1110)] = io_rcnt_read_count1,
198 [IOADR16(0x1114)] = io_rcnt_read_mode1,
199 [IOADR16(0x1118)] = io_rcnt_read_target1,
200 [IOADR16(0x1120)] = io_rcnt_read_count2,
201 [IOADR16(0x1124)] = io_rcnt_read_mode2,
202 [IOADR16(0x1128)] = io_rcnt_read_target2,
204 static const void *io_read32[0x880/4] = {
205 [IOADR32(0x1040)] = io_read_sio32,
206 [IOADR32(0x1100)] = io_rcnt_read_count0,
207 [IOADR32(0x1104)] = io_rcnt_read_mode0,
208 [IOADR32(0x1108)] = io_rcnt_read_target0,
209 [IOADR32(0x1110)] = io_rcnt_read_count1,
210 [IOADR32(0x1114)] = io_rcnt_read_mode1,
211 [IOADR32(0x1118)] = io_rcnt_read_target1,
212 [IOADR32(0x1120)] = io_rcnt_read_count2,
213 [IOADR32(0x1124)] = io_rcnt_read_mode2,
214 [IOADR32(0x1128)] = io_rcnt_read_target2,
215 // [IOADR32(0x1810)] = GPU_readData,
216 // [IOADR32(0x1814)] = GPU_readStatus,
217 [IOADR32(0x1820)] = mdecRead0,
218 [IOADR32(0x1824)] = mdecRead1,
221 static const void *io_write8 [0x880] = {
222 [IOADR8(0x1040)] = sioWrite8,
223 [IOADR8(0x1800)] = cdrWrite0,
224 [IOADR8(0x1801)] = cdrWrite1,
225 [IOADR8(0x1802)] = cdrWrite2,
226 [IOADR8(0x1803)] = cdrWrite3,
228 static const void *io_write16[0x880/2] = {
229 [IOADR16(0x1040)] = io_write_sio16,
230 [IOADR16(0x1044)] = sioWriteStat16,
231 [IOADR16(0x1048)] = sioWriteMode16,
232 [IOADR16(0x104a)] = sioWriteCtrl16,
233 [IOADR16(0x104e)] = sioWriteBaud16,
234 [IOADR16(0x1070)] = io_write_ireg16,
235 [IOADR16(0x1074)] = io_write_imask16,
236 [IOADR16(0x1100)] = io_rcnt_write_count0,
237 [IOADR16(0x1104)] = io_rcnt_write_mode0,
238 [IOADR16(0x1108)] = io_rcnt_write_target0,
239 [IOADR16(0x1110)] = io_rcnt_write_count1,
240 [IOADR16(0x1114)] = io_rcnt_write_mode1,
241 [IOADR16(0x1118)] = io_rcnt_write_target1,
242 [IOADR16(0x1120)] = io_rcnt_write_count2,
243 [IOADR16(0x1124)] = io_rcnt_write_mode2,
244 [IOADR16(0x1128)] = io_rcnt_write_target2,
246 static const void *io_write32[0x880/4] = {
247 [IOADR32(0x1040)] = io_write_sio32,
248 [IOADR32(0x1070)] = io_write_ireg32,
249 [IOADR32(0x1074)] = io_write_imask32,
250 [IOADR32(0x1088)] = io_write_chcr0,
251 [IOADR32(0x1098)] = io_write_chcr1,
252 [IOADR32(0x10a8)] = io_write_chcr2,
253 [IOADR32(0x10b8)] = io_write_chcr3,
254 [IOADR32(0x10c8)] = io_write_chcr4,
255 [IOADR32(0x10e8)] = io_write_chcr6,
256 [IOADR32(0x10f4)] = io_write_dma_icr32,
257 [IOADR32(0x1100)] = io_rcnt_write_count0,
258 [IOADR32(0x1104)] = io_rcnt_write_mode0,
259 [IOADR32(0x1108)] = io_rcnt_write_target0,
260 [IOADR32(0x1110)] = io_rcnt_write_count1,
261 [IOADR32(0x1114)] = io_rcnt_write_mode1,
262 [IOADR32(0x1118)] = io_rcnt_write_target1,
263 [IOADR32(0x1120)] = io_rcnt_write_count2,
264 [IOADR32(0x1124)] = io_rcnt_write_mode2,
265 [IOADR32(0x1128)] = io_rcnt_write_target2,
266 // [IOADR32(0x1810)] = GPU_writeData,
267 // [IOADR32(0x1814)] = GPU_writeStatus,
268 [IOADR32(0x1820)] = mdecWrite0,
269 [IOADR32(0x1824)] = mdecWrite1,
272 // this has to be in .bss to link into dynarec_local
284 void new_dyna_pcsx_mem_init(void)
288 // default/unmapped handlers
289 for (i = 0; i < 0x10000; i++) {
290 readmemb[i] = read_mem8;
291 readmemh[i] = read_mem16;
292 readmem[i] = read_mem32;
293 writememb[i] = write_mem8;
294 writememh[i] = write_mem16;
295 writemem[i] = write_mem32;
297 readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy;
298 readmemb[i] = readmemh[i] = readmem[i] = write_mem_dummy;
304 for (i = 0; i < 0x80; i++) {
305 readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_ram_mirror8;
306 readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_ram_mirror16;
307 readmem[i] = readmem [0x8000|i] = readmem [0xa000|i] = ari_read_ram_mirror32;
308 writememb[i] = writememb[0x8000|i] = writememb[0xa000|i] = ari_write_ram_mirror8;
309 writememh[i] = writememh[0x8000|i] = writememh[0xa000|i] = ari_write_ram_mirror16;
310 writemem[i] = writemem [0x8000|i] = writemem [0xa000|i] = ari_write_ram_mirror32;
314 for (i = 0x8000; i < 0x8020; i++) {
315 readmemb[i] = ari_read_ram8;
316 readmemh[i] = ari_read_ram16;
317 readmem[i] = ari_read_ram32;
318 writememb[i] = ari_write_ram8;
319 writememh[i] = ari_write_ram16;
320 writemem[i] = ari_write_ram32;
324 readmemb[0x1f80] = ari_read_io8;
325 readmemh[0x1f80] = ari_read_io16;
326 readmem[0x1f80] = ari_read_io32;
327 writememb[0x1f80] = ari_write_io8;
328 writememh[0x1f80] = ari_write_io16;
329 writemem[0x1f80] = ari_write_io32;
331 writemem[0xfffe] = write_mem32;
335 nd_pcsx_io.tab_read8 = io_read8;
336 nd_pcsx_io.tab_read16 = io_read16;
337 nd_pcsx_io.tab_read32 = io_read32;
338 nd_pcsx_io.tab_write8 = io_write8;
339 nd_pcsx_io.tab_write16 = io_write16;
340 nd_pcsx_io.tab_write32 = io_write32;
343 void new_dyna_pcsx_mem_reset(void)
345 // plugins might change so update the pointers
346 nd_pcsx_io.spu_readf = SPU_readRegister;
347 nd_pcsx_io.spu_writef = SPU_writeRegister;
349 io_read32[IOADR32(0x1810)] = GPU_readData;
350 io_read32[IOADR32(0x1814)] = GPU_readStatus;
351 io_write32[IOADR32(0x1810)] = GPU_writeData;
352 io_write32[IOADR32(0x1814)] = GPU_writeStatus;