3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 #include "../pico_int.h"
9 #include "../sound/ym2612.h"
10 #include "../../cpu/sh2/compiler.h"
12 struct Pico32x Pico32x;
15 #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
17 static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
19 if (sh2->pending_irl > sh2->pending_int_irq) {
20 elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
22 return 64 + sh2->pending_irl / 2;
24 elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
25 level, sh2->pending_int_vector, sh2_pc(sh2));
26 sh2->pending_int_irq = 0; // auto-clear
27 sh2->pending_level = sh2->pending_irl;
28 return sh2->pending_int_vector;
32 // MUST specify active_sh2 when called from sh2 memhandlers
33 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
35 int irqs, mlvl = 0, slvl = 0;
38 if (active_sh2 != NULL)
39 m68k_cycles = sh2_cycles_done_m68k(active_sh2);
42 irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
48 irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
53 mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
55 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
56 if (active_sh2 == &msh2)
57 sh2_end_run(active_sh2, 1);
60 srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
62 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
63 if (active_sh2 == &ssh2)
64 sh2_end_run(active_sh2, 1);
67 elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
70 // the mask register is inconsistent, CMD is supposed to be a mask,
71 // while others are actually irq trigger enables?
73 void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
75 Pico32x.sh2irqs |= mask & P32XI_VRES;
76 Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
77 Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
79 p32x_update_irls(sh2, m68k_cycles);
82 void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
84 if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
85 Pico32x.sh2irqi[0] |= P32XI_CMD;
87 Pico32x.sh2irqi[0] &= ~P32XI_CMD;
89 if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
90 Pico32x.sh2irqi[1] |= P32XI_CMD;
92 Pico32x.sh2irqi[1] &= ~P32XI_CMD;
94 p32x_update_irls(sh2, m68k_cycles);
97 void Pico32xStartup(void)
99 elprintf(EL_STATUS|EL_32X, "32X startup");
101 // TODO: OOM handling
103 sh2_init(&msh2, 0, &ssh2);
104 msh2.irq_callback = sh2_irq_cb;
105 sh2_init(&ssh2, 1, &msh2);
106 ssh2.irq_callback = sh2_irq_cb;
109 p32x_pwm_ctl_changed();
110 p32x_timers_recalc();
112 Pico32x.sh2_regs[0] = P32XS2_ADEN;
114 Pico32x.sh2_regs[0] |= P32XS_nCART;
117 Pico32x.vdp_regs[0] |= P32XV_nPAL;
124 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
125 void p32x_reset_sh2s(void)
127 elprintf(EL_32X, "sh2 reset");
131 sh2_peripheral_reset(&msh2);
132 sh2_peripheral_reset(&ssh2);
134 // if we don't have BIOS set, perform it's work here.
136 if (p32x_bios_m == NULL) {
137 unsigned int idl_src, idl_dst, idl_size; // initial data load
141 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
142 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
143 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
144 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
145 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
146 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
147 idl_src, idl_dst, idl_size);
150 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
153 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
154 sh2_set_gbr(0, 0x20004000);
158 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
159 // program will set M_OK
163 if (p32x_bios_s == NULL) {
167 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
168 sh2_set_gbr(1, 0x20004000);
170 // program will set S_OK
173 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
176 void Pico32xInit(void)
178 if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
179 Pico32xSetClocks(PICO_MSH2_HZ, 0);
180 if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
181 Pico32xSetClocks(0, PICO_MSH2_HZ);
184 void PicoPower32x(void)
186 memset(&Pico32x, 0, sizeof(Pico32x));
188 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
189 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
192 void PicoUnload32x(void)
194 if (Pico32xMem != NULL)
195 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
200 PicoAHW &= ~PAHW_32X;
203 void PicoReset32x(void)
205 if (PicoAHW & PAHW_32X) {
206 p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
207 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
208 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
209 p32x_pwm_ctl_changed();
210 p32x_timers_recalc();
214 static void p32x_start_blank(void)
216 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
221 offs = 8; lines = 224;
222 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
227 // XXX: no proper handling of 32col mode..
228 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
229 (Pico.video.reg[12] & 1) && // 40col mode
230 (PicoDrawMask & PDRAW_32X_ON))
232 int md_bg = Pico.video.reg[7] & 0x3f;
234 // we draw full layer (not line-by-line)
235 PicoDraw32xLayer(offs, lines, md_bg);
237 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
238 PicoDraw32xLayerMdOnly(offs, lines);
244 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
246 // FB swap waits until vblank
247 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
248 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
249 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
250 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
253 p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
254 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
255 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
258 void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
260 // rather rough, 32x hint is useless in practice
263 if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
264 return; // nobody cares
265 // note: when Pico.m.scanline is 224, SH2s might
266 // still be at scanline 93 (or so)
267 if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
270 after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
272 p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
274 p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
278 static void fillend_event(unsigned int now)
280 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
281 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
282 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
285 static void hint_event(unsigned int now)
287 p32x_trigger_irq(NULL, now, P32XI_HINT);
288 p32x_schedule_hint(NULL, now);
291 typedef void (event_cb)(unsigned int now);
293 /* times are in m68k (7.6MHz) cycles */
294 unsigned int p32x_event_times[P32X_EVENT_COUNT];
295 static unsigned int event_time_next;
296 static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
302 // schedule event at some time 'after', in m68k clocks
303 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
307 when = (now + after) | 1;
309 elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
310 p32x_event_times[event] = when;
312 if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
313 event_time_next = when;
316 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
318 unsigned int now = sh2_cycles_done_m68k(sh2);
321 p32x_event_schedule(now, event, after);
323 left_to_next = (event_time_next - now) * 3;
324 sh2_end_run(sh2, left_to_next);
327 static void p32x_run_events(unsigned int until)
329 int oldest, oldest_diff, time;
333 oldest = -1, oldest_diff = 0x7fffffff;
335 for (i = 0; i < P32X_EVENT_COUNT; i++) {
336 if (p32x_event_times[i]) {
337 diff = p32x_event_times[i] - until;
338 if (diff < oldest_diff) {
345 if (oldest_diff <= 0) {
346 time = p32x_event_times[oldest];
347 p32x_event_times[oldest] = 0;
348 elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
349 p32x_event_cbs[oldest](time);
351 else if (oldest_diff < 0x7fffffff) {
352 event_time_next = p32x_event_times[oldest];
362 elprintf(EL_32X, "32x: next event #%d at %u",
363 oldest, event_time_next);
366 static INLINE void run_sh2(SH2 *sh2, int m68k_cycles)
370 pevt_log_sh2_o(sh2, EVT_RUN_START);
371 sh2->state |= SH2_STATE_RUN;
372 cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
373 elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
374 sh2->m68krcycles_done, cycles, sh2->pc);
376 done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC);
378 sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
379 sh2->state &= ~SH2_STATE_RUN;
380 pevt_log_sh2_o(sh2, EVT_RUN_END);
381 elprintf_sh2(sh2, EL_32X, "-run %u %d",
382 sh2->m68krcycles_done, done);
385 // sync other sh2 to this one
386 // note: recursive call
387 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
389 SH2 *osh2 = sh2->other_sh2;
393 if (osh2->state & SH2_STATE_RUN)
396 m68k_cycles = m68k_target - osh2->m68krcycles_done;
397 if (m68k_cycles < 200)
400 if (osh2->state & SH2_IDLE_STATES) {
401 osh2->m68krcycles_done = m68k_target;
405 elprintf_sh2(osh2, EL_32X, "sync to %u %d",
406 m68k_target, m68k_cycles);
408 run_sh2(osh2, m68k_cycles);
410 // there might be new event to schedule current sh2 to
411 if (event_time_next) {
412 left_to_event = event_time_next - m68k_target;
414 if (sh2_cycles_left(sh2) > left_to_event) {
415 if (left_to_event < 1)
417 sh2_end_run(sh2, left_to_event);
422 #define sync_sh2s_normal p32x_sync_sh2s
423 //#define sync_sh2s_lockstep p32x_sync_sh2s
425 /* most timing is in 68k clock */
426 void sync_sh2s_normal(unsigned int m68k_target)
428 unsigned int now, target, timer_cycles;
431 elprintf(EL_32X, "sh2 sync to %u", m68k_target);
433 if (!(Pico32x.regs[0] & P32XS_nRES)) {
434 msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
438 now = msh2.m68krcycles_done;
439 if (CYCLES_GT(now, ssh2.m68krcycles_done))
440 now = ssh2.m68krcycles_done;
443 while (CYCLES_GT(m68k_target, now))
445 if (event_time_next && CYCLES_GE(now, event_time_next))
446 p32x_run_events(now);
448 target = m68k_target;
449 if (event_time_next && CYCLES_GT(target, event_time_next))
450 target = event_time_next;
452 while (CYCLES_GT(target, now))
454 elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
455 target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
456 m68k_target - now, Pico32x.emu_flags);
458 if (!(ssh2.state & SH2_IDLE_STATES)) {
459 cycles = target - ssh2.m68krcycles_done;
461 run_sh2(&ssh2, cycles);
463 if (event_time_next && CYCLES_GT(target, event_time_next))
464 target = event_time_next;
468 if (!(msh2.state & SH2_IDLE_STATES)) {
469 cycles = target - msh2.m68krcycles_done;
471 run_sh2(&msh2, cycles);
473 if (event_time_next && CYCLES_GT(target, event_time_next))
474 target = event_time_next;
479 if (!(msh2.state & SH2_IDLE_STATES)) {
480 if (CYCLES_GT(now, msh2.m68krcycles_done))
481 now = msh2.m68krcycles_done;
483 if (!(ssh2.state & SH2_IDLE_STATES)) {
484 if (CYCLES_GT(now, ssh2.m68krcycles_done))
485 now = ssh2.m68krcycles_done;
489 p32x_timers_do(now - timer_cycles);
494 if (msh2.state & SH2_IDLE_STATES) {
495 if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
496 msh2.m68krcycles_done = m68k_target;
498 if (ssh2.state & SH2_IDLE_STATES) {
499 if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
500 ssh2.m68krcycles_done = m68k_target;
506 void sync_sh2s_lockstep(unsigned int m68k_target)
508 unsigned int mcycles;
510 mcycles = msh2.m68krcycles_done;
511 if (ssh2.m68krcycles_done < mcycles)
512 mcycles = ssh2.m68krcycles_done;
514 while (mcycles < m68k_target) {
516 sync_sh2s_normal(mcycles);
520 #define CPUS_RUN(m68k_cycles) do { \
521 if (PicoAHW & PAHW_MCD) \
522 pcd_run_cpus(m68k_cycles); \
524 SekRunM68k(m68k_cycles); \
526 if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
527 && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
528 PicoSyncZ80(SekCyclesDone()); \
529 if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
530 p32x_sync_sh2s(SekCyclesDone()); \
535 #include "../pico_cmn.c"
537 void PicoFrame32x(void)
541 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
542 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
543 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
545 if (!(Pico32x.sh2_regs[0] & 0x80))
546 p32x_schedule_hint(NULL, SekCyclesDone());
547 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
548 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
550 if (PicoAHW & PAHW_MCD)
557 elprintf(EL_32X, "poll: %02x %02x %02x",
558 Pico32x.emu_flags & 3, msh2.state, ssh2.state);
561 // calculate multipliers against 68k clock (7670442)
562 // normally * 3, but effectively slower due to high latencies everywhere
563 // however using something lower breaks MK2 animations
564 void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
566 float m68k_clk = (float)(OSC_NTSC / 7);
568 msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
569 msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
572 ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
573 ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
577 void Pico32xStateLoaded(int is_early)
580 Pico32xMemStateLoaded();
584 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
585 p32x_update_irls(NULL, SekCyclesDone());
586 p32x_pwm_state_loaded();
587 p32x_run_events(SekCyclesDone());
590 // vim:shiftwidth=2:ts=2:expandtab