3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 #include "../pico_int.h"
9 #include "../sound/ym2612.h"
10 #include "../../cpu/sh2/compiler.h"
12 struct Pico32x Pico32x;
15 #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
17 static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
19 if (sh2->pending_irl > sh2->pending_int_irq) {
20 elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
21 sh2->is_slave ? 's' : 'm', level, sh2->pc);
22 return 64 + sh2->pending_irl / 2;
24 elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
25 sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
26 sh2->pending_int_irq = 0; // auto-clear
27 sh2->pending_level = sh2->pending_irl;
28 return sh2->pending_int_vector;
32 // if !nested_call, must sync CPUs before calling this
33 void p32x_update_irls(SH2 *active_sh2)
35 int irqs, mlvl = 0, slvl = 0;
39 if (active_sh2 != NULL)
40 m68k_cycles = sh2_cycles_done_m68k(active_sh2);
43 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
49 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
54 mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 != NULL);
56 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
58 srun = sh2_irl_irq(&ssh2, slvl, active_sh2 != NULL);
60 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
62 elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
65 void Pico32xStartup(void)
67 elprintf(EL_STATUS|EL_32X, "32X startup");
72 msh2.irq_callback = sh2_irq_cb;
74 ssh2.irq_callback = sh2_irq_cb;
80 Pico32x.vdp_regs[0] |= P32XV_nPAL;
82 PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
83 PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
90 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
91 void p32x_reset_sh2s(void)
93 elprintf(EL_32X, "sh2 reset");
98 // if we don't have BIOS set, perform it's work here.
100 if (p32x_bios_m == NULL) {
101 unsigned int idl_src, idl_dst, idl_size; // initial data load
105 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
106 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
107 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
108 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
109 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
110 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
111 idl_src, idl_dst, idl_size);
114 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
117 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
118 sh2_set_gbr(0, 0x20004000);
122 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
123 // program will set M_OK
127 if (p32x_bios_s == NULL) {
131 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
132 sh2_set_gbr(1, 0x20004000);
134 // program will set S_OK
137 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
140 void Pico32xInit(void)
142 if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
143 Pico32xSetClocks(PICO_MSH2_HZ, 0);
144 if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
145 Pico32xSetClocks(0, PICO_MSH2_HZ);
148 void PicoPower32x(void)
150 memset(&Pico32x, 0, sizeof(Pico32x));
152 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
153 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
154 Pico32x.sh2_regs[0] = P32XS2_ADEN;
157 void PicoUnload32x(void)
159 if (Pico32xMem != NULL)
160 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
165 PicoAHW &= ~PAHW_32X;
168 void PicoReset32x(void)
170 if (PicoAHW & PAHW_32X) {
171 Pico32x.sh2irqs |= P32XI_VRES;
172 p32x_update_irls(NULL);
173 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
174 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
175 p32x_timers_recalc();
179 static void p32x_start_blank(void)
181 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
186 offs = 8; lines = 224;
187 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
192 // XXX: no proper handling of 32col mode..
193 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
194 (Pico.video.reg[12] & 1) && // 40col mode
195 (PicoDrawMask & PDRAW_32X_ON))
197 int md_bg = Pico.video.reg[7] & 0x3f;
199 // we draw full layer (not line-by-line)
200 PicoDraw32xLayer(offs, lines, md_bg);
202 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
203 PicoDraw32xLayerMdOnly(offs, lines);
209 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
211 // FB swap waits until vblank
212 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
213 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
214 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
215 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
218 Pico32x.sh2irqs |= P32XI_VINT;
219 p32x_update_irls(NULL);
220 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
221 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
224 // compare cycles, handling overflows
226 #define CYCLES_GT(a, b) \
227 ((int)((a) - (b)) > 0)
229 #define CYCLES_GE(a, b) \
230 ((int)((a) - (b)) >= 0)
233 static void pwm_irq_event(unsigned int now)
235 Pico32x.emu_flags &= ~P32XF_PWM_PEND;
236 p32x_pwm_schedule(now);
238 Pico32x.sh2irqs |= P32XI_PWM;
239 p32x_update_irls(NULL);
242 static void fillend_event(unsigned int now)
244 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
245 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
246 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
249 typedef void (event_cb)(unsigned int now);
251 unsigned int event_times[P32X_EVENT_COUNT];
252 static unsigned int event_time_next;
253 static event_cb *event_cbs[] = {
254 [P32X_EVENT_PWM] = pwm_irq_event,
255 [P32X_EVENT_FILLEND] = fillend_event,
258 // schedule event at some time 'after', in m68k clocks
259 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
263 when = (now + after) | 1;
265 elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
266 event_times[event] = when;
268 if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
269 event_time_next = when;
272 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
274 unsigned int now = sh2_cycles_done_m68k(sh2);
277 p32x_event_schedule(now, event, after);
279 left_to_next = (event_time_next - now) * 3;
280 if (sh2_cycles_left(sh2) > left_to_next)
281 sh2_end_run(sh2, left_to_next);
284 static void run_events(unsigned int until)
286 int oldest, oldest_diff, time;
290 oldest = -1, oldest_diff = 0x7fffffff;
292 for (i = 0; i < P32X_EVENT_COUNT; i++) {
293 if (event_times[i]) {
294 diff = event_times[i] - until;
295 if (diff < oldest_diff) {
302 if (oldest_diff <= 0) {
303 time = event_times[oldest];
304 event_times[oldest] = 0;
305 elprintf(EL_32X, "run event #%d %u", oldest, time);
306 event_cbs[oldest](time);
308 else if (oldest_diff < 0x7fffffff) {
309 event_time_next = event_times[oldest];
319 elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
322 static inline void run_sh2(SH2 *sh2, int m68k_cycles)
326 pevt_log_sh2_o(sh2, EVT_RUN_START);
327 sh2->state |= SH2_STATE_RUN;
328 cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
329 elprintf(EL_32X, "%csh2 +run %u %d",
330 sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles);
332 done = sh2_execute(sh2, cycles);
334 sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
335 sh2->state &= ~SH2_STATE_RUN;
336 pevt_log_sh2_o(sh2, EVT_RUN_END);
337 elprintf(EL_32X, "%csh2 -run %u %d",
338 sh2->is_slave?'s':'m', sh2->m68krcycles_done, done);
341 // sync other sh2 to this one
342 // note: recursive call
343 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
345 SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
349 if (osh2->state & SH2_STATE_RUN)
352 m68k_cycles = m68k_target - osh2->m68krcycles_done;
353 if (m68k_cycles < 200)
356 if (osh2->state & SH2_IDLE_STATES) {
357 osh2->m68krcycles_done = m68k_target;
361 elprintf(EL_32X, "%csh2 sync to %u %d",
362 osh2->is_slave?'s':'m', m68k_target, m68k_cycles);
364 run_sh2(osh2, m68k_cycles);
366 // there might be new event to schedule current sh2 to
367 if (event_time_next) {
368 left_to_event = event_time_next - m68k_target;
370 if (sh2_cycles_left(sh2) > left_to_event) {
371 if (left_to_event < 1)
373 sh2_end_run(sh2, left_to_event);
378 #define sync_sh2s_normal p32x_sync_sh2s
379 //#define sync_sh2s_lockstep p32x_sync_sh2s
381 /* most timing is in 68k clock */
382 void sync_sh2s_normal(unsigned int m68k_target)
384 unsigned int now, target, timer_cycles;
387 elprintf(EL_32X, "sh2 sync to %u", m68k_target);
389 if (!(Pico32x.regs[0] & P32XS_nRES)) {
390 msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
394 now = msh2.m68krcycles_done;
395 if (CYCLES_GT(now, ssh2.m68krcycles_done))
396 now = ssh2.m68krcycles_done;
399 while (CYCLES_GT(m68k_target, now))
401 if (event_time_next && CYCLES_GE(now, event_time_next))
404 target = m68k_target;
405 if (event_time_next && CYCLES_GT(target, event_time_next))
406 target = event_time_next;
408 while (CYCLES_GT(target, now))
410 elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
411 target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
412 m68k_target - now, Pico32x.emu_flags);
414 if (!(ssh2.state & SH2_IDLE_STATES)) {
415 cycles = target - ssh2.m68krcycles_done;
417 run_sh2(&ssh2, cycles);
419 if (event_time_next && CYCLES_GT(target, event_time_next))
420 target = event_time_next;
424 if (!(msh2.state & SH2_IDLE_STATES)) {
425 cycles = target - msh2.m68krcycles_done;
427 run_sh2(&msh2, cycles);
429 if (event_time_next && CYCLES_GT(target, event_time_next))
430 target = event_time_next;
435 if (!(msh2.state & SH2_IDLE_STATES)) {
436 if (CYCLES_GT(now, msh2.m68krcycles_done))
437 now = msh2.m68krcycles_done;
439 if (!(ssh2.state & SH2_IDLE_STATES)) {
440 if (CYCLES_GT(now, ssh2.m68krcycles_done))
441 now = ssh2.m68krcycles_done;
445 p32x_timers_do(now - timer_cycles);
450 if (msh2.state & SH2_IDLE_STATES) {
451 if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
452 msh2.m68krcycles_done = m68k_target;
454 if (ssh2.state & SH2_IDLE_STATES) {
455 if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
456 ssh2.m68krcycles_done = m68k_target;
462 void sync_sh2s_lockstep(unsigned int m68k_target)
464 unsigned int mcycles;
466 mcycles = msh2.m68krcycles_done;
467 if (ssh2.m68krcycles_done < mcycles)
468 mcycles = ssh2.m68krcycles_done;
470 while (mcycles < m68k_target) {
472 sync_sh2s_normal(mcycles);
476 #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
477 SekRunM68k(m68k_cycles); \
478 if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
479 p32x_sync_sh2s(SekCyclesDoneT2()); \
483 #include "../pico_cmn.c"
485 void PicoFrame32x(void)
487 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
488 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
489 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
491 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
492 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
498 elprintf(EL_32X, "poll: %02x %02x %02x",
499 Pico32x.emu_flags & 3, msh2.state, ssh2.state);
502 // calculate multipliers against 68k clock (7670442)
503 // normally * 3, but effectively slower due to high latencies everywhere
504 // however using something lower breaks MK2 animations
505 void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
507 float m68k_clk = (float)(OSC_NTSC / 7);
509 msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
510 msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
513 ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
514 ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
518 void Pico32xStateLoaded(int is_early)
521 Pico32xMemStateLoaded();
526 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
527 p32x_update_irls(NULL);
528 p32x_timers_recalc();
529 run_events(SekCycleCntT);
532 // vim:shiftwidth=2:ts=2:expandtab