3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 #include "../pico_int.h"
9 #include "../sound/ym2612.h"
10 #include "../../cpu/sh2/compiler.h"
12 struct Pico32x Pico32x;
15 #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP)
17 static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
19 if (sh2->pending_irl > sh2->pending_int_irq) {
20 elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
22 return 64 + sh2->pending_irl / 2;
24 elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
25 level, sh2->pending_int_vector, sh2_pc(sh2));
26 sh2->pending_int_irq = 0; // auto-clear
27 sh2->pending_level = sh2->pending_irl;
28 return sh2->pending_int_vector;
32 // MUST specify active_sh2 when called from sh2 memhandlers
33 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
35 int irqs, mlvl = 0, slvl = 0;
38 if (active_sh2 != NULL)
39 m68k_cycles = sh2_cycles_done_m68k(active_sh2);
42 irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
48 irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
53 mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
55 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
56 if (active_sh2 == &msh2)
57 sh2_end_run(active_sh2, 1);
60 srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
62 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
63 if (active_sh2 == &ssh2)
64 sh2_end_run(active_sh2, 1);
67 elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
70 // the mask register is inconsistent, CMD is supposed to be a mask,
71 // while others are actually irq trigger enables?
73 void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
75 Pico32x.sh2irqs |= mask & P32XI_VRES;
76 Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
77 Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
79 p32x_update_irls(sh2, m68k_cycles);
82 void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
84 if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
85 Pico32x.sh2irqi[0] |= P32XI_CMD;
87 Pico32x.sh2irqi[0] &= ~P32XI_CMD;
89 if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
90 Pico32x.sh2irqi[1] |= P32XI_CMD;
92 Pico32x.sh2irqi[1] &= ~P32XI_CMD;
94 p32x_update_irls(sh2, m68k_cycles);
97 void Pico32xStartup(void)
99 elprintf(EL_STATUS|EL_32X, "32X startup");
101 // TODO: OOM handling
103 sh2_init(&msh2, 0, &ssh2);
104 msh2.irq_callback = sh2_irq_cb;
105 sh2_init(&ssh2, 1, &msh2);
106 ssh2.irq_callback = sh2_irq_cb;
109 p32x_pwm_ctl_changed();
110 p32x_timers_recalc();
112 Pico32x.sh2_regs[0] = P32XS2_ADEN;
114 Pico32x.sh2_regs[0] |= P32XS_nCART;
117 Pico32x.vdp_regs[0] |= P32XV_nPAL;
124 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
125 void p32x_reset_sh2s(void)
127 elprintf(EL_32X, "sh2 reset");
131 sh2_peripheral_reset(&msh2);
132 sh2_peripheral_reset(&ssh2);
134 // if we don't have BIOS set, perform it's work here.
136 if (p32x_bios_m == NULL) {
137 sh2_set_gbr(0, 0x20004000);
139 if (!(PicoAHW & PAHW_MCD)) {
140 unsigned int idl_src, idl_dst, idl_size; // initial data load
144 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
145 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
146 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
147 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
148 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
149 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
150 idl_src, idl_dst, idl_size);
153 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
156 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
160 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
162 // program will set M_OK
166 if (p32x_bios_s == NULL) {
170 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
171 sh2_set_gbr(1, 0x20004000);
173 // program will set S_OK
176 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
179 void Pico32xInit(void)
181 if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
182 Pico32xSetClocks(PICO_MSH2_HZ, 0);
183 if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
184 Pico32xSetClocks(0, PICO_MSH2_HZ);
187 void PicoPower32x(void)
189 memset(&Pico32x, 0, sizeof(Pico32x));
191 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
192 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
195 void PicoUnload32x(void)
197 if (Pico32xMem != NULL)
198 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
203 PicoAHW &= ~PAHW_32X;
206 void PicoReset32x(void)
208 if (PicoAHW & PAHW_32X) {
209 p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
210 p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
211 p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
212 p32x_pwm_ctl_changed();
213 p32x_timers_recalc();
217 static void p32x_start_blank(void)
219 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
224 offs = 8; lines = 224;
225 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
230 // XXX: no proper handling of 32col mode..
231 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
232 (Pico.video.reg[12] & 1) && // 40col mode
233 (PicoDrawMask & PDRAW_32X_ON))
235 int md_bg = Pico.video.reg[7] & 0x3f;
237 // we draw full layer (not line-by-line)
238 PicoDraw32xLayer(offs, lines, md_bg);
240 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
241 PicoDraw32xLayerMdOnly(offs, lines);
247 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
249 // FB swap waits until vblank
250 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
251 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
252 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
253 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
256 p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
257 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
258 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
261 void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
263 // rather rough, 32x hint is useless in practice
266 if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
267 return; // nobody cares
268 // note: when Pico.m.scanline is 224, SH2s might
269 // still be at scanline 93 (or so)
270 if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
273 after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
275 p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
277 p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
281 static void fillend_event(unsigned int now)
283 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
284 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now);
285 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
288 static void hint_event(unsigned int now)
290 p32x_trigger_irq(NULL, now, P32XI_HINT);
291 p32x_schedule_hint(NULL, now);
294 typedef void (event_cb)(unsigned int now);
296 /* times are in m68k (7.6MHz) cycles */
297 unsigned int p32x_event_times[P32X_EVENT_COUNT];
298 static unsigned int event_time_next;
299 static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
300 [P32X_EVENT_PWM] = p32x_pwm_irq_event,
301 [P32X_EVENT_FILLEND] = fillend_event,
302 [P32X_EVENT_HINT] = hint_event,
305 // schedule event at some time 'after', in m68k clocks
306 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
310 when = (now + after) | 1;
312 elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
313 p32x_event_times[event] = when;
315 if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
316 event_time_next = when;
319 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
321 unsigned int now = sh2_cycles_done_m68k(sh2);
324 p32x_event_schedule(now, event, after);
326 left_to_next = (event_time_next - now) * 3;
327 sh2_end_run(sh2, left_to_next);
330 static void p32x_run_events(unsigned int until)
332 int oldest, oldest_diff, time;
336 oldest = -1, oldest_diff = 0x7fffffff;
338 for (i = 0; i < P32X_EVENT_COUNT; i++) {
339 if (p32x_event_times[i]) {
340 diff = p32x_event_times[i] - until;
341 if (diff < oldest_diff) {
348 if (oldest_diff <= 0) {
349 time = p32x_event_times[oldest];
350 p32x_event_times[oldest] = 0;
351 elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
352 p32x_event_cbs[oldest](time);
354 else if (oldest_diff < 0x7fffffff) {
355 event_time_next = p32x_event_times[oldest];
365 elprintf(EL_32X, "32x: next event #%d at %u",
366 oldest, event_time_next);
369 static inline void run_sh2(SH2 *sh2, int m68k_cycles)
373 pevt_log_sh2_o(sh2, EVT_RUN_START);
374 sh2->state |= SH2_STATE_RUN;
375 cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
376 elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
377 sh2->m68krcycles_done, cycles, sh2->pc);
379 done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC);
381 sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
382 sh2->state &= ~SH2_STATE_RUN;
383 pevt_log_sh2_o(sh2, EVT_RUN_END);
384 elprintf_sh2(sh2, EL_32X, "-run %u %d",
385 sh2->m68krcycles_done, done);
388 // sync other sh2 to this one
389 // note: recursive call
390 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
392 SH2 *osh2 = sh2->other_sh2;
396 if (osh2->state & SH2_STATE_RUN)
399 m68k_cycles = m68k_target - osh2->m68krcycles_done;
400 if (m68k_cycles < 200)
403 if (osh2->state & SH2_IDLE_STATES) {
404 osh2->m68krcycles_done = m68k_target;
408 elprintf_sh2(osh2, EL_32X, "sync to %u %d",
409 m68k_target, m68k_cycles);
411 run_sh2(osh2, m68k_cycles);
413 // there might be new event to schedule current sh2 to
414 if (event_time_next) {
415 left_to_event = event_time_next - m68k_target;
417 if (sh2_cycles_left(sh2) > left_to_event) {
418 if (left_to_event < 1)
420 sh2_end_run(sh2, left_to_event);
425 #define sync_sh2s_normal p32x_sync_sh2s
426 //#define sync_sh2s_lockstep p32x_sync_sh2s
428 /* most timing is in 68k clock */
429 void sync_sh2s_normal(unsigned int m68k_target)
431 unsigned int now, target, timer_cycles;
434 elprintf(EL_32X, "sh2 sync to %u", m68k_target);
436 if (!(Pico32x.regs[0] & P32XS_nRES)) {
437 msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
441 now = msh2.m68krcycles_done;
442 if (CYCLES_GT(now, ssh2.m68krcycles_done))
443 now = ssh2.m68krcycles_done;
446 while (CYCLES_GT(m68k_target, now))
448 if (event_time_next && CYCLES_GE(now, event_time_next))
449 p32x_run_events(now);
451 target = m68k_target;
452 if (event_time_next && CYCLES_GT(target, event_time_next))
453 target = event_time_next;
455 while (CYCLES_GT(target, now))
457 elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
458 target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
459 m68k_target - now, Pico32x.emu_flags);
461 if (!(ssh2.state & SH2_IDLE_STATES)) {
462 cycles = target - ssh2.m68krcycles_done;
464 run_sh2(&ssh2, cycles);
466 if (event_time_next && CYCLES_GT(target, event_time_next))
467 target = event_time_next;
471 if (!(msh2.state & SH2_IDLE_STATES)) {
472 cycles = target - msh2.m68krcycles_done;
474 run_sh2(&msh2, cycles);
476 if (event_time_next && CYCLES_GT(target, event_time_next))
477 target = event_time_next;
482 if (!(msh2.state & SH2_IDLE_STATES)) {
483 if (CYCLES_GT(now, msh2.m68krcycles_done))
484 now = msh2.m68krcycles_done;
486 if (!(ssh2.state & SH2_IDLE_STATES)) {
487 if (CYCLES_GT(now, ssh2.m68krcycles_done))
488 now = ssh2.m68krcycles_done;
492 p32x_timers_do(now - timer_cycles);
497 if (msh2.state & SH2_IDLE_STATES) {
498 if (CYCLES_GT(m68k_target, msh2.m68krcycles_done))
499 msh2.m68krcycles_done = m68k_target;
501 if (ssh2.state & SH2_IDLE_STATES) {
502 if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done))
503 ssh2.m68krcycles_done = m68k_target;
509 void sync_sh2s_lockstep(unsigned int m68k_target)
511 unsigned int mcycles;
513 mcycles = msh2.m68krcycles_done;
514 if (ssh2.m68krcycles_done < mcycles)
515 mcycles = ssh2.m68krcycles_done;
517 while (mcycles < m68k_target) {
519 sync_sh2s_normal(mcycles);
523 #define CPUS_RUN(m68k_cycles) do { \
524 if (PicoAHW & PAHW_MCD) \
525 pcd_run_cpus(m68k_cycles); \
527 SekRunM68k(m68k_cycles); \
529 if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
530 && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
531 PicoSyncZ80(SekCyclesDone()); \
532 if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
533 p32x_sync_sh2s(SekCyclesDone()); \
538 #include "../pico_cmn.c"
540 void PicoFrame32x(void)
544 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
545 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
546 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
548 if (!(Pico32x.sh2_regs[0] & 0x80))
549 p32x_schedule_hint(NULL, SekCyclesDone());
550 p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
551 p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
553 if (PicoAHW & PAHW_MCD)
560 elprintf(EL_32X, "poll: %02x %02x %02x",
561 Pico32x.emu_flags & 3, msh2.state, ssh2.state);
564 // calculate multipliers against 68k clock (7670442)
565 // normally * 3, but effectively slower due to high latencies everywhere
566 // however using something lower breaks MK2 animations
567 void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
569 float m68k_clk = (float)(OSC_NTSC / 7);
571 msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
572 msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
575 ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
576 ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
580 void Pico32xStateLoaded(int is_early)
583 Pico32xMemStateLoaded();
587 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
588 p32x_update_irls(NULL, SekCyclesDone());
589 p32x_pwm_state_loaded();
590 p32x_run_events(SekCyclesDone());
593 // vim:shiftwidth=2:ts=2:expandtab