3 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
4 * a15102 ........ ......SM ? 4002 // intS intM
5 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
6 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
7 * a15108 (32bit DREQ src) 4008
8 * a1510c (32bit DREQ dst) 400c
9 * a15110 llllllll llllll00 4010 // DREQ Len
10 * a15112 (16bit FIFO reg) 4012
11 * a15114 ? (16bit VRES clr) 4014
12 * a15116 ? (16bit Vint clr) 4016
13 * a15118 ? (16bit Hint clr) 4018
14 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
15 * a1511c ? (16bit PWM clr) 401c
17 * a15120 (16 bytes comm) 2020
20 #include "../pico_int.h"
21 #include "../memory.h"
26 #define ash2_end_run(x)
30 static const char str_mars[] = "MARS";
32 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
33 struct Pico32xMem *Pico32xMem;
35 static void bank_switch(int b);
38 #define POLL_THRESHOLD 6
41 u32 addr, cycles, cyc_max;
44 static struct poll_det m68k_poll, sh2_poll[2];
46 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
48 int ret = 0, flag = pd->flag;
53 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
55 if (pd->cnt > POLL_THRESHOLD) {
56 if (!(Pico32x.emu_flags & flag)) {
57 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
58 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
59 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
62 Pico32x.emu_flags |= flag;
74 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
76 int ret = 0, flag = pd->flag;
78 flag <<= 3; // VDP only
80 flag |= flag << 3; // both
81 if (Pico32x.emu_flags & flag) {
82 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
85 Pico32x.emu_flags &= ~flag;
86 pd->addr = pd->cnt = 0;
90 void p32x_poll_event(int cpu_mask, int is_vdp)
93 p32x_poll_undetect(&sh2_poll[0], is_vdp);
95 p32x_poll_undetect(&sh2_poll[1], is_vdp);
102 static const u16 comm_fakevals[] = {
103 0x4d5f, 0x4f4b, // M_OK
104 0x535f, 0x4f4b, // S_OK
105 0x4D41, 0x5346, // MASF - Brutal Unleashed
106 0x5331, 0x4d31, // Darxide
109 0x0000, 0x0000, // eq for doom
110 0x0002, // Mortal Kombat
114 static u32 sh2_comm_faker(u32 a)
117 if (a == 0x28 && !p32x_csum_faked) {
119 return *(unsigned short *)(Pico.rom + 0x18e);
121 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
123 return comm_fakevals[f++];
129 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
130 unsigned int chcr0; // chan ctl
131 unsigned int sar1, dar1, tcr1; // same for chan 1
137 static void dma_68k2sh2_do(void)
139 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
142 if (dmac0->tcr0 != *dreqlen)
143 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
145 // HACK: assume bus is busy and SH2 is halted
146 // XXX: use different mechanism for this, not poll det
147 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
149 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
150 extern void p32x_sh2_write16(u32 a, u32 d, int id);
151 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
152 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0);
158 Pico32x.dmac_ptr = 0; // HACK
159 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
161 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
162 if (dmac0->tcr0 == 0) {
163 dmac0->chcr0 |= 2; // DMA has ended normally
164 p32x_poll_undetect(&sh2_poll[0], 0);
168 // ------------------------------------------------------------------
171 static u32 p32x_reg_read16(u32 a)
175 if (a == 2) // INTM, INTS
176 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
178 if ((a & 0x30) == 0x20)
179 return sh2_comm_faker(a);
181 if ((a & 0x30) == 0x20) {
182 // evil X-Men proto polls in a dbra loop and expects it to expire..
184 if (SekDar(2) != dr2)
188 if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
196 if ((a & 0x30) == 0x30)
197 return p32x_pwm_read16(a);
199 return Pico32x.regs[a / 2];
202 static void p32x_reg_write8(u32 a, u32 d)
204 u16 *r = Pico32x.regs;
207 // for things like bset on comm port
211 case 0: // adapter ctl
212 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
214 case 1: // adapter ctl, RES bit writeable
215 if ((d ^ r[0]) & d & P32XS_nRES)
217 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
220 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
221 Pico32x.sh2irqi[0] |= P32XI_CMD;
225 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
226 Pico32x.sh2irqi[1] |= P32XI_CMD;
239 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
246 if ((a & 0x30) == 0x20) {
249 p32x_poll_undetect(&sh2_poll[0], 0);
250 p32x_poll_undetect(&sh2_poll[1], 0);
251 // if some SH2 is busy waiting, it needs to see the result ASAP
252 if (SekCyclesLeftNoMCD > 32)
258 static void p32x_reg_write16(u32 a, u32 d)
260 u16 *r = Pico32x.regs;
263 // for things like bset on comm port
267 case 0x00: // adapter ctl
268 if ((d ^ r[0]) & d & P32XS_nRES)
270 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
272 case 0x10: // DREQ len
275 case 0x12: // FIFO reg
276 if (!(r[6 / 2] & P32XS_68S)) {
277 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
280 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
281 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
282 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
284 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
285 r[6 / 2] |= P32XS_FULL;
291 if ((a & 0x38) == 0x08) {
296 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
298 p32x_poll_undetect(&sh2_poll[0], 0);
299 p32x_poll_undetect(&sh2_poll[1], 0);
301 if (SekCyclesLeftNoMCD > 32)
306 else if ((a & 0x30) == 0x30) {
307 p32x_pwm_write16(a, d);
311 p32x_reg_write8(a + 1, d);
314 // ------------------------------------------------------------------
316 static u32 p32x_vdp_read16(u32 a)
320 return Pico32x.vdp_regs[a / 2];
323 static void p32x_vdp_write8(u32 a, u32 d)
325 u16 *r = Pico32x.vdp_regs;
328 // for FEN checks between writes
331 // TODO: verify what's writeable
334 // priority inversion is handled in palette
335 if ((r[0] ^ d) & P32XV_PRI)
336 Pico32x.dirty_pal = 1;
337 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
339 case 0x05: // fill len
344 Pico32x.pending_fb = d;
345 // if we are blanking and FS bit is changing
346 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
348 Pico32xSwapDRAM(d ^ 1);
349 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
355 static void p32x_vdp_write16(u32 a, u32 d)
358 if (a == 6) { // fill start
359 Pico32x.vdp_regs[6 / 2] = d;
362 if (a == 8) { // fill data
363 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
364 int len = Pico32x.vdp_regs[4 / 2] + 1;
365 a = Pico32x.vdp_regs[6 / 2];
368 a = (a & 0xff00) | ((a + 1) & 0xff);
370 Pico32x.vdp_regs[6 / 2] = a;
371 Pico32x.vdp_regs[8 / 2] = d;
375 p32x_vdp_write8(a | 1, d);
378 // ------------------------------------------------------------------
381 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
383 u16 *r = Pico32x.regs;
387 case 0x00: // adapter/irq ctl
388 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
389 case 0x04: // H count (often as comm too)
390 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
392 return Pico32x.sh2_regs[4 / 2];
393 case 0x10: // DREQ len
398 if ((a & 0x38) == 0x08)
401 if ((a & 0x30) == 0x20) {
402 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
406 if ((a & 0x30) == 0x30) {
407 sh2_poll[cpuid].cnt = 0;
408 return p32x_pwm_read16(a);
414 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
419 Pico32x.regs[0] &= ~P32XS_FM;
420 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
423 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
424 Pico32x.sh2_regs[0] &= ~0x80;
425 Pico32x.sh2_regs[0] |= d & 0x80;
429 Pico32x.sh2_regs[4 / 2] = d & 0xff;
430 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
434 if ((a & 0x30) == 0x20) {
435 u8 *r8 = (u8 *)Pico32x.regs;
437 if (p32x_poll_undetect(&m68k_poll, 0))
439 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
444 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
449 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
450 Pico32x.regs[a / 2] = d;
451 if (p32x_poll_undetect(&m68k_poll, 0))
453 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
457 else if ((a & 0x30) == 0x30) {
458 p32x_pwm_write16(a, d);
464 Pico32x.regs[0] &= ~P32XS_FM;
465 Pico32x.regs[0] |= d & P32XS_FM;
467 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
468 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
469 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
470 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
472 Pico32x.sh2irqs &= ~P32XI_PWM;
477 p32x_sh2reg_write8(a | 1, d, cpuid);
484 // ------------------------------------------------------------------
485 // SH2 internal peripherals
486 // we keep them in little endian format
487 static u32 sh2_peripheral_read8(u32 a, int id)
489 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
495 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
499 static u32 sh2_peripheral_read16(u32 a, int id)
501 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
507 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
511 static u32 sh2_peripheral_read32(u32 a, int id)
515 d = Pico32xMem->sh2_peri_regs[id][a / 4];
517 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
521 static void sh2_peripheral_write8(u32 a, u32 d, int id)
523 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
524 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
530 if ((a == 2 && (d & 0x20)) || // transmiter enabled
531 (a == 4 && !(d & 0x80))) { // valid data in TDR
532 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
533 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
534 int level = PREG8(oregs, 0x60) >> 4;
535 int vector = PREG8(oregs, 0x63) & 0x7f;
536 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
537 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
542 static void sh2_peripheral_write16(u32 a, u32 d, int id)
544 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
545 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
551 if ((d & 0xff00) == 0xa500) { // WTCSR
553 p32x_timers_recalc();
555 if ((d & 0xff00) == 0x5a00) // WTCNT
563 static void sh2_peripheral_write32(u32 a, u32 d, int id)
565 u32 *r = Pico32xMem->sh2_peri_regs[id];
566 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
572 // division unit (TODO: verify):
573 case 0x104: // DVDNT: divident L, starts divide
574 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
576 signed int divisor = r[0x100 / 4];
577 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
578 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
581 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
584 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
585 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
587 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
588 signed int divisor = r[0x100 / 4];
589 // XXX: undocumented mirroring to 0x118,0x11c?
590 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
592 r[0x11c / 4] = r[0x114 / 4] = divident;
594 if ((unsigned long long)divident + 1 > 1) {
595 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
596 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
600 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
604 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
605 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
606 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
607 dmac0->tcr0 &= 0xffffff;
609 // HACK: assume 68k starts writing soon and end the timeslice
612 // DREQ is only sent after first 4 words are written.
613 // we do multiple of 4 words to avoid messing up alignment
614 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
615 elprintf(EL_32X, "68k -> sh2 DMA");
621 // ------------------------------------------------------------------
625 static u32 PicoRead8_32x_on(u32 a)
628 if ((a & 0xffc0) == 0x5100) { // a15100
629 d = p32x_reg_read16(a);
633 if ((a & 0xfc00) != 0x5000)
634 return PicoRead8_io(a);
636 if ((a & 0xfff0) == 0x5180) { // a15180
637 d = p32x_vdp_read16(a);
641 if ((a & 0xfe00) == 0x5200) { // a15200
642 d = Pico32xMem->pal[(a & 0x1ff) / 2];
646 if ((a & 0xfffc) == 0x30ec) { // a130ec
651 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
661 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
665 static u32 PicoRead16_32x_on(u32 a)
668 if ((a & 0xffc0) == 0x5100) { // a15100
669 d = p32x_reg_read16(a);
673 if ((a & 0xfc00) != 0x5000)
674 return PicoRead16_io(a);
676 if ((a & 0xfff0) == 0x5180) { // a15180
677 d = p32x_vdp_read16(a);
681 if ((a & 0xfe00) == 0x5200) { // a15200
682 d = Pico32xMem->pal[(a & 0x1ff) / 2];
686 if ((a & 0xfffc) == 0x30ec) { // a130ec
687 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
691 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
695 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
699 static void PicoWrite8_32x_on(u32 a, u32 d)
701 if ((a & 0xfc00) == 0x5000)
702 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
704 if ((a & 0xffc0) == 0x5100) { // a15100
705 p32x_reg_write8(a, d);
709 if ((a & 0xfc00) != 0x5000) {
714 if ((a & 0xfff0) == 0x5180) { // a15180
715 p32x_vdp_write8(a, d);
720 if ((a & 0xfe00) == 0x5200) { // a15200
721 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
722 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
723 Pico32x.dirty_pal = 1;
727 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
730 static void PicoWrite16_32x_on(u32 a, u32 d)
732 if ((a & 0xfc00) == 0x5000)
733 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
735 if ((a & 0xffc0) == 0x5100) { // a15100
736 p32x_reg_write16(a, d);
740 if ((a & 0xfc00) != 0x5000) {
741 PicoWrite16_io(a, d);
745 if ((a & 0xfff0) == 0x5180) { // a15180
746 p32x_vdp_write16(a, d);
750 if ((a & 0xfe00) == 0x5200) { // a15200
751 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
752 Pico32x.dirty_pal = 1;
756 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
760 u32 PicoRead8_32x(u32 a)
763 if ((a & 0xffc0) == 0x5100) { // a15100
764 // regs are always readable
765 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
769 if ((a & 0xfffc) == 0x30ec) { // a130ec
774 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
778 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
782 u32 PicoRead16_32x(u32 a)
785 if ((a & 0xffc0) == 0x5100) { // a15100
786 d = Pico32x.regs[(a & 0x3f) / 2];
790 if ((a & 0xfffc) == 0x30ec) { // a130ec
791 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
795 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
799 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
803 void PicoWrite8_32x(u32 a, u32 d)
805 if ((a & 0xffc0) == 0x5100) { // a15100
806 u16 *r = Pico32x.regs;
808 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
811 if ((d ^ r[0]) & d & P32XS_ADEN) {
813 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
815 p32x_reg_write8(a, d); // forward for reset processing
820 // allow only COMM for now
821 if ((a & 0x30) == 0x20) {
828 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
831 void PicoWrite16_32x(u32 a, u32 d)
833 if ((a & 0xffc0) == 0x5100) { // a15100
834 u16 *r = Pico32x.regs;
836 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
839 if ((d ^ r[0]) & d & P32XS_ADEN) {
841 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
843 p32x_reg_write16(a, d); // forward for reset processing
848 // allow only COMM for now
849 if ((a & 0x30) == 0x20)
854 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
857 // -----------------------------------------------------------------
859 // hint vector is writeable
860 static void PicoWrite8_hint(u32 a, u32 d)
862 if ((a & 0xfffc) == 0x0070) {
863 Pico32xMem->m68k_rom[a ^ 1] = d;
867 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
870 static void PicoWrite16_hint(u32 a, u32 d)
872 if ((a & 0xfffc) == 0x0070) {
873 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
877 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
880 void Pico32xSwapDRAM(int b)
882 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
883 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
884 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
885 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
888 static void bank_switch(int b)
890 unsigned int rs, bank;
893 if (bank >= Pico.romsize) {
894 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
898 // 32X ROM (unbanked, XXX: consider mirroring?)
899 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
903 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
904 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
906 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
909 // setup FAME fetchmap
910 for (rs = 0x90; rs < 0xa0; rs++)
911 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
915 // -----------------------------------------------------------------
917 // -----------------------------------------------------------------
919 u32 p32x_sh2_read8(u32 a, int id)
923 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
924 return Pico32xMem->sh2_rom_m[a ^ 1];
925 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
926 return Pico32xMem->sh2_rom_s[a ^ 1];
928 if ((a & 0xdffc0000) == 0x06000000)
929 return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
931 if ((a & 0xdfc00000) == 0x02000000)
932 if ((a & 0x003fffff) < Pico.romsize)
933 return Pico.rom[(a & 0x3fffff) ^ 1];
935 if ((a & ~0xfff) == 0xc0000000)
936 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
938 if ((a & 0xdffc0000) == 0x04000000) {
939 /* XXX: overwrite readable as normal? */
940 u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
941 return dram[(a & 0x1ffff) ^ 1];
944 if ((a & 0xdfffff00) == 0x4000) {
945 d = p32x_sh2reg_read16(a, id);
949 if ((a & 0xdfffff00) == 0x4100) {
950 d = p32x_vdp_read16(a);
951 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
956 if ((a & 0xdfffff00) == 0x4200) {
957 d = Pico32xMem->pal[(a & 0x1ff) / 2];
961 if ((a & 0xfffffe00) == 0xfffffe00)
962 return sh2_peripheral_read8(a, id);
964 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
965 id ? 's' : 'm', a, d, sh2_pc(id));
974 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
975 id ? 's' : 'm', a, d, sh2_pc(id));
979 u32 p32x_sh2_read16(u32 a, int id)
983 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
984 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
985 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
986 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
988 if ((a & 0xdffc0000) == 0x06000000)
989 return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
991 if ((a & 0xdfc00000) == 0x02000000)
992 if ((a & 0x003fffff) < Pico.romsize)
993 return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
995 if ((a & ~0xfff) == 0xc0000000)
996 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
998 if ((a & 0xdffe0000) == 0x04000000)
999 return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
1001 if ((a & 0xdfffff00) == 0x4000) {
1002 d = p32x_sh2reg_read16(a, id);
1003 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1008 if ((a & 0xdfffff00) == 0x4100) {
1009 d = p32x_vdp_read16(a);
1010 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
1015 if ((a & 0xdfffff00) == 0x4200) {
1016 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1020 if ((a & 0xfffffe00) == 0xfffffe00)
1021 return sh2_peripheral_read16(a, id);
1023 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
1024 id ? 's' : 'm', a, d, sh2_pc(id));
1028 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1029 id ? 's' : 'm', a, d, sh2_pc(id));
1033 u32 p32x_sh2_read32(u32 a, int id)
1035 if ((a & 0xfffffe00) == 0xfffffe00)
1036 return sh2_peripheral_read32(a, id);
1038 // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
1039 return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
1042 void p32x_sh2_write8(u32 a, u32 d, int id)
1044 if ((a & 0xdffffc00) == 0x4000)
1045 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1046 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1048 if ((a & 0xdffc0000) == 0x06000000) {
1049 Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
1053 if ((a & 0xdffc0000) == 0x04000000) {
1055 if (!(a & 0x20000) || d) {
1056 dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
1057 dram[(a & 0x1ffff) ^ 1] = d;
1062 if ((a & ~0xfff) == 0xc0000000) {
1063 Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
1067 if ((a & 0xdfffff00) == 0x4100) {
1068 p32x_vdp_write8(a, d);
1072 if ((a & 0xdfffff00) == 0x4000) {
1073 p32x_sh2reg_write8(a, d, id);
1077 if ((a & 0xfffffe00) == 0xfffffe00) {
1078 sh2_peripheral_write8(a, d, id);
1082 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1083 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1086 void p32x_sh2_write16(u32 a, u32 d, int id)
1088 if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1089 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1090 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1092 // ignore "Associative purge space"
1093 if ((a & 0xf8000000) == 0x40000000)
1096 if ((a & 0xdffc0000) == 0x06000000) {
1097 ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
1101 if ((a & ~0xfff) == 0xc0000000) {
1102 ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
1106 if ((a & 0xdffc0000) == 0x04000000) {
1107 u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
1108 if (!(a & 0x20000)) {
1113 if (!(d & 0xff00)) d |= *pd & 0xff00;
1114 if (!(d & 0x00ff)) d |= *pd & 0x00ff;
1119 if ((a & 0xdfffff00) == 0x4100) {
1120 sh2_poll[id].cnt = 0; // for poll before VDP accesses
1121 p32x_vdp_write16(a, d);
1125 if ((a & 0xdffffe00) == 0x4200) {
1126 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1127 Pico32x.dirty_pal = 1;
1131 if ((a & 0xdfffff00) == 0x4000) {
1132 p32x_sh2reg_write16(a, d, id);
1136 if ((a & 0xfffffe00) == 0xfffffe00) {
1137 sh2_peripheral_write16(a, d, id);
1141 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1142 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1145 void p32x_sh2_write32(u32 a, u32 d, int id)
1147 if ((a & 0xfffffe00) == 0xfffffe00) {
1148 sh2_peripheral_write32(a, d, id);
1152 p32x_sh2_write16(a, d >> 16, id);
1153 p32x_sh2_write16(a + 2, d, id);
1156 static const u16 msh2_code[] = {
1157 // trap instructions
1158 0xaffe, // bra <self>
1160 // have to wait a bit until m68k initial program finishes clearing stuff
1161 // to avoid races with game SH2 code, like in Tempo
1162 0xd004, // mov.l @(_m_ok,pc), r0
1163 0xd105, // mov.l @(_cnt,pc), r1
1164 0xd205, // mov.l @(_start,pc), r2
1165 0x71ff, // add #-1, r1
1166 0x4115, // cmp/pl r1
1168 0xc208, // mov.l r0, @(h'20,gbr)
1169 0x6822, // mov.l @r2, r8
1172 ('M'<<8)|'_', ('O'<<8)|'K',
1174 0x2200, 0x03e0 // master start pointer in ROM
1177 static const u16 ssh2_code[] = {
1178 0xaffe, // bra <self>
1180 // code to wait for master, in case authentic master BIOS is used
1181 0xd104, // mov.l @(_m_ok,pc), r1
1182 0xd206, // mov.l @(_start,pc), r2
1183 0xc608, // mov.l @(h'20,gbr), r0
1184 0x3100, // cmp/eq r0, r1
1186 0xd003, // mov.l @(_s_ok,pc), r0
1187 0xc209, // mov.l r0, @(h'24,gbr)
1188 0x6822, // mov.l @r2, r8
1191 ('M'<<8)|'_', ('O'<<8)|'K',
1192 ('S'<<8)|'_', ('O'<<8)|'K',
1193 0x2200, 0x03e4 // slave start pointer in ROM
1196 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1197 static void get_bios(void)
1204 if (p32x_bios_g != NULL) {
1205 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1206 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
1210 ps = (u16 *)Pico32xMem->m68k_rom;
1212 for (i = 1; i < 0xc0/4; i++)
1213 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1216 for (i = 0xc0/2; i < 0x100/2; i++)
1220 ps[0xc0/2] = 0x46fc;
1221 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1222 ps[0xfe/2] = 0x60fe; // jump to self
1224 ps[0xfe/2] = 0x4e75; // rts
1227 // fill remaining m68k_rom page with game ROM
1228 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
1231 if (p32x_bios_m != NULL) {
1232 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1233 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1236 pl = (u32 *)Pico32xMem->sh2_rom_m;
1238 // fill exception vector table to our trap address
1239 for (i = 0; i < 128; i++)
1240 pl[i] = HWSWAP(0x200);
1243 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1246 pl[1] = pl[3] = HWSWAP(0x6040000);
1248 pl[0] = pl[2] = HWSWAP(0x204);
1252 if (p32x_bios_s != NULL) {
1253 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1254 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1257 pl = (u32 *)Pico32xMem->sh2_rom_s;
1259 // fill exception vector table to our trap address
1260 for (i = 0; i < 128; i++)
1261 pl[i] = HWSWAP(0x200);
1264 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1267 pl[1] = pl[3] = HWSWAP(0x603f800);
1269 pl[0] = pl[2] = HWSWAP(0x204);
1273 void PicoMemSetup32x(void)
1277 Pico32xMem = calloc(1, sizeof(*Pico32xMem));
1278 if (Pico32xMem == NULL) {
1279 elprintf(EL_STATUS, "OOM");
1283 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1287 // cartridge area becomes unmapped
1288 // XXX: we take the easy way and don't unmap ROM,
1289 // so that we can avoid handling the RV bit.
1290 // m68k_map_unmap(0x000000, 0x3fffff);
1293 rs = sizeof(Pico32xMem->m68k_rom);
1294 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1295 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1296 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1297 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1302 // 32X ROM (unbanked, XXX: consider mirroring?)
1303 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1306 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1307 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1309 // setup FAME fetchmap
1310 PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
1311 for (rs = 0x88; rs < 0x90; rs++)
1312 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
1319 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1320 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1321 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1322 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1324 // setup poll detector
1325 m68k_poll.flag = P32XF_68KPOLL;
1326 m68k_poll.cyc_max = 64;
1327 sh2_poll[0].flag = P32XF_MSH2POLL;
1328 sh2_poll[0].cyc_max = 21;
1329 sh2_poll[1].flag = P32XF_SSH2POLL;
1330 sh2_poll[1].cyc_max = 16;