3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 ? (16bit VRES clr) 4014
18 * a15116 ? (16bit Vint clr) 4016
19 * a15118 ? (16bit Hint clr) 4018
20 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
21 * a1511c ? (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * rom 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch(int b);
53 #define POLL_THRESHOLD 3
60 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
64 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
65 && cycles - m68k_poll.cycles <= 64)
67 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
68 if (!(Pico32x.emu_flags & flags)) {
69 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
70 a, cycles - m68k_poll.cycles);
73 Pico32x.emu_flags |= flags;
80 m68k_poll.cycles = cycles;
85 void p32x_m68k_poll_event(u32 flags)
87 if (Pico32x.emu_flags & flags) {
88 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
89 Pico32x.emu_flags & ~flags);
90 Pico32x.emu_flags &= ~flags;
93 m68k_poll.addr = m68k_poll.cnt = 0;
96 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
98 int cycles_left = sh2_cycles_left(sh2);
100 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
101 if (sh2->poll_cnt++ > 3) {
102 if (!(sh2->state & flags))
103 elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
104 sh2->state, sh2->state | flags);
108 pevt_log_sh2(sh2, EVT_POLL_START);
115 sh2->poll_cycles = cycles_left;
118 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
120 if (sh2->state & flags) {
121 elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
122 sh2->state, sh2->state & ~flags);
124 if (sh2->m68krcycles_done < m68k_cycles)
125 sh2->m68krcycles_done = m68k_cycles;
127 pevt_log_sh2_o(sh2, EVT_POLL_END);
130 sh2->state &= ~flags;
131 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
134 static void sh2s_sync_on_read(SH2 *sh2)
137 if (sh2->poll_cnt != 0)
140 cycles = sh2_cycles_done(sh2);
142 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
148 static int p32x_csum_faked;
149 static const u16 comm_fakevals[] = {
150 0x4d5f, 0x4f4b, // M_OK
151 0x535f, 0x4f4b, // S_OK
152 0x4D41, 0x5346, // MASF - Brutal Unleashed
153 0x5331, 0x4d31, // Darxide
156 0x0000, 0x0000, // eq for doom
157 0x0002, // Mortal Kombat
161 static u32 sh2_comm_faker(u32 a)
164 if (a == 0x28 && !p32x_csum_faked) {
166 return *(unsigned short *)(Pico.rom + 0x18e);
168 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
170 return comm_fakevals[f++];
176 unsigned int sar, dar; // src, dst addr
177 unsigned int tcr; // transfer count
178 unsigned int chcr; // chan ctl
179 // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
180 // ts - transfer size: 1, 2, 4, 16 bytes
181 // ar - auto request if 1, else dreq signal
185 #define DMA_AR (1 << 9)
186 #define DMA_IE (1 << 2)
187 #define DMA_TE (1 << 1)
188 #define DMA_DE (1 << 0)
192 struct dma_chan chan[2];
193 unsigned int vcrdma0;
194 unsigned int unknown0;
195 unsigned int vcrdma1;
196 unsigned int unknown1;
199 // pr - priority: chan0 > chan1 or round-robin
200 // ae - address error
201 // nmif - nmi occurred
202 // dme - DMA master enable
203 #define DMA_DME (1 << 0)
206 static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
208 char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
209 struct dmac *dmac = (void *)(regs + 0x180);
210 int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
211 int vector = (chan == &dmac->chan[0]) ?
212 dmac->vcrdma0 : dmac->vcrdma1;
214 elprintf(EL_32X, "dmac irq %d %d", level, vector);
215 sh2_internal_irq(sh2, level, vector & 0x7f);
218 static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
220 chan->chcr |= DMA_TE; // DMA has ended normally
222 p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
223 if (chan->chcr & DMA_IE)
224 dmac_te_irq(sh2, chan);
227 static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
231 size = (chan->chcr >> 10) & 3;
234 d = p32x_sh2_read8(chan->sar, sh2);
235 p32x_sh2_write8(chan->dar, d, sh2);
237 d = p32x_sh2_read16(chan->sar, sh2);
238 p32x_sh2_write16(chan->dar, d, sh2);
241 d = p32x_sh2_read32(chan->sar, sh2);
242 p32x_sh2_write32(chan->dar, d, sh2);
245 elprintf(EL_32X|EL_ANOMALY, "TODO: 16byte DMA");
246 chan->sar += 16; // always?
253 if (chan->chcr & (1 << 15))
255 if (chan->chcr & (1 << 14))
257 if (chan->chcr & (1 << 13))
259 if (chan->chcr & (1 << 12))
263 static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
265 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
268 // debug/sanity checks
269 if (chan->tcr != *dreqlen)
270 elprintf(EL_32X|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
271 chan->tcr, *dreqlen);
272 // note: DACK is not connected, single addr mode should not be used
273 if ((chan->chcr & 0x3f08) != 0x0400)
274 elprintf(EL_32X|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
275 if (chan->sar != 0x20004012)
276 elprintf(EL_32X|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
278 // HACK: assume bus is busy and SH2 is halted
279 sh2->state |= SH2_STATE_SLEEP;
281 for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
282 elprintf(EL_32X, "dmaw [%08x] %04x, left %d",
283 chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
284 p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
290 if (Pico32x.dmac0_fifo_ptr != i)
291 memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
292 (Pico32x.dmac0_fifo_ptr - i) * 2);
293 Pico32x.dmac0_fifo_ptr -= i;
295 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
297 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
299 dmac_transfer_complete(sh2, chan);
301 sh2_end_run(sh2, 16);
304 static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
306 // debug/sanity checks
307 if ((chan->chcr & 0xc308) != 0x0000)
308 elprintf(EL_32X|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
309 if ((chan->dar & ~0xf) != 0x20004030)
310 elprintf(EL_32X|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
312 dmac_transfer_one(sh2, chan);
314 dmac_transfer_complete(sh2, chan);
317 static void dreq0_trigger(void)
319 struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
320 struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
322 elprintf(EL_32X, "dreq0_trigger\n");
323 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
324 dreq0_do(&msh2, &mdmac->chan[0]);
326 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
327 dreq0_do(&ssh2, &sdmac->chan[0]);
331 void p32x_dreq1_trigger(void)
333 struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
334 struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
337 elprintf(EL_32X, "dreq1_trigger\n");
338 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
339 dreq1_do(&msh2, &mdmac->chan[1]);
342 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
343 dreq1_do(&ssh2, &sdmac->chan[1]);
348 elprintf(EL_32X|EL_ANOMALY, "dreq1: nobody cared");
351 // DMA trigger by SH2 register write
352 static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
354 elprintf(EL_32X, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
355 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
356 chan->tcr &= 0xffffff;
358 if (chan->chcr & DMA_AR) {
359 // auto-request transfer
360 while ((int)chan->tcr > 0)
361 dmac_transfer_one(sh2, chan);
362 dmac_transfer_complete(sh2, chan);
366 // DREQ0 is only sent after first 4 words are written.
367 // we do multiple of 4 words to avoid messing up alignment
368 if (chan->sar == 0x20004012) {
369 if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
370 elprintf(EL_32X, "68k -> sh2 DMA");
376 elprintf(EL_32X|EL_ANOMALY, "unhandled DMA: "
377 "%08x->%08x, cnt %d, chcr %04x @%06x",
378 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
381 // ------------------------------------------------------------------
384 static u32 p32x_reg_read16(u32 a)
389 if ((a & 0x30) == 0x20)
390 return sh2_comm_faker(a);
392 if ((a & 0x30) == 0x20) {
394 unsigned int cycles = SekCyclesDoneT();
395 int comreg = 1 << (a & 0x0f) / 2;
397 // evil X-Men proto polls in a dbra loop and expects it to expire..
398 if (SekDar(2) != dr2)
402 if (cycles - msh2.m68krcycles_done > 500)
403 p32x_sync_sh2s(cycles);
404 if (Pico32x.comm_dirty_sh2 & comreg)
405 Pico32x.comm_dirty_sh2 &= ~comreg;
406 else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
415 if (a == 2) { // INTM, INTS
416 unsigned int cycles = SekCyclesDoneT();
417 if (cycles - msh2.m68krcycles_done > 64)
418 p32x_sync_sh2s(cycles);
419 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
422 if ((a & 0x30) == 0x30)
423 return p32x_pwm_read16(a, SekCyclesDoneT());
426 return Pico32x.regs[a / 2];
429 static void p32x_reg_write8(u32 a, u32 d)
431 u16 *r = Pico32x.regs;
434 // for things like bset on comm port
438 case 0: // adapter ctl
439 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
441 case 1: // adapter ctl, RES bit writeable
442 if ((d ^ r[0]) & d & P32XS_nRES)
444 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
447 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
448 p32x_sync_sh2s(SekCyclesDoneT());
449 Pico32x.sh2irqi[0] |= P32XI_CMD;
450 p32x_update_irls(NULL);
452 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
453 p32x_sync_sh2s(SekCyclesDoneT());
454 Pico32x.sh2irqi[1] |= P32XI_CMD;
455 p32x_update_irls(NULL);
466 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
473 if ((a & 0x30) == 0x20) {
475 int cycles = SekCyclesDoneT();
481 comreg = 1 << (a & 0x0f) / 2;
482 if (Pico32x.comm_dirty_68k & comreg)
483 p32x_sync_sh2s(cycles);
486 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
487 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
488 Pico32x.comm_dirty_68k |= comreg;
490 if (cycles - (int)msh2.m68krcycles_done > 120)
491 p32x_sync_sh2s(cycles);
496 static void p32x_reg_write16(u32 a, u32 d)
498 u16 *r = Pico32x.regs;
501 // for things like bset on comm port
505 case 0x00: // adapter ctl
506 if ((d ^ r[0]) & d & P32XS_nRES)
508 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
510 case 0x10: // DREQ len
513 case 0x12: // FIFO reg
514 if (!(r[6 / 2] & P32XS_68S)) {
515 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
518 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
519 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
520 if ((Pico32x.dmac0_fifo_ptr & 3) == 0)
522 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
523 r[6 / 2] |= P32XS_FULL;
529 if ((a & 0x38) == 0x08) {
534 else if ((a & 0x30) == 0x20) {
535 int cycles = SekCyclesDoneT();
541 comreg = 1 << (a & 0x0f) / 2;
542 if (Pico32x.comm_dirty_68k & comreg)
543 p32x_sync_sh2s(cycles);
546 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
547 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
548 Pico32x.comm_dirty_68k |= comreg;
550 if (cycles - (int)msh2.m68krcycles_done > 120)
551 p32x_sync_sh2s(cycles);
555 else if ((a & 0x30) == 0x30) {
556 p32x_pwm_write16(a, d, SekCyclesDoneT());
560 p32x_reg_write8(a + 1, d);
563 // ------------------------------------------------------------------
565 static u32 p32x_vdp_read16(u32 a)
569 return Pico32x.vdp_regs[a / 2];
572 static void p32x_vdp_write8(u32 a, u32 d)
574 u16 *r = Pico32x.vdp_regs;
577 // TODO: verify what's writeable
580 // priority inversion is handled in palette
581 if ((r[0] ^ d) & P32XV_PRI)
582 Pico32x.dirty_pal = 1;
583 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
585 case 0x03: // shift (for pp mode)
588 case 0x05: // fill len
593 Pico32x.pending_fb = d;
594 // if we are blanking and FS bit is changing
595 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
596 r[0x0a/2] ^= P32XV_FS;
597 Pico32xSwapDRAM(d ^ 1);
598 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
604 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
607 if (a == 6) { // fill start
608 Pico32x.vdp_regs[6 / 2] = d;
611 if (a == 8) { // fill data
612 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
613 int len = Pico32x.vdp_regs[4 / 2] + 1;
615 a = Pico32x.vdp_regs[6 / 2];
618 a = (a & 0xff00) | ((a + 1) & 0xff);
620 Pico32x.vdp_regs[0x06 / 2] = a;
621 Pico32x.vdp_regs[0x08 / 2] = d;
622 if (sh2 != NULL && len > 4) {
623 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
624 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
625 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
630 p32x_vdp_write8(a | 1, d);
633 // ------------------------------------------------------------------
636 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
638 u16 *r = Pico32x.regs;
642 case 0x00: // adapter/irq ctl
643 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
644 case 0x04: // H count (often as comm too)
645 sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
646 sh2s_sync_on_read(&sh2s[cpuid]);
647 return Pico32x.sh2_regs[4 / 2];
648 case 0x10: // DREQ len
653 if ((a & 0x38) == 0x08)
656 if ((a & 0x30) == 0x20) {
657 int comreg = 1 << (a & 0x0f) / 2;
658 if (Pico32x.comm_dirty_68k & comreg)
659 Pico32x.comm_dirty_68k &= ~comreg;
661 sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
662 sh2s_sync_on_read(&sh2s[cpuid]);
665 if ((a & 0x30) == 0x30) {
666 return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
672 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
676 sh2s[cpuid].poll_addr = 0;
680 Pico32x.regs[0] &= ~P32XS_FM;
681 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
683 case 1: // HEN/irq masks
684 if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
685 elprintf(EL_ANOMALY|EL_32X, "HEN");
686 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
687 Pico32x.sh2_regs[0] &= ~0x80;
688 Pico32x.sh2_regs[0] |= d & 0x80;
690 p32x_pwm_schedule_sh2(&sh2s[cpuid]);
691 p32x_update_irls(&sh2s[cpuid]);
695 if (Pico32x.sh2_regs[4 / 2] != d) {
696 Pico32x.sh2_regs[4 / 2] = d;
697 p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
698 sh2_cycles_done_m68k(&sh2s[cpuid]));
699 sh2_end_run(&sh2s[cpuid], 4);
704 if ((a & 0x30) == 0x20) {
705 u8 *r8 = (u8 *)Pico32x.regs;
711 p32x_m68k_poll_event(P32XF_68KCPOLL);
712 p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
713 sh2_cycles_done_m68k(&sh2s[cpuid]));
714 comreg = 1 << (a & 0x0f) / 2;
715 Pico32x.comm_dirty_sh2 |= comreg;
720 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
724 sh2s[cpuid].poll_addr = 0;
727 if ((a & 0x30) == 0x20) {
729 if (Pico32x.regs[a / 2] == d)
732 Pico32x.regs[a / 2] = d;
733 p32x_m68k_poll_event(P32XF_68KCPOLL);
734 p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
735 sh2_cycles_done_m68k(&sh2s[cpuid]));
736 comreg = 1 << (a & 0x0f) / 2;
737 Pico32x.comm_dirty_sh2 |= comreg;
741 else if ((a & 0x30) == 0x30) {
742 p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
748 Pico32x.regs[0] &= ~P32XS_FM;
749 Pico32x.regs[0] |= d & P32XS_FM;
751 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
752 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
753 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
754 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
756 Pico32x.sh2irqs &= ~P32XI_PWM;
757 p32x_pwm_schedule_sh2(&sh2s[cpuid]);
761 p32x_sh2reg_write8(a | 1, d, cpuid);
765 p32x_update_irls(&sh2s[cpuid]);
768 // ------------------------------------------------------------------
769 // SH2 internal peripherals
770 // we keep them in little endian format
771 static u32 sh2_peripheral_read8(u32 a, int id)
773 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
779 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
783 static u32 sh2_peripheral_read16(u32 a, int id)
785 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
791 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
795 static u32 sh2_peripheral_read32(u32 a, int id)
799 d = Pico32xMem->sh2_peri_regs[id][a / 4];
801 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
805 static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
807 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
808 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
814 if ((a == 2 && (d & 0x20)) || // transmiter enabled
815 (a == 4 && !(d & 0x80))) { // valid data in TDR
816 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
817 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
818 int level = PREG8(oregs, 0x60) >> 4;
819 int vector = PREG8(oregs, 0x63) & 0x7f;
820 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
821 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
828 static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
830 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
831 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
837 if ((d & 0xff00) == 0xa500) { // WTCSR
839 p32x_timers_recalc();
841 if ((d & 0xff00) == 0x5a00) // WTCNT
850 static void sh2_peripheral_write32(u32 a, u32 d, int id)
852 u32 *r = Pico32xMem->sh2_peri_regs[id];
853 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
859 // division unit (TODO: verify):
860 case 0x104: // DVDNT: divident L, starts divide
861 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
863 signed int divisor = r[0x100 / 4];
864 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
865 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
868 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
871 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
872 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
874 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
875 signed int divisor = r[0x100 / 4];
876 // XXX: undocumented mirroring to 0x118,0x11c?
877 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
879 r[0x11c / 4] = r[0x114 / 4] = divident;
881 if ((unsigned long long)divident + 1 > 1) {
882 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
883 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
887 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
891 // perhaps starting a DMA?
892 if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
893 struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
894 if (!(dmac->dmaor & DMA_DME))
897 if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
898 dmac_trigger(&sh2s[id], &dmac->chan[0]);
899 if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
900 dmac_trigger(&sh2s[id], &dmac->chan[1]);
904 // ------------------------------------------------------------------
908 static u32 PicoRead8_32x_on(u32 a)
911 if ((a & 0xffc0) == 0x5100) { // a15100
912 d = p32x_reg_read16(a);
916 if ((a & 0xfc00) != 0x5000)
917 return PicoRead8_io(a);
919 if ((a & 0xfff0) == 0x5180) { // a15180
920 d = p32x_vdp_read16(a);
924 if ((a & 0xfe00) == 0x5200) { // a15200
925 d = Pico32xMem->pal[(a & 0x1ff) / 2];
929 if ((a & 0xfffc) == 0x30ec) { // a130ec
934 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
944 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
948 static u32 PicoRead16_32x_on(u32 a)
951 if ((a & 0xffc0) == 0x5100) { // a15100
952 d = p32x_reg_read16(a);
956 if ((a & 0xfc00) != 0x5000)
957 return PicoRead16_io(a);
959 if ((a & 0xfff0) == 0x5180) { // a15180
960 d = p32x_vdp_read16(a);
964 if ((a & 0xfe00) == 0x5200) { // a15200
965 d = Pico32xMem->pal[(a & 0x1ff) / 2];
969 if ((a & 0xfffc) == 0x30ec) { // a130ec
970 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
974 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
978 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
982 static void PicoWrite8_32x_on(u32 a, u32 d)
984 if ((a & 0xfc00) == 0x5000)
985 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
987 if ((a & 0xffc0) == 0x5100) { // a15100
988 p32x_reg_write8(a, d);
992 if ((a & 0xfc00) != 0x5000) {
997 if (!(Pico32x.regs[0] & P32XS_FM)) {
998 if ((a & 0xfff0) == 0x5180) { // a15180
999 p32x_vdp_write8(a, d);
1004 if ((a & 0xfe00) == 0x5200) { // a15200
1005 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1006 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
1007 Pico32x.dirty_pal = 1;
1012 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1015 static void PicoWrite16_32x_on(u32 a, u32 d)
1017 if ((a & 0xfc00) == 0x5000)
1018 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1020 if ((a & 0xffc0) == 0x5100) { // a15100
1021 p32x_reg_write16(a, d);
1025 if ((a & 0xfc00) != 0x5000) {
1026 PicoWrite16_io(a, d);
1030 if (!(Pico32x.regs[0] & P32XS_FM)) {
1031 if ((a & 0xfff0) == 0x5180) { // a15180
1032 p32x_vdp_write16(a, d, NULL); // FIXME?
1036 if ((a & 0xfe00) == 0x5200) { // a15200
1037 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1038 Pico32x.dirty_pal = 1;
1043 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1047 u32 PicoRead8_32x(u32 a)
1050 if ((a & 0xffc0) == 0x5100) { // a15100
1051 // regs are always readable
1052 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
1056 if ((a & 0xfffc) == 0x30ec) { // a130ec
1057 d = str_mars[a & 3];
1061 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
1065 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
1069 u32 PicoRead16_32x(u32 a)
1072 if ((a & 0xffc0) == 0x5100) { // a15100
1073 d = Pico32x.regs[(a & 0x3f) / 2];
1077 if ((a & 0xfffc) == 0x30ec) { // a130ec
1078 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
1082 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
1086 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
1090 void PicoWrite8_32x(u32 a, u32 d)
1092 if ((a & 0xffc0) == 0x5100) { // a15100
1093 u16 *r = Pico32x.regs;
1095 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1098 if ((d ^ r[0]) & d & P32XS_ADEN) {
1100 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1102 p32x_reg_write8(a, d); // forward for reset processing
1107 // allow only COMM for now
1108 if ((a & 0x30) == 0x20) {
1115 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1118 void PicoWrite16_32x(u32 a, u32 d)
1120 if ((a & 0xffc0) == 0x5100) { // a15100
1121 u16 *r = Pico32x.regs;
1123 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1126 if ((d ^ r[0]) & d & P32XS_ADEN) {
1128 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1130 p32x_reg_write16(a, d); // forward for reset processing
1135 // allow only COMM for now
1136 if ((a & 0x30) == 0x20)
1141 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1144 // -----------------------------------------------------------------
1146 // hint vector is writeable
1147 static void PicoWrite8_hint(u32 a, u32 d)
1149 if ((a & 0xfffc) == 0x0070) {
1150 Pico32xMem->m68k_rom[a ^ 1] = d;
1154 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1157 static void PicoWrite16_hint(u32 a, u32 d)
1159 if ((a & 0xfffc) == 0x0070) {
1160 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1164 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1167 static void bank_switch(int b)
1169 unsigned int rs, bank;
1172 if (bank >= Pico.romsize) {
1173 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1177 // 32X ROM (unbanked, XXX: consider mirroring?)
1178 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1182 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1183 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1185 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1188 // setup FAME fetchmap
1189 for (rs = 0x90; rs < 0xa0; rs++)
1190 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
1194 // -----------------------------------------------------------------
1196 // -----------------------------------------------------------------
1199 static u32 sh2_read8_unmapped(u32 a, int id)
1201 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
1202 id ? 's' : 'm', a, 0, sh2_pc(id));
1206 static u32 sh2_read8_cs0(u32 a, int id)
1210 // 0x3ff00 is veridied
1211 if ((a & 0x3ff00) == 0x4000) {
1212 d = p32x_sh2reg_read16(a, id);
1216 if ((a & 0x3ff00) == 0x4100) {
1217 d = p32x_vdp_read16(a);
1218 sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
1223 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1224 return Pico32xMem->sh2_rom_m[a ^ 1];
1225 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1226 return Pico32xMem->sh2_rom_s[a ^ 1];
1228 if ((a & 0x3fe00) == 0x4200) {
1229 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1233 return sh2_read8_unmapped(a, id);
1241 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
1242 id ? 's' : 'm', a, d, sh2_pc(id));
1246 static u32 sh2_read8_da(u32 a, int id)
1248 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
1252 static u32 sh2_read16_unmapped(u32 a, int id)
1254 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
1255 id ? 's' : 'm', a, 0, sh2_pc(id));
1259 static u32 sh2_read16_cs0(u32 a, int id)
1263 if ((a & 0x3ff00) == 0x4000) {
1264 d = p32x_sh2reg_read16(a, id);
1265 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1270 if ((a & 0x3ff00) == 0x4100) {
1271 d = p32x_vdp_read16(a);
1272 sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
1276 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1277 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1278 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1279 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1281 if ((a & 0x3fe00) == 0x4200) {
1282 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1286 return sh2_read16_unmapped(a, id);
1289 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1290 id ? 's' : 'm', a, d, sh2_pc(id));
1294 static u32 sh2_read16_da(u32 a, int id)
1296 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
1299 static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
1305 static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
1307 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1308 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1312 static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
1314 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1315 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1317 if (Pico32x.regs[0] & P32XS_FM) {
1318 if ((a & 0x3ff00) == 0x4100) {
1319 sh2s[id].poll_addr = 0;
1320 p32x_vdp_write8(a, d);
1325 if ((a & 0x3ff00) == 0x4000) {
1326 p32x_sh2reg_write8(a, d, id);
1330 return sh2_write8_unmapped(a, d, id);
1333 /* quirk: in both normal and overwrite areas only nonzero values go through */
1334 #define sh2_write8_dramN(n) \
1335 if ((d & 0xff) != 0) { \
1336 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1337 dram[(a & 0x1ffff) ^ 1] = d; \
1341 static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
1343 sh2_write8_dramN(0);
1346 static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
1348 sh2_write8_dramN(1);
1351 static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
1353 u32 a1 = a & 0x3ffff;
1355 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1357 sh2_drc_wcheck_ram(a, t, id);
1359 Pico32xMem->sdram[a1 ^ 1] = d;
1363 static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
1367 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1369 sh2_drc_wcheck_da(a, t, id);
1371 Pico32xMem->data_array[id][a1 ^ 1] = d;
1376 static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
1378 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1379 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1383 static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
1385 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1386 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1387 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1389 if (Pico32x.regs[0] & P32XS_FM) {
1390 if ((a & 0x3ff00) == 0x4100) {
1391 sh2s[id].poll_addr = 0;
1392 p32x_vdp_write16(a, d, &sh2s[id]);
1396 if ((a & 0x3fe00) == 0x4200) {
1397 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1398 Pico32x.dirty_pal = 1;
1403 if ((a & 0x3ff00) == 0x4000) {
1404 p32x_sh2reg_write16(a, d, id);
1408 return sh2_write16_unmapped(a, d, id);
1411 #define sh2_write16_dramN(n) \
1412 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1413 if (!(a & 0x20000)) { \
1418 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1419 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1423 static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
1425 sh2_write16_dramN(0);
1428 static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
1430 sh2_write16_dramN(1);
1433 static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
1435 u32 a1 = a & 0x3ffff;
1437 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1439 sh2_drc_wcheck_ram(a, t, id);
1441 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1445 static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
1449 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1451 sh2_drc_wcheck_da(a, t, id);
1453 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
1458 typedef u32 (sh2_read_handler)(u32 a, int id);
1459 typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
1461 #define SH2MAP_ADDR2OFFS_R(a) \
1462 ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
1464 #define SH2MAP_ADDR2OFFS_W(a) \
1465 ((u32)(a) >> SH2_WRITE_SHIFT)
1467 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1469 const sh2_memmap *sh2_map = sh2->read8_map;
1472 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1474 if (map_flag_set(p))
1475 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1477 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1480 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1482 const sh2_memmap *sh2_map = sh2->read16_map;
1485 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1487 if (map_flag_set(p))
1488 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1490 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1493 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1495 const sh2_memmap *sh2_map = sh2->read16_map;
1496 sh2_read_handler *handler;
1500 offs = SH2MAP_ADDR2OFFS_R(a);
1503 if (!map_flag_set(p)) {
1504 // XXX: maybe 32bit access instead with ror?
1505 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1506 return (pd[0] << 16) | pd[1];
1510 return sh2_peripheral_read32(a, sh2->is_slave);
1512 handler = (sh2_read_handler *)(p << 1);
1513 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1516 // return nonzero if write potentially causes an interrupt (used by drc)
1517 int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1519 const void **sh2_wmap = sh2->write8_tab;
1520 sh2_write_handler *wh;
1522 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1523 return wh(a, d, sh2->is_slave);
1526 int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1528 const void **sh2_wmap = sh2->write16_tab;
1529 sh2_write_handler *wh;
1531 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1532 return wh(a, d, sh2->is_slave);
1535 int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1537 const void **sh2_wmap = sh2->write16_tab;
1538 sh2_write_handler *handler;
1541 offs = SH2MAP_ADDR2OFFS_W(a);
1543 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1544 sh2_peripheral_write32(a, d, sh2->is_slave);
1548 handler = sh2_wmap[offs];
1549 handler(a, d >> 16, sh2->is_slave);
1550 handler(a + 2, d, sh2->is_slave);
1554 // -----------------------------------------------------------------
1556 static const u16 msh2_code[] = {
1557 // trap instructions
1558 0xaffe, // bra <self>
1560 // have to wait a bit until m68k initial program finishes clearing stuff
1561 // to avoid races with game SH2 code, like in Tempo
1562 0xd004, // mov.l @(_m_ok,pc), r0
1563 0xd105, // mov.l @(_cnt,pc), r1
1564 0xd205, // mov.l @(_start,pc), r2
1565 0x71ff, // add #-1, r1
1566 0x4115, // cmp/pl r1
1568 0xc208, // mov.l r0, @(h'20,gbr)
1569 0x6822, // mov.l @r2, r8
1572 ('M'<<8)|'_', ('O'<<8)|'K',
1574 0x2200, 0x03e0 // master start pointer in ROM
1577 static const u16 ssh2_code[] = {
1578 0xaffe, // bra <self>
1580 // code to wait for master, in case authentic master BIOS is used
1581 0xd104, // mov.l @(_m_ok,pc), r1
1582 0xd206, // mov.l @(_start,pc), r2
1583 0xc608, // mov.l @(h'20,gbr), r0
1584 0x3100, // cmp/eq r0, r1
1586 0xd003, // mov.l @(_s_ok,pc), r0
1587 0xc209, // mov.l r0, @(h'24,gbr)
1588 0x6822, // mov.l @r2, r8
1591 ('M'<<8)|'_', ('O'<<8)|'K',
1592 ('S'<<8)|'_', ('O'<<8)|'K',
1593 0x2200, 0x03e4 // slave start pointer in ROM
1596 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1597 static void get_bios(void)
1604 if (p32x_bios_g != NULL) {
1605 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1606 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1610 ps = (u16 *)Pico32xMem->m68k_rom;
1612 for (i = 1; i < 0xc0/4; i++)
1613 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1616 for (i = 0xc0/2; i < 0x100/2; i++)
1620 ps[0xc0/2] = 0x46fc;
1621 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1622 ps[0xfe/2] = 0x60fe; // jump to self
1624 ps[0xfe/2] = 0x4e75; // rts
1627 // fill remaining m68k_rom page with game ROM
1628 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1629 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1630 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1633 if (p32x_bios_m != NULL) {
1634 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1635 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1638 pl = (u32 *)Pico32xMem->sh2_rom_m;
1640 // fill exception vector table to our trap address
1641 for (i = 0; i < 128; i++)
1642 pl[i] = HWSWAP(0x200);
1645 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1648 pl[1] = pl[3] = HWSWAP(0x6040000);
1650 pl[0] = pl[2] = HWSWAP(0x204);
1654 if (p32x_bios_s != NULL) {
1655 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1656 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1659 pl = (u32 *)Pico32xMem->sh2_rom_s;
1661 // fill exception vector table to our trap address
1662 for (i = 0; i < 128; i++)
1663 pl[i] = HWSWAP(0x200);
1666 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1669 pl[1] = pl[3] = HWSWAP(0x603f800);
1671 pl[0] = pl[2] = HWSWAP(0x204);
1675 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1676 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1678 static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
1679 // for writes we are using handlers only
1680 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1682 void Pico32xSwapDRAM(int b)
1684 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1685 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1686 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1687 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1690 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1691 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1693 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1694 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1697 void PicoMemSetup32x(void)
1702 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1703 if (Pico32xMem == NULL) {
1704 elprintf(EL_STATUS, "OOM");
1710 // cartridge area becomes unmapped
1711 // XXX: we take the easy way and don't unmap ROM,
1712 // so that we can avoid handling the RV bit.
1713 // m68k_map_unmap(0x000000, 0x3fffff);
1716 rs = sizeof(Pico32xMem->m68k_rom_bank);
1717 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1718 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1719 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1720 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1722 // 32X ROM (unbanked, XXX: consider mirroring?)
1723 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1726 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1727 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1729 // setup FAME fetchmap
1730 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1731 for (rs = 0x88; rs < 0x90; rs++)
1732 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1739 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1740 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1741 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1742 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1744 // SH2 maps: A31,A30,A29,CS1,CS0
1745 // all unmapped by default
1746 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1747 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1748 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1751 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1752 sh2_write8_map[i] = sh2_write8_unmapped;
1753 sh2_write16_map[i] = sh2_write16_unmapped;
1757 for (i = 0x40; i <= 0x5f; i++) {
1758 sh2_write8_map[i >> 1] =
1759 sh2_write16_map[i >> 1] = sh2_write_ignore;
1763 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1764 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
1765 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1766 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1768 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1769 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1770 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1771 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1772 // CS2 - DRAM - done by Pico32xSwapDRAM()
1773 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1774 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1776 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
1777 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1778 sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
1779 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1780 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
1781 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
1783 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1784 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
1785 sh2_write8_map[0xc0/2] = sh2_write8_da;
1786 sh2_write16_map[0xc0/2] = sh2_write16_da;
1788 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1789 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
1790 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1791 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1793 // map DRAM area, both 68k and SH2
1796 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1797 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1798 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1799 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1801 sh2_drc_mem_setup(&msh2);
1802 sh2_drc_mem_setup(&ssh2);
1805 void Pico32xMemStateLoaded(void)
1807 bank_switch(Pico32x.regs[4 / 2]);
1808 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1809 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1810 Pico32x.dirty_pal = 1;
1812 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1813 memset(&m68k_poll, 0, sizeof(m68k_poll));
1815 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1817 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1819 sh2_drc_flush_all();
1822 // vim:shiftwidth=2:ts=2:expandtab