3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 0 (16bit VRES clr) 4014
18 * a15116 0 (16bit Vint clr) 4016
19 * a15118 0 (16bit Hint clr) 4018
20 * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
21 * a1511c 0 (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * cart 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch(int b);
52 // addressing byte in 16bit reg
53 #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
56 #define POLL_THRESHOLD 3
63 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
67 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
68 && cycles - m68k_poll.cycles <= 64 && !SekNotPolling)
70 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
71 if (!(Pico32x.emu_flags & flags)) {
72 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
73 a, cycles - m68k_poll.cycles);
76 Pico32x.emu_flags |= flags;
84 m68k_poll.cycles = cycles;
89 void p32x_m68k_poll_event(u32 flags)
91 if (Pico32x.emu_flags & flags) {
92 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
93 Pico32x.emu_flags & ~flags);
94 Pico32x.emu_flags &= ~flags;
97 m68k_poll.addr = m68k_poll.cnt = 0;
100 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
102 int cycles_left = sh2_cycles_left(sh2);
104 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
105 if (sh2->poll_cnt++ > maxcnt) {
106 if (!(sh2->state & flags))
107 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
108 sh2->state, sh2->state | flags);
112 pevt_log_sh2(sh2, EVT_POLL_START);
119 sh2->poll_cycles = cycles_left;
122 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
124 if (sh2->state & flags) {
125 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
126 sh2->state & ~flags);
128 if (sh2->m68krcycles_done < m68k_cycles)
129 sh2->m68krcycles_done = m68k_cycles;
131 pevt_log_sh2_o(sh2, EVT_POLL_END);
134 sh2->state &= ~flags;
135 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
138 static void sh2s_sync_on_read(SH2 *sh2)
141 if (sh2->poll_cnt != 0)
144 cycles = sh2_cycles_done(sh2);
146 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
152 static int p32x_csum_faked;
153 static const u16 comm_fakevals[] = {
154 0x4d5f, 0x4f4b, // M_OK
155 0x535f, 0x4f4b, // S_OK
156 0x4D41, 0x5346, // MASF - Brutal Unleashed
157 0x5331, 0x4d31, // Darxide
160 0x0000, 0x0000, // eq for doom
161 0x0002, // Mortal Kombat
165 static u32 sh2_comm_faker(u32 a)
168 if (a == 0x28 && !p32x_csum_faked) {
170 return *(unsigned short *)(Pico.rom + 0x18e);
172 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
174 return comm_fakevals[f++];
178 // ------------------------------------------------------------------
181 static u32 p32x_reg_read16(u32 a)
186 if ((a & 0x30) == 0x20)
187 return sh2_comm_faker(a);
189 if ((a & 0x30) == 0x20) {
190 unsigned int cycles = SekCyclesDone();
191 int comreg = 1 << (a & 0x0f) / 2;
193 if (cycles - msh2.m68krcycles_done > 244
194 || (Pico32x.comm_dirty_68k & comreg))
195 p32x_sync_sh2s(cycles);
197 if (Pico32x.comm_dirty_sh2 & comreg)
198 Pico32x.comm_dirty_sh2 &= ~comreg;
199 else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
207 if (a == 2) { // INTM, INTS
208 unsigned int cycles = SekCyclesDone();
209 if (cycles - msh2.m68krcycles_done > 64)
210 p32x_sync_sh2s(cycles);
214 if ((a & 0x30) == 0x30)
215 return p32x_pwm_read16(a, NULL, SekCyclesDone());
218 return Pico32x.regs[a / 2];
221 static void dreq0_write(u16 *r, u32 d)
223 if (!(r[6 / 2] & P32XS_68S)) {
224 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
225 return; // ignored - tested
227 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
228 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
229 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
230 r[6 / 2] |= P32XS_FULL;
231 // tested: len register decrements and 68S clears
232 // even if SH2s/DMAC aren't active..
234 if (r[0x10 / 2] == 0)
235 r[6 / 2] &= ~P32XS_68S;
237 if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
238 p32x_sync_sh2s(SekCyclesDone());
239 p32x_dreq0_trigger();
243 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
246 // writable bits tested
247 static void p32x_reg_write8(u32 a, u32 d)
249 u16 *r = Pico32x.regs;
252 // for things like bset on comm port
256 case 0x00: // adapter ctl: FM writable
257 REG8IN16(r, 0x00) = d & 0x80;
259 case 0x01: // adapter ctl: RES and ADEN writable
260 if ((d ^ r[0]) & d & P32XS_nRES)
262 REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
263 REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
265 case 0x02: // ignored, always 0
267 case 0x03: // irq ctl
268 if ((d ^ r[0x02 / 2]) & 3) {
269 int cycles = SekCyclesDone();
270 p32x_sync_sh2s(cycles);
272 p32x_update_cmd_irq(NULL, cycles);
275 case 0x04: // ignored, always 0
279 if (r[0x04 / 2] != d) {
284 case 0x06: // ignored, always 0
286 case 0x07: // DREQ ctl
287 REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
288 if (!(d & P32XS_68S)) {
289 Pico32x.dmac0_fifo_ptr = 0;
290 REG8IN16(r, 0x07) &= ~P32XS_FULL;
292 REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
294 case 0x08: // ignored, always 0
296 case 0x09: // DREQ src
297 REG8IN16(r, 0x09) = d;
300 REG8IN16(r, 0x0a) = d;
303 REG8IN16(r, 0x0b) = d & 0xfe;
305 case 0x0c: // ignored, always 0
307 case 0x0d: // DREQ dest
310 case 0x10: // DREQ len
314 REG8IN16(r, a) = d & 0xfc;
316 // DREQ FIFO - writes to odd addr go to fifo
317 // do writes to even work? Reads return 0
322 d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
323 REG8IN16(r, 0x12) = 0;
326 case 0x14: // ignored, always 0
333 case 0x1a: // what's this?
334 elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
335 REG8IN16(r, a) = d & 0x01;
338 REG8IN16(r, a) = d & 0x01;
340 case 0x1c: // ignored, always 0
346 case 0x31: // PWM control
347 REG8IN16(r, a) &= ~0x0f;
348 REG8IN16(r, a) |= d & 0x0f;
351 case 0x32: // PWM cycle
352 REG8IN16(r, a) = d & 0x0f;
359 // PWM pulse regs.. Only writes to odd address send a value
360 // to FIFO; reads are 0 (except status bits)
369 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
370 REG8IN16(r, a ^ 1) = 0;
372 case 0x3a: // ignored, always 0
380 p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
384 if ((a & 0x30) == 0x20) {
385 int cycles = SekCyclesDone();
388 if (REG8IN16(r, a) == d)
391 comreg = 1 << (a & 0x0f) / 2;
392 if (Pico32x.comm_dirty_68k & comreg)
393 p32x_sync_sh2s(cycles);
396 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
397 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
398 Pico32x.comm_dirty_68k |= comreg;
400 if (cycles - (int)msh2.m68krcycles_done > 120)
401 p32x_sync_sh2s(cycles);
406 static void p32x_reg_write16(u32 a, u32 d)
408 u16 *r = Pico32x.regs;
411 // for things like bset on comm port
415 case 0x00: // adapter ctl
416 if ((d ^ r[0]) & d & P32XS_nRES)
418 r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
419 r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
421 case 0x08: // DREQ src
427 case 0x0c: // DREQ dest
433 case 0x10: // DREQ len
436 case 0x12: // FIFO reg
439 case 0x1a: // TV + mystery bit
440 r[a / 2] = d & 0x0101;
442 case 0x30: // PWM control
443 d = (r[a / 2] & ~0x0f) | (d & 0x0f);
445 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
450 if ((a & 0x30) == 0x20) {
451 int cycles = SekCyclesDone();
457 comreg = 1 << (a & 0x0f) / 2;
458 if (Pico32x.comm_dirty_68k & comreg)
459 p32x_sync_sh2s(cycles);
462 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
463 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
464 Pico32x.comm_dirty_68k |= comreg;
466 if (cycles - (int)msh2.m68krcycles_done > 120)
467 p32x_sync_sh2s(cycles);
471 else if ((a & 0x30) == 0x30) {
472 p32x_pwm_write16(a, d, NULL, SekCyclesDone());
476 p32x_reg_write8(a + 1, d);
479 // ------------------------------------------------------------------
481 static u32 p32x_vdp_read16(u32 a)
486 d = Pico32x.vdp_regs[a / 2];
488 // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
489 // most often at 0xb1-0xb5, even during vblank,
490 // what's the deal with that?
491 // we'll just fake it along with hblank for now
492 Pico32x.vdp_fbcr_fake++;
493 if (Pico32x.vdp_fbcr_fake & 4)
495 if ((Pico32x.vdp_fbcr_fake & 7) == 0)
501 static void p32x_vdp_write8(u32 a, u32 d)
503 u16 *r = Pico32x.vdp_regs;
506 // TODO: verify what's writeable
509 // priority inversion is handled in palette
510 if ((r[0] ^ d) & P32XV_PRI)
511 Pico32x.dirty_pal = 1;
512 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
514 case 0x03: // shift (for pp mode)
517 case 0x05: // fill len
522 Pico32x.pending_fb = d;
523 // if we are blanking and FS bit is changing
524 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
525 r[0x0a/2] ^= P32XV_FS;
526 Pico32xSwapDRAM(d ^ 1);
527 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
533 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
536 if (a == 6) { // fill start
537 Pico32x.vdp_regs[6 / 2] = d;
540 if (a == 8) { // fill data
541 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
542 int len = Pico32x.vdp_regs[4 / 2] + 1;
544 a = Pico32x.vdp_regs[6 / 2];
547 a = (a & 0xff00) | ((a + 1) & 0xff);
549 Pico32x.vdp_regs[0x06 / 2] = a;
550 Pico32x.vdp_regs[0x08 / 2] = d;
551 if (sh2 != NULL && len > 4) {
552 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
553 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
554 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
559 p32x_vdp_write8(a | 1, d);
562 // ------------------------------------------------------------------
565 static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
567 u16 *r = Pico32x.regs;
571 case 0x00: // adapter/irq ctl
572 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
573 | Pico32x.sh2irq_mask[sh2->is_slave];
574 case 0x04: // H count (often as comm too)
575 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
576 sh2s_sync_on_read(sh2);
577 return Pico32x.sh2_regs[4 / 2];
579 return (r[a / 2] & ~P32XS_FULL) | 0x4000;
580 case 0x08: // DREQ src
582 case 0x0c: // DREQ dst
584 case 0x10: // DREQ len
586 case 0x12: // DREQ FIFO - does this work on hw?
587 if (Pico32x.dmac0_fifo_ptr > 0) {
588 Pico32x.dmac0_fifo_ptr--;
589 r[a / 2] = Pico32x.dmac_fifo[0];
590 memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
591 Pico32x.dmac0_fifo_ptr * 2);
603 if ((a & 0x30) == 0x20) {
604 int comreg = 1 << (a & 0x0f) / 2;
605 if (Pico32x.comm_dirty_68k & comreg)
606 Pico32x.comm_dirty_68k &= ~comreg;
608 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
609 sh2s_sync_on_read(sh2);
612 if ((a & 0x30) == 0x30)
613 return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
615 elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
616 "unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
620 static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
622 u16 *r = Pico32x.regs;
631 r[0] |= (d << 8) & P32XS_FM;
633 case 0x01: // HEN/irq masks
634 old = Pico32x.sh2irq_mask[sh2->is_slave];
636 p32x_pwm_sync_to_sh2(sh2);
638 Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
639 Pico32x.sh2_regs[0] &= ~0x80;
640 Pico32x.sh2_regs[0] |= d & 0x80;
643 p32x_pwm_schedule_sh2(sh2);
645 p32x_update_cmd_irq(sh2, 0);
647 p32x_schedule_hint(sh2, 0);
649 case 0x04: // ignored?
651 case 0x05: // H count
653 if (Pico32x.sh2_regs[4 / 2] != d) {
654 Pico32x.sh2_regs[4 / 2] = d;
655 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
656 sh2_cycles_done_m68k(sh2));
661 REG8IN16(r, a) = d & 0x0f;
664 case 0x31: // PWM control
665 REG8IN16(r, a) = d & 0x8f;
668 case 0x32: // PWM cycle
669 REG8IN16(r, a) = d & 0x0f;
676 // PWM pulse regs.. Only writes to odd address send a value
677 // to FIFO; reads are 0 (except status bits)
686 d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
687 REG8IN16(r, a ^ 1) = 0;
689 case 0x3a: // ignored, always 0?
697 p32x_pwm_write16(a & ~1, d, sh2, 0);
701 if ((a & 0x30) == 0x20) {
703 if (REG8IN16(r, a) == d)
707 p32x_m68k_poll_event(P32XF_68KCPOLL);
708 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
709 sh2_cycles_done_m68k(sh2));
710 comreg = 1 << (a & 0x0f) / 2;
711 Pico32x.comm_dirty_sh2 |= comreg;
715 elprintf(EL_32X|EL_ANOMALY,
716 "unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
719 static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
726 if ((a & 0x30) == 0x20) {
728 if (Pico32x.regs[a / 2] == d)
731 Pico32x.regs[a / 2] = d;
732 p32x_m68k_poll_event(P32XF_68KCPOLL);
733 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
734 sh2_cycles_done_m68k(sh2));
735 comreg = 1 << (a & 0x0f) / 2;
736 Pico32x.comm_dirty_sh2 |= comreg;
740 else if ((a & 0x30) == 0x30) {
741 p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
747 Pico32x.regs[0] &= ~P32XS_FM;
748 Pico32x.regs[0] |= d & P32XS_FM;
751 Pico32x.sh2irqs &= ~P32XI_VRES;
754 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
757 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
760 Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
761 p32x_update_cmd_irq(sh2, 0);
764 p32x_pwm_sync_to_sh2(sh2);
765 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
766 p32x_pwm_schedule_sh2(sh2);
770 p32x_sh2reg_write8(a | 1, d, sh2);
774 p32x_update_irls(sh2, 0);
777 // ------------------------------------------------------------------
781 static u32 PicoRead8_32x_on(u32 a)
784 if ((a & 0xffc0) == 0x5100) { // a15100
785 d = p32x_reg_read16(a);
789 if ((a & 0xfc00) != 0x5000) {
790 if (PicoAHW & PAHW_MCD)
791 return PicoRead8_mcd_io(a);
793 return PicoRead8_io(a);
796 if ((a & 0xfff0) == 0x5180) { // a15180
797 d = p32x_vdp_read16(a);
801 if ((a & 0xfe00) == 0x5200) { // a15200
802 d = Pico32xMem->pal[(a & 0x1ff) / 2];
806 if ((a & 0xfffc) == 0x30ec) { // a130ec
811 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
821 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
825 static u32 PicoRead16_32x_on(u32 a)
828 if ((a & 0xffc0) == 0x5100) { // a15100
829 d = p32x_reg_read16(a);
833 if ((a & 0xfc00) != 0x5000) {
834 if (PicoAHW & PAHW_MCD)
835 return PicoRead16_mcd_io(a);
837 return PicoRead16_io(a);
840 if ((a & 0xfff0) == 0x5180) { // a15180
841 d = p32x_vdp_read16(a);
845 if ((a & 0xfe00) == 0x5200) { // a15200
846 d = Pico32xMem->pal[(a & 0x1ff) / 2];
850 if ((a & 0xfffc) == 0x30ec) { // a130ec
851 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
855 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
859 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
863 static void PicoWrite8_32x_on(u32 a, u32 d)
865 if ((a & 0xfc00) == 0x5000)
866 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
868 if ((a & 0xffc0) == 0x5100) { // a15100
869 p32x_reg_write8(a, d);
873 if ((a & 0xfc00) != 0x5000) {
874 if (PicoAHW & PAHW_MCD)
875 PicoWrite8_mcd_io(a, d);
879 bank_switch(Pico32x.regs[4 / 2]);
883 if (!(Pico32x.regs[0] & P32XS_FM)) {
884 if ((a & 0xfff0) == 0x5180) { // a15180
885 p32x_vdp_write8(a, d);
890 if ((a & 0xfe00) == 0x5200) { // a15200
891 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
892 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
893 Pico32x.dirty_pal = 1;
898 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
901 static void PicoWrite16_32x_on(u32 a, u32 d)
903 if ((a & 0xfc00) == 0x5000)
904 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
906 if ((a & 0xffc0) == 0x5100) { // a15100
907 p32x_reg_write16(a, d);
911 if ((a & 0xfc00) != 0x5000) {
912 if (PicoAHW & PAHW_MCD)
913 PicoWrite16_mcd_io(a, d);
915 PicoWrite16_io(a, d);
917 bank_switch(Pico32x.regs[4 / 2]);
921 if (!(Pico32x.regs[0] & P32XS_FM)) {
922 if ((a & 0xfff0) == 0x5180) { // a15180
923 p32x_vdp_write16(a, d, NULL); // FIXME?
927 if ((a & 0xfe00) == 0x5200) { // a15200
928 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
929 Pico32x.dirty_pal = 1;
934 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
938 u32 PicoRead8_32x(u32 a)
941 if ((a & 0xffc0) == 0x5100) { // a15100
942 // regs are always readable
943 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
947 if ((a & 0xfffc) == 0x30ec) { // a130ec
952 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
956 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
960 u32 PicoRead16_32x(u32 a)
963 if ((a & 0xffc0) == 0x5100) { // a15100
964 d = Pico32x.regs[(a & 0x3f) / 2];
968 if ((a & 0xfffc) == 0x30ec) { // a130ec
969 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
973 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
977 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
981 void PicoWrite8_32x(u32 a, u32 d)
983 if ((a & 0xffc0) == 0x5100) { // a15100
984 u16 *r = Pico32x.regs;
986 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
989 if ((d ^ r[0]) & d & P32XS_ADEN) {
991 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
993 p32x_reg_write8(a, d); // forward for reset processing
998 // allow only COMM for now
999 if ((a & 0x30) == 0x20) {
1006 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1009 void PicoWrite16_32x(u32 a, u32 d)
1011 if ((a & 0xffc0) == 0x5100) { // a15100
1012 u16 *r = Pico32x.regs;
1014 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1017 if ((d ^ r[0]) & d & P32XS_ADEN) {
1019 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
1021 p32x_reg_write16(a, d); // forward for reset processing
1026 // allow only COMM for now
1027 if ((a & 0x30) == 0x20)
1032 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1035 /* quirk: in both normal and overwrite areas only nonzero values go through */
1036 #define sh2_write8_dramN(n) \
1037 if ((d & 0xff) != 0) { \
1038 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1039 dram[(a & 0x1ffff) ^ 1] = d; \
1042 static void m68k_write8_dram0_ow(u32 a, u32 d)
1044 sh2_write8_dramN(0);
1047 static void m68k_write8_dram1_ow(u32 a, u32 d)
1049 sh2_write8_dramN(1);
1052 #define sh2_write16_dramN(n) \
1053 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1054 if (!(a & 0x20000)) { \
1059 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1060 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1063 static void m68k_write16_dram0_ow(u32 a, u32 d)
1065 sh2_write16_dramN(0);
1068 static void m68k_write16_dram1_ow(u32 a, u32 d)
1070 sh2_write16_dramN(1);
1073 // -----------------------------------------------------------------
1075 // hint vector is writeable
1076 static void PicoWrite8_hint(u32 a, u32 d)
1078 if ((a & 0xfffc) == 0x0070) {
1079 Pico32xMem->m68k_rom[a ^ 1] = d;
1083 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
1084 a, d & 0xff, SekPc);
1087 static void PicoWrite16_hint(u32 a, u32 d)
1089 if ((a & 0xfffc) == 0x0070) {
1090 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1094 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
1095 a, d & 0xffff, SekPc);
1098 // normally not writable, but somebody could make a RAM cart
1099 static void PicoWrite8_cart(u32 a, u32 d)
1101 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1107 static void PicoWrite16_cart(u32 a, u32 d)
1109 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1115 // same with bank, but save ram is sometimes here
1116 static u32 PicoRead8_bank(u32 a)
1118 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1119 return m68k_read8(a);
1122 static u32 PicoRead16_bank(u32 a)
1124 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1125 return m68k_read16(a);
1128 static void PicoWrite8_bank(u32 a, u32 d)
1130 if (!(Pico.m.sram_reg & SRR_MAPPED))
1131 elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
1132 a, d & 0xff, SekPc);
1134 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1138 static void PicoWrite16_bank(u32 a, u32 d)
1140 if (!(Pico.m.sram_reg & SRR_MAPPED))
1141 elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
1142 a, d & 0xffff, SekPc);
1144 a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
1148 static void bank_map_handler(void)
1150 cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
1151 cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
1154 static void bank_switch(int b)
1156 unsigned int rs, bank;
1158 if (Pico.m.ncart_in)
1162 if ((Pico.m.sram_reg & SRR_MAPPED) && bank == SRam.start) {
1167 if (bank >= Pico.romsize) {
1168 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1173 // 32X ROM (unbanked, XXX: consider mirroring?)
1174 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1178 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1179 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1181 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1184 // setup FAME fetchmap
1185 for (rs = 0x90; rs < 0xa0; rs++)
1186 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
1190 // -----------------------------------------------------------------
1192 // -----------------------------------------------------------------
1195 static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
1197 elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
1202 static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
1206 sh2_burn_cycles(sh2, 1*2);
1208 // 0x3ffc0 is veridied
1209 if ((a & 0x3ffc0) == 0x4000) {
1210 d = p32x_sh2reg_read16(a, sh2);
1214 if ((a & 0x3fff0) == 0x4100) {
1215 d = p32x_vdp_read16(a);
1216 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1221 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1222 return Pico32xMem->sh2_rom_m.b[a ^ 1];
1223 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1224 return Pico32xMem->sh2_rom_s.b[a ^ 1];
1226 if ((a & 0x3fe00) == 0x4200) {
1227 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1231 return sh2_read8_unmapped(a, sh2);
1239 elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
1244 static u32 sh2_read8_da(u32 a, SH2 *sh2)
1246 return sh2->data_array[(a & 0xfff) ^ 1];
1250 static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
1252 elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
1257 static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
1261 sh2_burn_cycles(sh2, 1*2);
1263 if ((a & 0x3ffc0) == 0x4000) {
1264 d = p32x_sh2reg_read16(a, sh2);
1265 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1270 if ((a & 0x3fff0) == 0x4100) {
1271 d = p32x_vdp_read16(a);
1272 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1276 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1277 return Pico32xMem->sh2_rom_m.w[a / 2];
1278 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1279 return Pico32xMem->sh2_rom_s.w[a / 2];
1281 if ((a & 0x3fe00) == 0x4200) {
1282 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1286 return sh2_read16_unmapped(a, sh2);
1289 elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
1294 static u32 sh2_read16_da(u32 a, SH2 *sh2)
1296 return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
1300 static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
1305 static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
1307 elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
1308 a, d & 0xff, sh2_pc(sh2));
1311 static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
1313 elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
1314 a, d & 0xff, sh2_pc(sh2));
1316 if (Pico32x.regs[0] & P32XS_FM) {
1317 if ((a & 0x3fff0) == 0x4100) {
1319 p32x_vdp_write8(a, d);
1324 if ((a & 0x3ffc0) == 0x4000) {
1325 p32x_sh2reg_write8(a, d, sh2);
1329 sh2_write8_unmapped(a, d, sh2);
1332 static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
1334 sh2_write8_dramN(0);
1337 static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
1339 sh2_write8_dramN(1);
1342 static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
1344 u32 a1 = a & 0x3ffff;
1346 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1348 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1350 Pico32xMem->sdram[a1 ^ 1] = d;
1353 static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
1357 sh2_end_run(sh2, 32);
1359 sh2_write8_sdram(a, d, sh2);
1362 static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
1366 int id = sh2->is_slave;
1367 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1369 sh2_drc_wcheck_da(a, t, id);
1371 sh2->data_array[a1 ^ 1] = d;
1375 static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
1377 elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
1378 a, d & 0xffff, sh2_pc(sh2));
1381 static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
1383 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1384 elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
1385 a, d & 0xffff, sh2_pc(sh2));
1387 if (Pico32x.regs[0] & P32XS_FM) {
1388 if ((a & 0x3fff0) == 0x4100) {
1390 p32x_vdp_write16(a, d, sh2);
1394 if ((a & 0x3fe00) == 0x4200) {
1395 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1396 Pico32x.dirty_pal = 1;
1401 if ((a & 0x3ffc0) == 0x4000) {
1402 p32x_sh2reg_write16(a, d, sh2);
1406 sh2_write16_unmapped(a, d, sh2);
1409 static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
1411 sh2_write16_dramN(0);
1414 static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
1416 sh2_write16_dramN(1);
1419 static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
1421 u32 a1 = a & 0x3ffff;
1423 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1425 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1427 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1430 static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
1434 int id = sh2->is_slave;
1435 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1437 sh2_drc_wcheck_da(a, t, id);
1439 ((u16 *)sh2->data_array)[a1 / 2] = d;
1443 typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
1444 typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
1446 #define SH2MAP_ADDR2OFFS_R(a) \
1447 ((u32)(a) >> SH2_READ_SHIFT)
1449 #define SH2MAP_ADDR2OFFS_W(a) \
1450 ((u32)(a) >> SH2_WRITE_SHIFT)
1452 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1454 const sh2_memmap *sh2_map = sh2->read8_map;
1457 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1459 if (map_flag_set(p))
1460 return ((sh2_read_handler *)(p << 1))(a, sh2);
1462 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1465 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1467 const sh2_memmap *sh2_map = sh2->read16_map;
1470 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1472 if (map_flag_set(p))
1473 return ((sh2_read_handler *)(p << 1))(a, sh2);
1475 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1478 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1480 const sh2_memmap *sh2_map = sh2->read16_map;
1481 sh2_read_handler *handler;
1485 offs = SH2MAP_ADDR2OFFS_R(a);
1488 if (!map_flag_set(p)) {
1489 // XXX: maybe 32bit access instead with ror?
1490 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1491 return (pd[0] << 16) | pd[1];
1494 if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
1495 return sh2_peripheral_read32(a, sh2);
1497 handler = (sh2_read_handler *)(p << 1);
1498 return (handler(a, sh2) << 16) | handler(a + 2, sh2);
1501 void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1503 const void **sh2_wmap = sh2->write8_tab;
1504 sh2_write_handler *wh;
1506 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1510 void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1512 const void **sh2_wmap = sh2->write16_tab;
1513 sh2_write_handler *wh;
1515 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1519 void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1521 const void **sh2_wmap = sh2->write16_tab;
1522 sh2_write_handler *wh;
1525 offs = SH2MAP_ADDR2OFFS_W(a);
1527 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1528 sh2_peripheral_write32(a, d, sh2);
1532 wh = sh2_wmap[offs];
1533 wh(a, d >> 16, sh2);
1537 // -----------------------------------------------------------------
1539 static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
1541 unsigned int addr68k;
1543 addr68k = Pico.m.z80_bank68k << 15;
1544 addr68k += a & 0x7fff;
1545 if ((addr68k & 0xfff000) == 0xa15000)
1546 Pico32x.emu_flags |= P32XF_Z80_32X_IO;
1548 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
1549 m68k_write8(addr68k, d);
1552 // -----------------------------------------------------------------
1554 static const u16 msh2_code[] = {
1555 // trap instructions
1556 0xaffe, // 200 bra <self>
1558 // have to wait a bit until m68k initial program finishes clearing stuff
1559 // to avoid races with game SH2 code, like in Tempo
1560 0xd406, // 204 mov.l @(_m_ok,pc), r4
1561 0xc400, // 206 mov.b @(h'0,gbr),r0
1562 0xc801, // 208 tst #1, r0
1563 0x8b0f, // 20a bf cd_start
1564 0xd105, // 20c mov.l @(_cnt,pc), r1
1565 0xd206, // 20e mov.l @(_start,pc), r2
1566 0x71ff, // 210 add #-1, r1
1567 0x4115, // 212 cmp/pl r1
1568 0x89fc, // 214 bt -2
1569 0x6043, // 216 mov r4, r0
1570 0xc208, // 218 mov.l r0, @(h'20,gbr)
1571 0x6822, // 21a mov.l @r2, r8
1572 0x482b, // 21c jmp @r8
1574 ('M'<<8)|'_', ('O'<<8)|'K', // 220 _m_ok
1575 0x0001, 0x0000, // 224 _cnt
1576 0x2200, 0x03e0, // master start pointer in ROM
1578 0xd20d, // 22c mov.l @(__cd_,pc), r2
1579 0xc608, // 22e mov.l @(h'20,gbr), r0
1580 0x3200, // 230 cmp/eq r0, r2
1581 0x8bfc, // 232 bf #-2
1582 0xe000, // 234 mov #0, r0
1583 0xcf80, // 236 or.b #0x80,@(r0,gbr)
1584 0xd80b, // 238 mov.l @(_start_cd,pc), r8 // 24000018
1585 0xd30c, // 23a mov.l @(_max_len,pc), r3
1586 0x5b84, // 23c mov.l @(h'10,r8), r11 // master vbr
1587 0x5a82, // 23e mov.l @(8,r8), r10 // entry
1588 0x5081, // 240 mov.l @(4,r8), r0 // len
1589 0x5980, // 242 mov.l @(0,r8), r9 // dst
1590 0x3036, // 244 cmp/hi r3,r0
1591 0x8b00, // 246 bf #1
1592 0x6033, // 248 mov r3,r0
1593 0x7820, // 24a add #0x20, r8
1595 0x6286, // 24c mov.l @r8+, r2
1596 0x2922, // 24e mov.l r2, @r9
1597 0x7904, // 250 add #4, r9
1598 0x70fc, // 252 add #-4, r0
1599 0x8800, // 254 cmp/eq #0, r0
1600 0x8bf9, // 256 bf #-5
1602 0x4b2e, // 258 ldc r11, vbr
1603 0x6043, // 25a mov r4, r0 // M_OK
1604 0xc208, // 25c mov.l r0, @(h'20,gbr)
1605 0x4a2b, // 25e jmp @r10
1607 0x0009, // 262 nop // pad
1608 ('_'<<8)|'C', ('D'<<8)|'_', // 264 __cd_
1609 0x2400, 0x0018, // 268 _start_cd
1610 0x0001, 0xffe0, // 26c _max_len
1613 static const u16 ssh2_code[] = {
1614 0xaffe, // 200 bra <self>
1616 // code to wait for master, in case authentic master BIOS is used
1617 0xd106, // 204 mov.l @(_m_ok,pc), r1
1618 0xd208, // 206 mov.l @(_start,pc), r2
1619 0xc608, // 208 mov.l @(h'20,gbr), r0
1620 0x3100, // 20a cmp/eq r0, r1
1621 0x8bfc, // 20c bf #-2
1622 0xc400, // 20e mov.b @(h'0,gbr),r0
1623 0xc801, // 210 tst #1, r0
1624 0xd004, // 212 mov.l @(_s_ok,pc), r0
1625 0x8b0a, // 214 bf cd_start
1626 0xc209, // 216 mov.l r0, @(h'24,gbr)
1627 0x6822, // 218 mov.l @r2, r8
1628 0x482b, // 21a jmp @r8
1631 ('M'<<8)|'_', ('O'<<8)|'K', // 220
1632 ('S'<<8)|'_', ('O'<<8)|'K', // 224
1633 0x2200, 0x03e4, // slave start pointer in ROM
1635 0xd803, // 22c mov.l @(_start_cd,pc), r8 // 24000018
1636 0x5b85, // 22e mov.l @(h'14,r8), r11 // slave vbr
1637 0x5a83, // 230 mov.l @(h'0c,r8), r10 // entry
1638 0x4b2e, // 232 ldc r11, vbr
1639 0xc209, // 234 mov.l r0, @(h'24,gbr) // write S_OK
1640 0x4a2b, // 236 jmp @r10
1643 0x2400, 0x0018, // 23c _start_cd
1646 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1647 static void get_bios(void)
1654 if (p32x_bios_g != NULL) {
1655 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1656 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1660 ps = (u16 *)Pico32xMem->m68k_rom;
1662 for (i = 1; i < 0xc0/4; i++)
1663 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1666 for (i = 0xc0/2; i < 0x100/2; i++)
1670 ps[0xc0/2] = 0x46fc;
1671 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1672 ps[0xfe/2] = 0x60fe; // jump to self
1674 ps[0xfe/2] = 0x4e75; // rts
1677 // fill remaining m68k_rom page with game ROM
1678 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1679 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1680 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1683 if (p32x_bios_m != NULL) {
1684 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1685 Byteswap(&Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1688 pl = (u32 *)&Pico32xMem->sh2_rom_m;
1690 // fill exception vector table to our trap address
1691 for (i = 0; i < 128; i++)
1692 pl[i] = HWSWAP(0x200);
1695 pl[0] = pl[2] = HWSWAP(0x204);
1697 pl[1] = pl[3] = HWSWAP(0x6040000);
1700 memcpy(&Pico32xMem->sh2_rom_m.b[0x200], msh2_code, sizeof(msh2_code));
1704 if (p32x_bios_s != NULL) {
1705 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1706 Byteswap(&Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1709 pl = (u32 *)&Pico32xMem->sh2_rom_s;
1711 // fill exception vector table to our trap address
1712 for (i = 0; i < 128; i++)
1713 pl[i] = HWSWAP(0x200);
1716 pl[0] = pl[2] = HWSWAP(0x204);
1718 pl[1] = pl[3] = HWSWAP(0x603f800);
1721 memcpy(&Pico32xMem->sh2_rom_s.b[0x200], ssh2_code, sizeof(ssh2_code));
1725 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1726 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1728 static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
1729 // for writes we are using handlers only
1730 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1732 void Pico32xSwapDRAM(int b)
1734 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1735 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1736 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1737 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1738 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1739 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1740 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1741 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1744 sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
1745 sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1747 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1748 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1751 void PicoMemSetup32x(void)
1756 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1757 if (Pico32xMem == NULL) {
1758 elprintf(EL_STATUS, "OOM");
1764 // cartridge area becomes unmapped
1765 // XXX: we take the easy way and don't unmap ROM,
1766 // so that we can avoid handling the RV bit.
1767 // m68k_map_unmap(0x000000, 0x3fffff);
1769 if (!Pico.m.ncart_in) {
1771 rs = sizeof(Pico32xMem->m68k_rom_bank);
1772 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1773 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1774 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1775 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1777 // 32X ROM (unbanked, XXX: consider mirroring?)
1778 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1781 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1782 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1783 cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
1784 cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
1786 // setup FAME fetchmap
1787 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1788 for (rs = 0x88; rs < 0x90; rs++)
1789 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1794 cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
1795 cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
1799 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1800 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1801 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1802 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1804 // SH2 maps: A31,A30,A29,CS1,CS0
1805 // all unmapped by default
1806 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1807 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1808 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1811 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1812 sh2_write8_map[i] = sh2_write8_unmapped;
1813 sh2_write16_map[i] = sh2_write16_unmapped;
1817 for (i = 0x40; i <= 0x5f; i++) {
1818 sh2_write8_map[i >> 1] =
1819 sh2_write16_map[i >> 1] = sh2_write_ignore;
1823 sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
1824 sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
1825 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1826 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1828 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
1829 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
1830 sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
1831 sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
1832 // CS2 - DRAM - done by Pico32xSwapDRAM()
1833 sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
1834 sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
1836 sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
1837 sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
1838 sh2_write8_map[0x06/2] = sh2_write8_sdram;
1839 sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
1840 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1841 sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
1842 sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
1844 sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
1845 sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
1846 sh2_write8_map[0xc0/2] = sh2_write8_da;
1847 sh2_write16_map[0xc0/2] = sh2_write16_da;
1849 sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
1850 sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
1851 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1852 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1854 // map DRAM area, both 68k and SH2
1857 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1858 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1859 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1860 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1862 sh2_drc_mem_setup(&msh2);
1863 sh2_drc_mem_setup(&ssh2);
1866 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
1869 void Pico32xMemStateLoaded(void)
1871 bank_switch(Pico32x.regs[4 / 2]);
1872 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1873 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1874 Pico32x.dirty_pal = 1;
1876 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1877 memset(&m68k_poll, 0, sizeof(m68k_poll));
1879 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1881 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1883 sh2_drc_flush_all();
1886 // vim:shiftwidth=2:ts=2:expandtab