3 * iii. .cc. ..xx * // Internal, Cs, x
6 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
7 * a15102 ........ ......SM ? 4002 // intS intM
8 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
9 * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
10 * a15108 (32bit DREQ src) 4008
11 * a1510c (32bit DREQ dst) 400c
12 * a15110 llllllll llllll00 4010 // DREQ Len
13 * a15112 (16bit FIFO reg) 4012
14 * a15114 ? (16bit VRES clr) 4014
15 * a15116 ? (16bit Vint clr) 4016
16 * a15118 ? (16bit Hint clr) 4018
17 * a1511a ........ .......C (16bit CMD clr) 401a // Cm
18 * a1511c ? (16bit PWM clr) 401c
20 * a15120 (16 bytes comm) 2020
23 #include "../pico_int.h"
24 #include "../memory.h"
26 #include "../../cpu/sh2/compiler.h"
32 #define ash2_end_run(x)
36 static const char str_mars[] = "MARS";
38 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
39 struct Pico32xMem *Pico32xMem;
41 static void bank_switch(int b);
44 #define POLL_THRESHOLD 6
47 u32 addr, cycles, cyc_max;
50 static struct poll_det m68k_poll, sh2_poll[2];
52 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
54 int ret = 0, flag = pd->flag;
59 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
61 if (pd->cnt > POLL_THRESHOLD) {
62 if (!(Pico32x.emu_flags & flag)) {
63 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
64 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
65 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
68 Pico32x.emu_flags |= flag;
80 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
82 int ret = 0, flag = pd->flag;
84 flag <<= 3; // VDP only
86 flag |= flag << 3; // both
87 if (Pico32x.emu_flags & flag) {
88 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
91 Pico32x.emu_flags &= ~flag;
92 pd->addr = pd->cnt = 0;
96 void p32x_poll_event(int cpu_mask, int is_vdp)
99 p32x_poll_undetect(&sh2_poll[0], is_vdp);
101 p32x_poll_undetect(&sh2_poll[1], is_vdp);
108 static const u16 comm_fakevals[] = {
109 0x4d5f, 0x4f4b, // M_OK
110 0x535f, 0x4f4b, // S_OK
111 0x4D41, 0x5346, // MASF - Brutal Unleashed
112 0x5331, 0x4d31, // Darxide
115 0x0000, 0x0000, // eq for doom
116 0x0002, // Mortal Kombat
120 static u32 sh2_comm_faker(u32 a)
123 if (a == 0x28 && !p32x_csum_faked) {
125 return *(unsigned short *)(Pico.rom + 0x18e);
127 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
129 return comm_fakevals[f++];
135 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
136 unsigned int chcr0; // chan ctl
137 unsigned int sar1, dar1, tcr1; // same for chan 1
143 static void dma_68k2sh2_do(void)
145 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
148 if (dmac0->tcr0 != *dreqlen)
149 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
151 // HACK: assume bus is busy and SH2 is halted
152 // XXX: use different mechanism for this, not poll det
153 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
155 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
156 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
157 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], &msh2);
163 Pico32x.dmac_ptr = 0; // HACK
164 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
166 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
167 if (dmac0->tcr0 == 0) {
168 dmac0->chcr0 |= 2; // DMA has ended normally
169 p32x_poll_undetect(&sh2_poll[0], 0);
173 // ------------------------------------------------------------------
176 static u32 p32x_reg_read16(u32 a)
180 if (a == 2) // INTM, INTS
181 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
183 if ((a & 0x30) == 0x20)
184 return sh2_comm_faker(a);
186 if ((a & 0x30) == 0x20) {
187 // evil X-Men proto polls in a dbra loop and expects it to expire..
189 if (SekDar(2) != dr2)
193 if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
201 if ((a & 0x30) == 0x30)
202 return p32x_pwm_read16(a);
204 return Pico32x.regs[a / 2];
207 static void p32x_reg_write8(u32 a, u32 d)
209 u16 *r = Pico32x.regs;
212 // for things like bset on comm port
216 case 0: // adapter ctl
217 r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
219 case 1: // adapter ctl, RES bit writeable
220 if ((d ^ r[0]) & d & P32XS_nRES)
222 r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
225 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
226 Pico32x.sh2irqi[0] |= P32XI_CMD;
230 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
231 Pico32x.sh2irqi[1] |= P32XI_CMD;
244 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
251 if ((a & 0x30) == 0x20) {
254 p32x_poll_undetect(&sh2_poll[0], 0);
255 p32x_poll_undetect(&sh2_poll[1], 0);
256 // if some SH2 is busy waiting, it needs to see the result ASAP
257 if (SekCyclesLeftNoMCD > 32)
263 static void p32x_reg_write16(u32 a, u32 d)
265 u16 *r = Pico32x.regs;
268 // for things like bset on comm port
272 case 0x00: // adapter ctl
273 if ((d ^ r[0]) & d & P32XS_nRES)
275 r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
277 case 0x10: // DREQ len
280 case 0x12: // FIFO reg
281 if (!(r[6 / 2] & P32XS_68S)) {
282 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
285 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
286 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
287 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
289 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
290 r[6 / 2] |= P32XS_FULL;
296 if ((a & 0x38) == 0x08) {
301 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
303 p32x_poll_undetect(&sh2_poll[0], 0);
304 p32x_poll_undetect(&sh2_poll[1], 0);
306 if (SekCyclesLeftNoMCD > 32)
311 else if ((a & 0x30) == 0x30) {
312 p32x_pwm_write16(a, d);
316 p32x_reg_write8(a + 1, d);
319 // ------------------------------------------------------------------
321 static u32 p32x_vdp_read16(u32 a)
325 return Pico32x.vdp_regs[a / 2];
328 static void p32x_vdp_write8(u32 a, u32 d)
330 u16 *r = Pico32x.vdp_regs;
333 // for FEN checks between writes
336 // TODO: verify what's writeable
339 // priority inversion is handled in palette
340 if ((r[0] ^ d) & P32XV_PRI)
341 Pico32x.dirty_pal = 1;
342 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
344 case 0x05: // fill len
349 Pico32x.pending_fb = d;
350 // if we are blanking and FS bit is changing
351 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
353 Pico32xSwapDRAM(d ^ 1);
354 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
360 static void p32x_vdp_write16(u32 a, u32 d)
363 if (a == 6) { // fill start
364 Pico32x.vdp_regs[6 / 2] = d;
367 if (a == 8) { // fill data
368 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
369 int len = Pico32x.vdp_regs[4 / 2] + 1;
370 a = Pico32x.vdp_regs[6 / 2];
373 a = (a & 0xff00) | ((a + 1) & 0xff);
375 Pico32x.vdp_regs[6 / 2] = a;
376 Pico32x.vdp_regs[8 / 2] = d;
380 p32x_vdp_write8(a | 1, d);
383 // ------------------------------------------------------------------
386 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
388 u16 *r = Pico32x.regs;
392 case 0x00: // adapter/irq ctl
393 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
394 case 0x04: // H count (often as comm too)
395 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
397 return Pico32x.sh2_regs[4 / 2];
398 case 0x10: // DREQ len
403 if ((a & 0x38) == 0x08)
406 if ((a & 0x30) == 0x20) {
407 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
411 if ((a & 0x30) == 0x30) {
412 sh2_poll[cpuid].cnt = 0;
413 return p32x_pwm_read16(a);
419 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
424 Pico32x.regs[0] &= ~P32XS_FM;
425 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
428 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
429 Pico32x.sh2_regs[0] &= ~0x80;
430 Pico32x.sh2_regs[0] |= d & 0x80;
434 Pico32x.sh2_regs[4 / 2] = d & 0xff;
435 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
439 if ((a & 0x30) == 0x20) {
440 u8 *r8 = (u8 *)Pico32x.regs;
442 if (p32x_poll_undetect(&m68k_poll, 0))
444 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
449 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
454 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
455 Pico32x.regs[a / 2] = d;
456 if (p32x_poll_undetect(&m68k_poll, 0))
458 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
462 else if ((a & 0x30) == 0x30) {
463 p32x_pwm_write16(a, d);
469 Pico32x.regs[0] &= ~P32XS_FM;
470 Pico32x.regs[0] |= d & P32XS_FM;
472 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
473 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
474 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
475 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
477 Pico32x.sh2irqs &= ~P32XI_PWM;
482 p32x_sh2reg_write8(a | 1, d, cpuid);
489 // ------------------------------------------------------------------
490 // SH2 internal peripherals
491 // we keep them in little endian format
492 static u32 sh2_peripheral_read8(u32 a, int id)
494 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
500 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
504 static u32 sh2_peripheral_read16(u32 a, int id)
506 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
512 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
516 static u32 sh2_peripheral_read32(u32 a, int id)
520 d = Pico32xMem->sh2_peri_regs[id][a / 4];
522 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
526 static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
528 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
529 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
535 if ((a == 2 && (d & 0x20)) || // transmiter enabled
536 (a == 4 && !(d & 0x80))) { // valid data in TDR
537 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
538 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
539 int level = PREG8(oregs, 0x60) >> 4;
540 int vector = PREG8(oregs, 0x63) & 0x7f;
541 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
542 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
549 static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
551 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
552 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
558 if ((d & 0xff00) == 0xa500) { // WTCSR
560 p32x_timers_recalc();
562 if ((d & 0xff00) == 0x5a00) // WTCNT
571 static void sh2_peripheral_write32(u32 a, u32 d, int id)
573 u32 *r = Pico32xMem->sh2_peri_regs[id];
574 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
580 // division unit (TODO: verify):
581 case 0x104: // DVDNT: divident L, starts divide
582 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
584 signed int divisor = r[0x100 / 4];
585 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
586 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
589 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
592 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
593 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
595 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
596 signed int divisor = r[0x100 / 4];
597 // XXX: undocumented mirroring to 0x118,0x11c?
598 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
600 r[0x11c / 4] = r[0x114 / 4] = divident;
602 if ((unsigned long long)divident + 1 > 1) {
603 //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
604 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
608 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
612 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
613 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
614 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
615 dmac0->tcr0 &= 0xffffff;
617 // HACK: assume 68k starts writing soon and end the timeslice
620 // DREQ is only sent after first 4 words are written.
621 // we do multiple of 4 words to avoid messing up alignment
622 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
623 elprintf(EL_32X, "68k -> sh2 DMA");
629 // ------------------------------------------------------------------
633 static u32 PicoRead8_32x_on(u32 a)
636 if ((a & 0xffc0) == 0x5100) { // a15100
637 d = p32x_reg_read16(a);
641 if ((a & 0xfc00) != 0x5000)
642 return PicoRead8_io(a);
644 if ((a & 0xfff0) == 0x5180) { // a15180
645 d = p32x_vdp_read16(a);
649 if ((a & 0xfe00) == 0x5200) { // a15200
650 d = Pico32xMem->pal[(a & 0x1ff) / 2];
654 if ((a & 0xfffc) == 0x30ec) { // a130ec
659 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
669 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
673 static u32 PicoRead16_32x_on(u32 a)
676 if ((a & 0xffc0) == 0x5100) { // a15100
677 d = p32x_reg_read16(a);
681 if ((a & 0xfc00) != 0x5000)
682 return PicoRead16_io(a);
684 if ((a & 0xfff0) == 0x5180) { // a15180
685 d = p32x_vdp_read16(a);
689 if ((a & 0xfe00) == 0x5200) { // a15200
690 d = Pico32xMem->pal[(a & 0x1ff) / 2];
694 if ((a & 0xfffc) == 0x30ec) { // a130ec
695 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
699 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
703 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
707 static void PicoWrite8_32x_on(u32 a, u32 d)
709 if ((a & 0xfc00) == 0x5000)
710 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
712 if ((a & 0xffc0) == 0x5100) { // a15100
713 p32x_reg_write8(a, d);
717 if ((a & 0xfc00) != 0x5000) {
722 if ((a & 0xfff0) == 0x5180) { // a15180
723 p32x_vdp_write8(a, d);
728 if ((a & 0xfe00) == 0x5200) { // a15200
729 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
730 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
731 Pico32x.dirty_pal = 1;
735 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
738 static void PicoWrite16_32x_on(u32 a, u32 d)
740 if ((a & 0xfc00) == 0x5000)
741 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
743 if ((a & 0xffc0) == 0x5100) { // a15100
744 p32x_reg_write16(a, d);
748 if ((a & 0xfc00) != 0x5000) {
749 PicoWrite16_io(a, d);
753 if ((a & 0xfff0) == 0x5180) { // a15180
754 p32x_vdp_write16(a, d);
758 if ((a & 0xfe00) == 0x5200) { // a15200
759 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
760 Pico32x.dirty_pal = 1;
764 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
768 u32 PicoRead8_32x(u32 a)
771 if ((a & 0xffc0) == 0x5100) { // a15100
772 // regs are always readable
773 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
777 if ((a & 0xfffc) == 0x30ec) { // a130ec
782 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
786 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
790 u32 PicoRead16_32x(u32 a)
793 if ((a & 0xffc0) == 0x5100) { // a15100
794 d = Pico32x.regs[(a & 0x3f) / 2];
798 if ((a & 0xfffc) == 0x30ec) { // a130ec
799 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
803 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
807 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
811 void PicoWrite8_32x(u32 a, u32 d)
813 if ((a & 0xffc0) == 0x5100) { // a15100
814 u16 *r = Pico32x.regs;
816 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
819 if ((d ^ r[0]) & d & P32XS_ADEN) {
821 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
823 p32x_reg_write8(a, d); // forward for reset processing
828 // allow only COMM for now
829 if ((a & 0x30) == 0x20) {
836 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
839 void PicoWrite16_32x(u32 a, u32 d)
841 if ((a & 0xffc0) == 0x5100) { // a15100
842 u16 *r = Pico32x.regs;
844 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
847 if ((d ^ r[0]) & d & P32XS_ADEN) {
849 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
851 p32x_reg_write16(a, d); // forward for reset processing
856 // allow only COMM for now
857 if ((a & 0x30) == 0x20)
862 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
865 // -----------------------------------------------------------------
867 // hint vector is writeable
868 static void PicoWrite8_hint(u32 a, u32 d)
870 if ((a & 0xfffc) == 0x0070) {
871 Pico32xMem->m68k_rom[a ^ 1] = d;
875 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
878 static void PicoWrite16_hint(u32 a, u32 d)
880 if ((a & 0xfffc) == 0x0070) {
881 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
885 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
888 static void bank_switch(int b)
890 unsigned int rs, bank;
893 if (bank >= Pico.romsize) {
894 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
898 // 32X ROM (unbanked, XXX: consider mirroring?)
899 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
903 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
904 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
906 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
909 // setup FAME fetchmap
910 for (rs = 0x90; rs < 0xa0; rs++)
911 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom + bank - 0x900000;
915 // -----------------------------------------------------------------
917 // -----------------------------------------------------------------
920 static u32 sh2_read8_unmapped(u32 a, int id)
922 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
923 id ? 's' : 'm', a, 0, sh2_pc(id));
927 static u32 sh2_read8_cs0(u32 a, int id)
931 // 0x3ff00 is veridied
932 if ((a & 0x3ff00) == 0x4000) {
933 d = p32x_sh2reg_read16(a, id);
937 if ((a & 0x3ff00) == 0x4100) {
938 d = p32x_vdp_read16(a);
939 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
945 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
946 return Pico32xMem->sh2_rom_m[a ^ 1];
947 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
948 return Pico32xMem->sh2_rom_s[a ^ 1];
950 if ((a & 0x3ff00) == 0x4200) {
951 d = Pico32xMem->pal[(a & 0x1ff) / 2];
955 return sh2_read8_unmapped(a, id);
963 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
964 id ? 's' : 'm', a, d, sh2_pc(id));
968 static u32 sh2_read8_da(u32 a, int id)
970 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
974 static u32 sh2_read16_unmapped(u32 a, int id)
976 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
977 id ? 's' : 'm', a, 0, sh2_pc(id));
981 static u32 sh2_read16_cs0(u32 a, int id)
985 if ((a & 0x3ff00) == 0x4000) {
986 d = p32x_sh2reg_read16(a, id);
987 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
992 if ((a & 0x3ff00) == 0x4100) {
993 d = p32x_vdp_read16(a);
994 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
999 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
1000 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1001 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
1002 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1004 if ((a & 0x3ff00) == 0x4200) {
1005 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1009 return sh2_read16_unmapped(a, id);
1012 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
1013 id ? 's' : 'm', a, d, sh2_pc(id));
1017 static u32 sh2_read16_da(u32 a, int id)
1019 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
1022 static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
1028 static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
1030 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
1031 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1035 static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
1037 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
1038 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
1040 if ((a & 0x3ff00) == 0x4100) {
1041 p32x_vdp_write8(a, d);
1045 if ((a & 0x3ff00) == 0x4000) {
1046 p32x_sh2reg_write8(a, d, id);
1050 return sh2_write8_unmapped(a, d, id);
1053 #define sh2_write8_dramN(n) \
1054 if (!(a & 0x20000) || d) { \
1055 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
1056 dram[(a & 0x1ffff) ^ 1] = d; \
1060 static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
1062 sh2_write8_dramN(0);
1065 static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
1067 sh2_write8_dramN(1);
1070 static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
1072 u32 a1 = a & 0x3ffff;
1074 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1076 sh2_drc_wcheck_ram(a, t, id);
1078 Pico32xMem->sdram[a1 ^ 1] = d;
1082 static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
1086 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1088 sh2_drc_wcheck_da(a, t, id);
1090 Pico32xMem->data_array[id][a1 ^ 1] = d;
1095 static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
1097 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1098 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1102 static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
1104 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1105 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
1106 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1108 if ((a & 0x3ff00) == 0x4100) {
1109 sh2_poll[id].cnt = 0; // for poll before VDP accesses
1110 p32x_vdp_write16(a, d);
1114 if ((a & 0x3fe00) == 0x4200) {
1115 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1116 Pico32x.dirty_pal = 1;
1120 if ((a & 0x3ff00) == 0x4000) {
1121 p32x_sh2reg_write16(a, d, id);
1125 return sh2_write16_unmapped(a, d, id);
1128 #define sh2_write16_dramN(n) \
1129 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
1130 if (!(a & 0x20000)) { \
1135 if (!(d & 0xff00)) d |= *pd & 0xff00; \
1136 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
1140 static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
1142 sh2_write16_dramN(0);
1145 static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
1147 sh2_write16_dramN(1);
1150 static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
1152 u32 a1 = a & 0x3ffff;
1154 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1156 sh2_drc_wcheck_ram(a, t, id);
1158 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1162 static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
1166 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1168 sh2_drc_wcheck_da(a, t, id);
1170 ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
1176 uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
1180 typedef u32 (sh2_read_handler)(u32 a, int id);
1181 typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
1183 #define SH2MAP_ADDR2OFFS_R(a) \
1184 ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
1186 #define SH2MAP_ADDR2OFFS_W(a) \
1187 ((u32)(a) >> SH2_WRITE_SHIFT)
1189 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1191 const sh2_memmap *sh2_map = sh2->read8_map;
1194 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1196 if (map_flag_set(p))
1197 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1199 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1202 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1204 const sh2_memmap *sh2_map = sh2->read16_map;
1207 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1209 if (map_flag_set(p))
1210 return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
1212 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1215 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1217 const sh2_memmap *sh2_map = sh2->read16_map;
1218 sh2_read_handler *handler;
1222 offs = SH2MAP_ADDR2OFFS_R(a);
1225 if (!map_flag_set(p)) {
1226 // XXX: maybe 32bit access instead with ror?
1227 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1228 return (pd[0] << 16) | pd[1];
1232 return sh2_peripheral_read32(a, sh2->is_slave);
1234 handler = (sh2_read_handler *)(p << 1);
1235 return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
1238 // return nonzero if write potentially causes an interrupt (used by drc)
1239 int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1241 const void **sh2_wmap = sh2->write8_tab;
1242 sh2_write_handler *wh;
1244 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1245 return wh(a, d, sh2->is_slave);
1248 int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1250 const void **sh2_wmap = sh2->write16_tab;
1251 sh2_write_handler *wh;
1253 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1254 return wh(a, d, sh2->is_slave);
1257 int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1259 const void **sh2_wmap = sh2->write16_tab;
1260 sh2_write_handler *handler;
1263 offs = SH2MAP_ADDR2OFFS_W(a);
1265 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1266 sh2_peripheral_write32(a, d, sh2->is_slave);
1270 handler = sh2_wmap[offs];
1271 handler(a, d >> 16, sh2->is_slave);
1272 handler(a + 2, d, sh2->is_slave);
1276 // -----------------------------------------------------------------
1278 static const u16 msh2_code[] = {
1279 // trap instructions
1280 0xaffe, // bra <self>
1282 // have to wait a bit until m68k initial program finishes clearing stuff
1283 // to avoid races with game SH2 code, like in Tempo
1284 0xd004, // mov.l @(_m_ok,pc), r0
1285 0xd105, // mov.l @(_cnt,pc), r1
1286 0xd205, // mov.l @(_start,pc), r2
1287 0x71ff, // add #-1, r1
1288 0x4115, // cmp/pl r1
1290 0xc208, // mov.l r0, @(h'20,gbr)
1291 0x6822, // mov.l @r2, r8
1294 ('M'<<8)|'_', ('O'<<8)|'K',
1296 0x2200, 0x03e0 // master start pointer in ROM
1299 static const u16 ssh2_code[] = {
1300 0xaffe, // bra <self>
1302 // code to wait for master, in case authentic master BIOS is used
1303 0xd104, // mov.l @(_m_ok,pc), r1
1304 0xd206, // mov.l @(_start,pc), r2
1305 0xc608, // mov.l @(h'20,gbr), r0
1306 0x3100, // cmp/eq r0, r1
1308 0xd003, // mov.l @(_s_ok,pc), r0
1309 0xc209, // mov.l r0, @(h'24,gbr)
1310 0x6822, // mov.l @r2, r8
1313 ('M'<<8)|'_', ('O'<<8)|'K',
1314 ('S'<<8)|'_', ('O'<<8)|'K',
1315 0x2200, 0x03e4 // slave start pointer in ROM
1318 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1319 static void get_bios(void)
1326 if (p32x_bios_g != NULL) {
1327 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1328 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
1332 ps = (u16 *)Pico32xMem->m68k_rom;
1334 for (i = 1; i < 0xc0/4; i++)
1335 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1338 for (i = 0xc0/2; i < 0x100/2; i++)
1342 ps[0xc0/2] = 0x46fc;
1343 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1344 ps[0xfe/2] = 0x60fe; // jump to self
1346 ps[0xfe/2] = 0x4e75; // rts
1349 // fill remaining m68k_rom page with game ROM
1350 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
1353 if (p32x_bios_m != NULL) {
1354 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1355 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1358 pl = (u32 *)Pico32xMem->sh2_rom_m;
1360 // fill exception vector table to our trap address
1361 for (i = 0; i < 128; i++)
1362 pl[i] = HWSWAP(0x200);
1365 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1368 pl[1] = pl[3] = HWSWAP(0x6040000);
1370 pl[0] = pl[2] = HWSWAP(0x204);
1374 if (p32x_bios_s != NULL) {
1375 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1376 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1379 pl = (u32 *)Pico32xMem->sh2_rom_s;
1381 // fill exception vector table to our trap address
1382 for (i = 0; i < 128; i++)
1383 pl[i] = HWSWAP(0x200);
1386 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1389 pl[1] = pl[3] = HWSWAP(0x603f800);
1391 pl[0] = pl[2] = HWSWAP(0x204);
1395 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1396 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1398 static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
1399 // for writes we are using handlers only
1400 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1402 void Pico32xSwapDRAM(int b)
1404 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1405 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1406 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1407 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1410 sh2_read8_map[2].addr = sh2_read8_map[6].addr =
1411 sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1413 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1414 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1417 void PicoMemSetup32x(void)
1422 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem));
1423 if (Pico32xMem == NULL) {
1424 elprintf(EL_STATUS, "OOM");
1428 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1432 // cartridge area becomes unmapped
1433 // XXX: we take the easy way and don't unmap ROM,
1434 // so that we can avoid handling the RV bit.
1435 // m68k_map_unmap(0x000000, 0x3fffff);
1438 rs = sizeof(Pico32xMem->m68k_rom);
1439 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1440 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1441 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1442 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1444 // 32X ROM (unbanked, XXX: consider mirroring?)
1445 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1448 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1449 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1451 // setup FAME fetchmap
1452 PicoCpuFM68k.Fetch[0] = (u32)Pico32xMem->m68k_rom;
1453 for (rs = 0x88; rs < 0x90; rs++)
1454 PicoCpuFM68k.Fetch[rs] = (u32)Pico.rom - 0x880000;
1461 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1462 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1463 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1464 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1466 // SH2 maps: A31,A30,A29,CS1,CS0
1467 // all unmapped by default
1468 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1469 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1470 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1473 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1474 sh2_write8_map[i] = sh2_write8_unmapped;
1475 sh2_write16_map[i] = sh2_write16_unmapped;
1479 for (i = 0x40; i <= 0x5f; i++) {
1480 sh2_write8_map[i >> 1] =
1481 sh2_write16_map[i >> 1] = sh2_write_ignore;
1485 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
1486 sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
1487 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1488 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1490 sh2_read8_map[1].addr = sh2_read8_map[5].addr =
1491 sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
1492 sh2_read8_map[1].mask = sh2_read8_map[5].mask =
1493 sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
1494 // CS2 - DRAM - done by Pico32xSwapDRAM()
1495 sh2_read8_map[2].mask = sh2_read8_map[6].mask =
1496 sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
1498 sh2_read8_map[3].addr = sh2_read8_map[7].addr =
1499 sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
1500 sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
1501 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1502 sh2_read8_map[3].mask = sh2_read8_map[7].mask =
1503 sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
1505 sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
1506 sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
1507 sh2_write8_map[0xc0/2] = sh2_write8_da;
1508 sh2_write16_map[0xc0/2] = sh2_write16_da;
1510 sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
1511 sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
1512 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1513 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1515 // map DRAM area, both 68k and SH2
1518 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1519 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1520 msh2.write8_tab = ssh2.write8_tab = (const void **)sh2_write8_map;
1521 msh2.write16_tab = ssh2.write16_tab = (const void **)sh2_write16_map;
1523 // setup poll detector
1524 m68k_poll.flag = P32XF_68KPOLL;
1525 m68k_poll.cyc_max = 64;
1526 sh2_poll[0].flag = P32XF_MSH2POLL;
1527 sh2_poll[0].cyc_max = 21;
1528 sh2_poll[1].flag = P32XF_SSH2POLL;
1529 sh2_poll[1].cyc_max = 16;
1532 // vim:shiftwidth=2:expandtab