1 #include "../pico_int.h"
7 #define ash2_end_run(x)
11 static const char str_mars[] = "MARS";
13 struct Pico32xMem *Pico32xMem;
15 static void bank_switch(int b);
18 #define POLL_THRESHOLD 6
21 u32 addr, cycles, cyc_max;
24 static struct poll_det m68k_poll, sh2_poll[2];
26 static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
28 int ret = 0, flag = pd->flag;
33 if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
35 if (pd->cnt > POLL_THRESHOLD) {
36 if (!(Pico32x.emu_flags & flag)) {
37 elprintf(EL_32X, "%s poll addr %08x, cyc %u",
38 flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
39 (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
42 Pico32x.emu_flags |= flag;
54 static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
56 int ret = 0, flag = pd->flag;
58 flag <<= 3; // VDP only
60 flag |= flag << 3; // both
61 if (Pico32x.emu_flags & flag) {
62 elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
65 Pico32x.emu_flags &= ~flag;
66 pd->addr = pd->cnt = 0;
70 void p32x_poll_event(int cpu_mask, int is_vdp)
73 p32x_poll_undetect(&sh2_poll[0], is_vdp);
75 p32x_poll_undetect(&sh2_poll[1], is_vdp);
82 static const u16 comm_fakevals[] = {
83 0x4d5f, 0x4f4b, // M_OK
84 0x535f, 0x4f4b, // S_OK
85 0x4D41, 0x5346, // MASF - Brutal Unleashed
86 0x5331, 0x4d31, // Darxide
89 0x0000, 0x0000, // eq for doom
90 0x0002, // Mortal Kombat
94 static u32 sh2_comm_faker(u32 a)
97 if (a == 0x28 && !p32x_csum_faked) {
99 return *(unsigned short *)(Pico.rom + 0x18e);
101 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
103 return comm_fakevals[f++];
109 unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
110 unsigned int chcr0; // chan ctl
111 unsigned int sar1, dar1, tcr1; // same for chan 1
117 static void dma_68k2sh2_do(void)
119 unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
122 if (dmac0->tcr0 != *dreqlen)
123 elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
125 // HACK: assume bus is busy and SH2 is halted
126 // XXX: use different mechanism for this, not poll det
127 Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
129 for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
130 extern void p32x_sh2_write16(u32 a, u32 d, int id);
131 elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
132 p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0);
138 Pico32x.dmac_ptr = 0; // HACK
139 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
141 Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
142 if (dmac0->tcr0 == 0) {
143 dmac0->chcr0 |= 2; // DMA has ended normally
144 p32x_poll_undetect(&sh2_poll[0], 0);
148 // ------------------------------------------------------------------
151 static u32 p32x_reg_read16(u32 a)
155 if (a == 2) // INTM, INTS
156 return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
158 if ((a & 0x30) == 0x20)
159 return sh2_comm_faker(a);
161 if ((a & 0x30) == 0x20) {
162 // evil X-Men proto polls in a dbra loop and expects it to expire..
164 if (SekDar(2) != dr2)
168 if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
176 if ((a & 0x30) == 0x30)
177 return p32x_pwm_read16(a);
179 return Pico32x.regs[a / 2];
182 static void p32x_reg_write8(u32 a, u32 d)
184 u16 *r = Pico32x.regs;
187 // for things like bset on comm port
190 if (a == 1 && !(r[0] & 1)) {
200 case 0: // adapter ctl
201 r[0] = (r[0] & 0x83) | ((d << 8) & P32XS_FM);
204 if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
205 Pico32x.sh2irqi[0] |= P32XI_CMD;
209 if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
210 Pico32x.sh2irqi[1] |= P32XI_CMD;
223 r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
230 if ((a & 0x30) == 0x20) {
233 p32x_poll_undetect(&sh2_poll[0], 0);
234 p32x_poll_undetect(&sh2_poll[1], 0);
235 // if some SH2 is busy waiting, it needs to see the result ASAP
236 if (SekCyclesLeftNoMCD > 32)
242 static void p32x_reg_write16(u32 a, u32 d)
244 u16 *r = Pico32x.regs;
247 // for things like bset on comm port
251 case 0x00: // adapter ctl
252 r[0] = (r[0] & 0x83) | (d & P32XS_FM);
254 case 0x10: // DREQ len
257 case 0x12: // FIFO reg
258 if (!(r[6 / 2] & P32XS_68S)) {
259 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
262 if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
263 Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
264 if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
266 if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
267 r[6 / 2] |= P32XS_FULL;
273 if ((a & 0x38) == 0x08) {
278 else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
280 p32x_poll_undetect(&sh2_poll[0], 0);
281 p32x_poll_undetect(&sh2_poll[1], 0);
283 if (SekCyclesLeftNoMCD > 32)
288 else if ((a & 0x30) == 0x30) {
289 p32x_pwm_write16(a, d);
293 p32x_reg_write8(a + 1, d);
296 // ------------------------------------------------------------------
298 static u32 p32x_vdp_read16(u32 a)
302 return Pico32x.vdp_regs[a / 2];
305 static void p32x_vdp_write8(u32 a, u32 d)
307 u16 *r = Pico32x.vdp_regs;
310 // for FEN checks between writes
313 // TODO: verify what's writeable
316 // priority inversion is handled in palette
317 if ((r[0] ^ d) & P32XV_PRI)
318 Pico32x.dirty_pal = 1;
319 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
321 case 0x05: // fill len
326 Pico32x.pending_fb = d;
327 // if we are blanking and FS bit is changing
328 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
330 Pico32xSwapDRAM(d ^ 1);
331 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
337 static void p32x_vdp_write16(u32 a, u32 d)
340 if (a == 6) { // fill start
341 Pico32x.vdp_regs[6 / 2] = d;
344 if (a == 8) { // fill data
345 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
346 int len = Pico32x.vdp_regs[4 / 2] + 1;
347 a = Pico32x.vdp_regs[6 / 2];
350 a = (a & 0xff00) | ((a + 1) & 0xff);
352 Pico32x.vdp_regs[6 / 2] = a;
353 Pico32x.vdp_regs[8 / 2] = d;
357 p32x_vdp_write8(a | 1, d);
360 // ------------------------------------------------------------------
363 static u32 p32x_sh2reg_read16(u32 a, int cpuid)
365 u16 *r = Pico32x.regs;
369 case 0x00: // adapter/irq ctl
370 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
371 case 0x04: // H count (often as comm too)
372 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
374 return Pico32x.sh2_regs[4 / 2];
375 case 0x10: // DREQ len
380 if ((a & 0x38) == 0x08)
383 if ((a & 0x30) == 0x20) {
384 if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
388 if ((a & 0x30) == 0x30) {
389 sh2_poll[cpuid].cnt = 0;
390 return p32x_pwm_read16(a);
396 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
401 Pico32x.regs[0] &= ~P32XS_FM;
402 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
405 Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
406 Pico32x.sh2_regs[0] &= ~0x80;
407 Pico32x.sh2_regs[0] |= d & 0x80;
411 Pico32x.sh2_regs[4 / 2] = d & 0xff;
412 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
416 if ((a & 0x30) == 0x20) {
417 u8 *r8 = (u8 *)Pico32x.regs;
419 if (p32x_poll_undetect(&m68k_poll, 0))
421 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
426 static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
431 if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
432 Pico32x.regs[a / 2] = d;
433 if (p32x_poll_undetect(&m68k_poll, 0))
435 p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
439 else if ((a & 0x30) == 0x30) {
440 p32x_pwm_write16(a, d);
446 Pico32x.regs[0] &= ~P32XS_FM;
447 Pico32x.regs[0] |= d & P32XS_FM;
449 case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
450 case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
451 case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
452 case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
454 Pico32x.sh2irqs &= ~P32XI_PWM;
459 p32x_sh2reg_write8(a | 1, d, cpuid);
466 // ------------------------------------------------------------------
467 // SH2 internal peripherals
468 // we keep them in little endian format
469 static u32 sh2_peripheral_read8(u32 a, int id)
471 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
477 elprintf(EL_32X, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
481 static u32 sh2_peripheral_read16(u32 a, int id)
483 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
489 elprintf(EL_32X, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
493 static u32 sh2_peripheral_read32(u32 a, int id)
497 d = Pico32xMem->sh2_peri_regs[id][a / 4];
499 elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
503 static void sh2_peripheral_write8(u32 a, u32 d, int id)
505 u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
506 elprintf(EL_32X, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
512 if ((a == 2 && (d & 0x20)) || // transmiter enabled
513 (a == 4 && !(d & 0x80))) { // valid data in TDR
514 void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
515 if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
516 int level = PREG8(oregs, 0x60) >> 4;
517 int vector = PREG8(oregs, 0x63) & 0x7f;
518 elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
519 sh2_internal_irq(&sh2s[id ^ 1], level, vector);
524 static void sh2_peripheral_write16(u32 a, u32 d, int id)
526 u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
527 elprintf(EL_32X, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
533 if ((d & 0xff00) == 0xa500) { // WTCSR
535 p32x_timers_recalc();
537 if ((d & 0xff00) == 0x5a00) // WTCNT
545 static void sh2_peripheral_write32(u32 a, u32 d, int id)
547 u32 *r = Pico32xMem->sh2_peri_regs[id];
548 elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
554 // division unit (TODO: verify):
555 case 0x104: // DVDNT: divident L, starts divide
556 elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
558 signed int divisor = r[0x100 / 4];
559 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
560 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
564 elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
565 id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
567 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
568 signed int divisor = r[0x100 / 4];
569 // XXX: undocumented mirroring to 0x118,0x11c?
570 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
571 r[0x11c / 4] = r[0x114 / 4] = divident / divisor;
576 if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
577 elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
578 dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
579 dmac0->tcr0 &= 0xffffff;
581 // HACK: assume 68k starts writing soon and end the timeslice
584 // DREQ is only sent after first 4 words are written.
585 // we do multiple of 4 words to avoid messing up alignment
586 if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
587 elprintf(EL_32X, "68k -> sh2 DMA");
593 // ------------------------------------------------------------------
594 // default 32x handlers
595 u32 PicoRead8_32x(u32 a)
598 if ((a & 0xffc0) == 0x5100) { // a15100
599 d = p32x_reg_read16(a);
603 if (!(Pico32x.regs[0] & 1))
606 if ((a & 0xfff0) == 0x5180) { // a15180
607 d = p32x_vdp_read16(a);
611 if ((a & 0xfe00) == 0x5200) { // a15200
612 d = Pico32xMem->pal[(a & 0x1ff) / 2];
617 if ((a & 0xfffc) == 0x30ec) { // a130ec
622 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
632 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
636 u32 PicoRead16_32x(u32 a)
639 if ((a & 0xffc0) == 0x5100) { // a15100
640 d = p32x_reg_read16(a);
644 if (!(Pico32x.regs[0] & 1))
647 if ((a & 0xfff0) == 0x5180) { // a15180
648 d = p32x_vdp_read16(a);
652 if ((a & 0xfe00) == 0x5200) { // a15200
653 d = Pico32xMem->pal[(a & 0x1ff) / 2];
658 if ((a & 0xfffc) == 0x30ec) { // a130ec
659 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
663 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
667 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
671 void PicoWrite8_32x(u32 a, u32 d)
673 if ((a & 0xfc00) == 0x5000)
674 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
676 if ((a & 0xffc0) == 0x5100) { // a15100
677 p32x_reg_write8(a, d);
681 if (!(Pico32x.regs[0] & 1))
684 if ((a & 0xfff0) == 0x5180) { // a15180
685 p32x_vdp_write8(a, d);
690 if ((a & 0xfe00) == 0x5200) { // a15200
691 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
692 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
693 Pico32x.dirty_pal = 1;
698 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
701 void PicoWrite16_32x(u32 a, u32 d)
703 if ((a & 0xfc00) == 0x5000)
704 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
706 if ((a & 0xffc0) == 0x5100) { // a15100
707 p32x_reg_write16(a, d);
711 if (!(Pico32x.regs[0] & 1))
714 if ((a & 0xfff0) == 0x5180) { // a15180
715 p32x_vdp_write16(a, d);
719 if ((a & 0xfe00) == 0x5200) { // a15200
720 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
721 Pico32x.dirty_pal = 1;
726 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
729 // hint vector is writeable
730 static void PicoWrite8_hint(u32 a, u32 d)
732 if ((a & 0xfffc) == 0x0070) {
733 Pico32xMem->m68k_rom[a ^ 1] = d;
737 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
740 static void PicoWrite16_hint(u32 a, u32 d)
742 if ((a & 0xfffc) == 0x0070) {
743 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
747 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
750 void Pico32xSwapDRAM(int b)
752 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
753 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
754 cpu68k_map_set(m68k_write8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
755 cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
758 static void bank_switch(int b)
760 unsigned int rs, bank;
763 if (bank >= Pico.romsize) {
764 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
768 // 32X ROM (unbanked, XXX: consider mirroring?)
769 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
773 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
774 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
776 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
779 // -----------------------------------------------------------------
781 // -----------------------------------------------------------------
783 u32 p32x_sh2_read8(u32 a, int id)
787 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
788 return Pico32xMem->sh2_rom_m[a ^ 1];
789 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
790 return Pico32xMem->sh2_rom_s[a ^ 1];
792 if ((a & 0xdffc0000) == 0x06000000)
793 return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
795 if ((a & 0xdfc00000) == 0x02000000)
796 if ((a & 0x003fffff) < Pico.romsize)
797 return Pico.rom[(a & 0x3fffff) ^ 1];
799 if ((a & ~0xfff) == 0xc0000000)
800 return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
802 if ((a & 0xdffc0000) == 0x04000000) {
803 /* XXX: overwrite readable as normal? */
804 u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
805 return dram[(a & 0x1ffff) ^ 1];
808 if ((a & 0xdfffff00) == 0x4000) {
809 d = p32x_sh2reg_read16(a, id);
813 if ((a & 0xdfffff00) == 0x4100) {
814 d = p32x_vdp_read16(a);
815 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
820 if ((a & 0xdfffff00) == 0x4200) {
821 d = Pico32xMem->pal[(a & 0x1ff) / 2];
825 if ((a & 0xfffffe00) == 0xfffffe00)
826 return sh2_peripheral_read8(a, id);
828 elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
829 id ? 's' : 'm', a, d, sh2_pc(id));
838 elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
839 id ? 's' : 'm', a, d, sh2_pc(id));
843 u32 p32x_sh2_read16(u32 a, int id)
847 if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
848 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
849 if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
850 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
852 if ((a & 0xdffc0000) == 0x06000000)
853 return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
855 if ((a & 0xdfc00000) == 0x02000000)
856 if ((a & 0x003fffff) < Pico.romsize)
857 return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
859 if ((a & ~0xfff) == 0xc0000000)
860 return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
862 if ((a & 0xdffe0000) == 0x04000000)
863 return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
865 if ((a & 0xdfffff00) == 0x4000) {
866 d = p32x_sh2reg_read16(a, id);
867 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
872 if ((a & 0xdfffff00) == 0x4100) {
873 d = p32x_vdp_read16(a);
874 if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
879 if ((a & 0xdfffff00) == 0x4200) {
880 d = Pico32xMem->pal[(a & 0x1ff) / 2];
884 if ((a & 0xfffffe00) == 0xfffffe00)
885 return sh2_peripheral_read16(a, id);
887 elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
888 id ? 's' : 'm', a, d, sh2_pc(id));
892 elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
893 id ? 's' : 'm', a, d, sh2_pc(id));
897 u32 p32x_sh2_read32(u32 a, int id)
899 if ((a & 0xfffffe00) == 0xfffffe00)
900 return sh2_peripheral_read32(a, id);
902 // elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
903 return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
906 void p32x_sh2_write8(u32 a, u32 d, int id)
908 if ((a & 0xdffffc00) == 0x4000)
909 elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
910 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
912 if ((a & 0xdffc0000) == 0x06000000) {
913 Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
917 if ((a & 0xdffc0000) == 0x04000000) {
919 if (!(a & 0x20000) || d) {
920 dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
921 dram[(a & 0x1ffff) ^ 1] = d;
926 if ((a & ~0xfff) == 0xc0000000) {
927 Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
931 if ((a & 0xdfffff00) == 0x4100) {
932 p32x_vdp_write8(a, d);
936 if ((a & 0xdfffff00) == 0x4000) {
937 p32x_sh2reg_write8(a, d, id);
941 if ((a & 0xfffffe00) == 0xfffffe00) {
942 sh2_peripheral_write8(a, d, id);
946 elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
947 id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
950 void p32x_sh2_write16(u32 a, u32 d, int id)
952 if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
953 elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
954 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
956 // ignore "Associative purge space"
957 if ((a & 0xf8000000) == 0x40000000)
960 if ((a & 0xdffc0000) == 0x06000000) {
961 ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
965 if ((a & ~0xfff) == 0xc0000000) {
966 ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
970 if ((a & 0xdffc0000) == 0x04000000) {
971 u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
972 if (!(a & 0x20000)) {
977 if (!(d & 0xff00)) d |= *pd & 0xff00;
978 if (!(d & 0x00ff)) d |= *pd & 0x00ff;
983 if ((a & 0xdfffff00) == 0x4100) {
984 sh2_poll[id].cnt = 0; // for poll before VDP accesses
985 p32x_vdp_write16(a, d);
989 if ((a & 0xdffffe00) == 0x4200) {
990 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
991 Pico32x.dirty_pal = 1;
995 if ((a & 0xdfffff00) == 0x4000) {
996 p32x_sh2reg_write16(a, d, id);
1000 if ((a & 0xfffffe00) == 0xfffffe00) {
1001 sh2_peripheral_write16(a, d, id);
1005 elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
1006 id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
1009 void p32x_sh2_write32(u32 a, u32 d, int id)
1011 if ((a & 0xfffffe00) == 0xfffffe00) {
1012 sh2_peripheral_write32(a, d, id);
1016 p32x_sh2_write16(a, d >> 16, id);
1017 p32x_sh2_write16(a + 2, d, id);
1020 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
1021 void PicoMemSetup32x(void)
1028 Pico32xMem = calloc(1, sizeof(*Pico32xMem));
1029 if (Pico32xMem == NULL) {
1030 elprintf(EL_STATUS, "OOM");
1034 dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
1037 ps = (unsigned short *)Pico32xMem->m68k_rom;
1038 pl = (unsigned int *)Pico32xMem->m68k_rom;
1039 for (i = 1; i < 0xc0/4; i++)
1040 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1043 for (i = 0xc0/2; i < 0x100/2; i++)
1047 ps[0xc0/2] = 0x46fc;
1048 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1049 ps[0xfe/2] = 0x60fe; // jump to self
1051 ps[0xfe/2] = 0x4e75; // rts
1054 // fill remaining mem with ROM
1055 memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
1060 FILE *f = fopen("32X_M_BIOS.BIN", "rb");
1063 printf("missing 32X_M_BIOS.BIN\n");
1066 fread(Pico32xMem->sh2_rom_m, 1, sizeof(Pico32xMem->sh2_rom_m), f);
1068 f = fopen("32X_S_BIOS.BIN", "rb");
1070 printf("missing 32X_S_BIOS.BIN\n");
1073 fread(Pico32xMem->sh2_rom_s, 1, sizeof(Pico32xMem->sh2_rom_s), f);
1076 for (i = 0; i < sizeof(Pico32xMem->sh2_rom_m); i += 2) {
1077 int t = Pico32xMem->sh2_rom_m[i];
1078 Pico32xMem->sh2_rom_m[i] = Pico32xMem->sh2_rom_m[i + 1];
1079 Pico32xMem->sh2_rom_m[i + 1] = t;
1081 for (i = 0; i < sizeof(Pico32xMem->sh2_rom_s); i += 2) {
1082 int t = Pico32xMem->sh2_rom_s[i];
1083 Pico32xMem->sh2_rom_s[i] = Pico32xMem->sh2_rom_s[i + 1];
1084 Pico32xMem->sh2_rom_s[i + 1] = t;
1088 // cartridge area becomes unmapped
1089 // XXX: we take the easy way and don't unmap ROM,
1090 // so that we can avoid handling the RV bit.
1091 // m68k_map_unmap(0x000000, 0x3fffff);
1094 rs = sizeof(Pico32xMem->m68k_rom);
1095 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1096 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
1097 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1098 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1103 // 32X ROM (unbanked, XXX: consider mirroring?)
1104 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1107 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1108 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1113 // setup poll detector
1114 m68k_poll.flag = P32XF_68KPOLL;
1115 m68k_poll.cyc_max = 64;
1116 sh2_poll[0].flag = P32XF_MSH2POLL;
1117 sh2_poll[0].cyc_max = 21;
1118 sh2_poll[1].flag = P32XF_SSH2POLL;
1119 sh2_poll[1].cyc_max = 16;