3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
10 * a15102 ........ ......SM ? 4002 // intS intM
11 * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
12 * a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
13 * a15108 (32bit DREQ src) 4008
14 * a1510c (32bit DREQ dst) 400c
15 * a15110 llllllll llllll00 4010 // DREQ Len
16 * a15112 (16bit FIFO reg) 4012
17 * a15114 0 (16bit VRES clr) 4014
18 * a15116 0 (16bit Vint clr) 4016
19 * a15118 0 (16bit Hint clr) 4018
20 * a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
21 * a1511c 0 (16bit PWM clr) 401c
23 * a15120 (16 bytes comm) 2020
27 * iii. .cc. ..xx * // Internal, Cs, x
29 * sh2 map, wait/bus cycles (from docs):
31 * rom 0000000-0003fff 1 -
32 * sys reg 0004000-00040ff 1 1
33 * vdp reg 0004100-00041ff 5 5
34 * vdp pal 0004200-00043ff 5 5
35 * cart 2000000-23fffff 6-15
36 * dram/fb 4000000-401ffff 5-12 1-3
37 * fb ovr 4020000-403ffff
38 * sdram 6000000-603ffff 12 2 (cycles)
41 #include "../pico_int.h"
42 #include "../memory.h"
43 #include "../../cpu/sh2/compiler.h"
45 static const char str_mars[] = "MARS";
47 void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
48 struct Pico32xMem *Pico32xMem;
50 static void bank_switch(int b);
52 // addressing byte in 16bit reg
53 #define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
56 #define POLL_THRESHOLD 3
63 static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
67 if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
68 && cycles - m68k_poll.cycles <= 64)
70 if (m68k_poll.cnt++ > POLL_THRESHOLD) {
71 if (!(Pico32x.emu_flags & flags)) {
72 elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
73 a, cycles - m68k_poll.cycles);
76 Pico32x.emu_flags |= flags;
83 m68k_poll.cycles = cycles;
88 void p32x_m68k_poll_event(u32 flags)
90 if (Pico32x.emu_flags & flags) {
91 elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
92 Pico32x.emu_flags & ~flags);
93 Pico32x.emu_flags &= ~flags;
96 m68k_poll.addr = m68k_poll.cnt = 0;
99 static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
101 int cycles_left = sh2_cycles_left(sh2);
103 if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
104 if (sh2->poll_cnt++ > maxcnt) {
105 if (!(sh2->state & flags))
106 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x",
107 sh2->state, sh2->state | flags);
111 pevt_log_sh2(sh2, EVT_POLL_START);
118 sh2->poll_cycles = cycles_left;
121 void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
123 if (sh2->state & flags) {
124 elprintf_sh2(sh2, EL_32X, "state: %02x->%02x", sh2->state,
125 sh2->state & ~flags);
127 if (sh2->m68krcycles_done < m68k_cycles)
128 sh2->m68krcycles_done = m68k_cycles;
130 pevt_log_sh2_o(sh2, EVT_POLL_END);
133 sh2->state &= ~flags;
134 sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
137 static void sh2s_sync_on_read(SH2 *sh2)
140 if (sh2->poll_cnt != 0)
143 cycles = sh2_cycles_done(sh2);
145 p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
151 static int p32x_csum_faked;
152 static const u16 comm_fakevals[] = {
153 0x4d5f, 0x4f4b, // M_OK
154 0x535f, 0x4f4b, // S_OK
155 0x4D41, 0x5346, // MASF - Brutal Unleashed
156 0x5331, 0x4d31, // Darxide
159 0x0000, 0x0000, // eq for doom
160 0x0002, // Mortal Kombat
164 static u32 sh2_comm_faker(u32 a)
167 if (a == 0x28 && !p32x_csum_faked) {
169 return *(unsigned short *)(Pico.rom + 0x18e);
171 if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0]))
173 return comm_fakevals[f++];
177 // ------------------------------------------------------------------
180 static u32 p32x_reg_read16(u32 a)
185 if ((a & 0x30) == 0x20)
186 return sh2_comm_faker(a);
188 if ((a & 0x30) == 0x20) {
190 unsigned int cycles = SekCyclesDoneT();
191 int comreg = 1 << (a & 0x0f) / 2;
193 // evil X-Men proto polls in a dbra loop and expects it to expire..
194 if (SekDar(2) != dr2)
198 if (cycles - msh2.m68krcycles_done > 500)
199 p32x_sync_sh2s(cycles);
200 if (Pico32x.comm_dirty_sh2 & comreg)
201 Pico32x.comm_dirty_sh2 &= ~comreg;
202 else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
211 if (a == 2) { // INTM, INTS
212 unsigned int cycles = SekCyclesDoneT();
213 if (cycles - msh2.m68krcycles_done > 64)
214 p32x_sync_sh2s(cycles);
218 if ((a & 0x30) == 0x30)
219 return p32x_pwm_read16(a, NULL, SekCyclesDoneT());
222 return Pico32x.regs[a / 2];
225 static void dreq0_write(u16 *r, u32 d)
227 if (!(r[6 / 2] & P32XS_68S)) {
228 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
229 return; // ignored - tested
231 if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
232 Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
233 if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
234 r[6 / 2] |= P32XS_FULL;
235 // tested: len register decrements and 68S clears
236 // even if SH2s/DMAC aren't active..
238 if (r[0x10 / 2] == 0)
239 r[6 / 2] &= ~P32XS_68S;
241 if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
242 p32x_sync_sh2s(SekCyclesDoneT());
243 p32x_dreq0_trigger();
247 elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
250 // writable bits tested
251 static void p32x_reg_write8(u32 a, u32 d)
253 u16 *r = Pico32x.regs;
256 // for things like bset on comm port
260 case 0x00: // adapter ctl: FM writable
261 REG8IN16(r, 0x00) = d & 0x80;
263 case 0x01: // adapter ctl: RES and ADEN writable
264 if ((d ^ r[0]) & d & P32XS_nRES)
266 REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
267 REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
269 case 0x02: // ignored, always 0
271 case 0x03: // irq ctl
272 if ((d ^ r[0x02 / 2]) & 3) {
273 int cycles = SekCyclesDoneT();
274 p32x_sync_sh2s(cycles);
276 p32x_update_cmd_irq(NULL, cycles);
279 case 0x04: // ignored, always 0
283 if (r[0x04 / 2] != d) {
288 case 0x06: // ignored, always 0
290 case 0x07: // DREQ ctl
291 REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
292 if (!(d & P32XS_68S)) {
293 Pico32x.dmac0_fifo_ptr = 0;
294 REG8IN16(r, 0x07) &= ~P32XS_FULL;
296 REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
298 case 0x08: // ignored, always 0
300 case 0x09: // DREQ src
301 REG8IN16(r, 0x09) = d;
304 REG8IN16(r, 0x0a) = d;
307 REG8IN16(r, 0x0b) = d & 0xfe;
309 case 0x0c: // ignored, always 0
311 case 0x0d: // DREQ dest
314 case 0x10: // DREQ len
318 REG8IN16(r, a) = d & 0xfc;
320 // DREQ FIFO - writes to odd addr go to fifo
321 // do writes to even work? Reads return 0
326 d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
327 REG8IN16(r, 0x12) = 0;
330 case 0x14: // ignored, always 0
337 case 0x1a: // what's this?
338 elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
339 REG8IN16(r, a) = d & 0x01;
342 REG8IN16(r, a) = d & 0x01;
344 case 0x1c: // ignored, always 0
350 case 0x31: // PWM control
351 REG8IN16(r, a) &= ~0x0f;
352 REG8IN16(r, a) |= d & 0x0f;
354 case 0x32: // PWM cycle
355 REG8IN16(r, a) = d & 0x0f;
360 // PWM pulse regs.. Only writes to odd address send a value
361 // to FIFO; reads are 0 (except status bits)
370 d = (REG8IN16(r, a) << 8) | (d & 0xff);
373 case 0x3a: // ignored, always 0
381 p32x_pwm_write16(a & ~1, r[a / 2], NULL, SekCyclesDoneT());
385 if ((a & 0x30) == 0x20) {
386 int cycles = SekCyclesDoneT();
389 if (REG8IN16(r, a) == d)
392 comreg = 1 << (a & 0x0f) / 2;
393 if (Pico32x.comm_dirty_68k & comreg)
394 p32x_sync_sh2s(cycles);
397 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
398 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
399 Pico32x.comm_dirty_68k |= comreg;
401 if (cycles - (int)msh2.m68krcycles_done > 120)
402 p32x_sync_sh2s(cycles);
407 static void p32x_reg_write16(u32 a, u32 d)
409 u16 *r = Pico32x.regs;
412 // for things like bset on comm port
416 case 0x00: // adapter ctl
417 if ((d ^ r[0]) & d & P32XS_nRES)
419 r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
420 r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
422 case 0x08: // DREQ src
428 case 0x0c: // DREQ dest
434 case 0x10: // DREQ len
437 case 0x12: // FIFO reg
440 case 0x1a: // TV + mystery bit
441 r[a / 2] = d & 0x0101;
446 if ((a & 0x30) == 0x20) {
447 int cycles = SekCyclesDoneT();
453 comreg = 1 << (a & 0x0f) / 2;
454 if (Pico32x.comm_dirty_68k & comreg)
455 p32x_sync_sh2s(cycles);
458 p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
459 p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
460 Pico32x.comm_dirty_68k |= comreg;
462 if (cycles - (int)msh2.m68krcycles_done > 120)
463 p32x_sync_sh2s(cycles);
467 else if ((a & 0x30) == 0x30) {
468 p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
472 p32x_reg_write8(a + 1, d);
475 // ------------------------------------------------------------------
477 static u32 p32x_vdp_read16(u32 a)
482 d = Pico32x.vdp_regs[a / 2];
484 // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
485 // most often at 0xb1-0xb5, even during vblank,
486 // what's the deal with that?
487 // we'll just fake it along with hblank for now
488 Pico32x.vdp_fbcr_fake++;
489 if (Pico32x.vdp_fbcr_fake & 4)
491 if ((Pico32x.vdp_fbcr_fake & 7) == 0)
497 static void p32x_vdp_write8(u32 a, u32 d)
499 u16 *r = Pico32x.vdp_regs;
502 // TODO: verify what's writeable
505 // priority inversion is handled in palette
506 if ((r[0] ^ d) & P32XV_PRI)
507 Pico32x.dirty_pal = 1;
508 r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
510 case 0x03: // shift (for pp mode)
513 case 0x05: // fill len
518 Pico32x.pending_fb = d;
519 // if we are blanking and FS bit is changing
520 if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
521 r[0x0a/2] ^= P32XV_FS;
522 Pico32xSwapDRAM(d ^ 1);
523 elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
529 static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
532 if (a == 6) { // fill start
533 Pico32x.vdp_regs[6 / 2] = d;
536 if (a == 8) { // fill data
537 u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
538 int len = Pico32x.vdp_regs[4 / 2] + 1;
540 a = Pico32x.vdp_regs[6 / 2];
543 a = (a & 0xff00) | ((a + 1) & 0xff);
545 Pico32x.vdp_regs[0x06 / 2] = a;
546 Pico32x.vdp_regs[0x08 / 2] = d;
547 if (sh2 != NULL && len > 4) {
548 Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
549 // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
550 p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
555 p32x_vdp_write8(a | 1, d);
558 // ------------------------------------------------------------------
561 static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
563 u16 *r = Pico32x.regs;
567 case 0x00: // adapter/irq ctl
568 return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
569 | Pico32x.sh2irq_mask[sh2->is_slave];
570 case 0x04: // H count (often as comm too)
571 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
572 sh2s_sync_on_read(sh2);
573 return Pico32x.sh2_regs[4 / 2];
575 return (r[a / 2] & ~P32XS_FULL) | 0x4000;
576 case 0x08: // DREQ src
578 case 0x0c: // DREQ dst
580 case 0x10: // DREQ len
582 case 0x12: // DREQ FIFO - does this work on hw?
583 if (Pico32x.dmac0_fifo_ptr > 0) {
584 Pico32x.dmac0_fifo_ptr--;
585 r[a / 2] = Pico32x.dmac_fifo[0];
586 memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
587 Pico32x.dmac0_fifo_ptr * 2);
599 if ((a & 0x30) == 0x20) {
600 int comreg = 1 << (a & 0x0f) / 2;
601 if (Pico32x.comm_dirty_68k & comreg)
602 Pico32x.comm_dirty_68k &= ~comreg;
604 sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
605 sh2s_sync_on_read(sh2);
608 if ((a & 0x30) == 0x30)
609 return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
611 elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
612 "unhandled sysreg r16 [%06x] @%06x", a, SekPc);
616 static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
625 Pico32x.regs[0] &= ~P32XS_FM;
626 Pico32x.regs[0] |= (d << 8) & P32XS_FM;
628 case 1: // HEN/irq masks
629 old = Pico32x.sh2irq_mask[sh2->is_slave];
631 p32x_pwm_sync_to_sh2(sh2);
633 Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
634 Pico32x.sh2_regs[0] &= ~0x80;
635 Pico32x.sh2_regs[0] |= d & 0x80;
638 p32x_pwm_schedule_sh2(sh2);
640 p32x_update_cmd_irq(sh2, 0);
642 p32x_schedule_hint(sh2, 0);
646 if (Pico32x.sh2_regs[4 / 2] != d) {
647 Pico32x.sh2_regs[4 / 2] = d;
648 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
649 sh2_cycles_done_m68k(sh2));
655 if ((a & 0x30) == 0x20) {
656 u8 *r8 = (u8 *)Pico32x.regs;
662 p32x_m68k_poll_event(P32XF_68KCPOLL);
663 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
664 sh2_cycles_done_m68k(sh2));
665 comreg = 1 << (a & 0x0f) / 2;
666 Pico32x.comm_dirty_sh2 |= comreg;
671 static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
678 if ((a & 0x30) == 0x20) {
680 if (Pico32x.regs[a / 2] == d)
683 Pico32x.regs[a / 2] = d;
684 p32x_m68k_poll_event(P32XF_68KCPOLL);
685 p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
686 sh2_cycles_done_m68k(sh2));
687 comreg = 1 << (a & 0x0f) / 2;
688 Pico32x.comm_dirty_sh2 |= comreg;
692 else if ((a & 0x30) == 0x30) {
693 p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
699 Pico32x.regs[0] &= ~P32XS_FM;
700 Pico32x.regs[0] |= d & P32XS_FM;
703 Pico32x.sh2irqs &= ~P32XI_VRES;
706 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
709 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
712 Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
713 p32x_update_cmd_irq(sh2, 0);
716 p32x_pwm_sync_to_sh2(sh2);
717 Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
718 p32x_pwm_schedule_sh2(sh2);
722 p32x_sh2reg_write8(a | 1, d, sh2);
726 p32x_update_irls(sh2, 0);
729 // ------------------------------------------------------------------
733 static u32 PicoRead8_32x_on(u32 a)
736 if ((a & 0xffc0) == 0x5100) { // a15100
737 d = p32x_reg_read16(a);
741 if ((a & 0xfc00) != 0x5000)
742 return PicoRead8_io(a);
744 if ((a & 0xfff0) == 0x5180) { // a15180
745 d = p32x_vdp_read16(a);
749 if ((a & 0xfe00) == 0x5200) { // a15200
750 d = Pico32xMem->pal[(a & 0x1ff) / 2];
754 if ((a & 0xfffc) == 0x30ec) { // a130ec
759 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
769 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
773 static u32 PicoRead16_32x_on(u32 a)
776 if ((a & 0xffc0) == 0x5100) { // a15100
777 d = p32x_reg_read16(a);
781 if ((a & 0xfc00) != 0x5000)
782 return PicoRead16_io(a);
784 if ((a & 0xfff0) == 0x5180) { // a15180
785 d = p32x_vdp_read16(a);
789 if ((a & 0xfe00) == 0x5200) { // a15200
790 d = Pico32xMem->pal[(a & 0x1ff) / 2];
794 if ((a & 0xfffc) == 0x30ec) { // a130ec
795 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
799 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
803 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
807 static void PicoWrite8_32x_on(u32 a, u32 d)
809 if ((a & 0xfc00) == 0x5000)
810 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
812 if ((a & 0xffc0) == 0x5100) { // a15100
813 p32x_reg_write8(a, d);
817 if ((a & 0xfc00) != 0x5000) {
822 if (!(Pico32x.regs[0] & P32XS_FM)) {
823 if ((a & 0xfff0) == 0x5180) { // a15180
824 p32x_vdp_write8(a, d);
829 if ((a & 0xfe00) == 0x5200) { // a15200
830 elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
831 ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
832 Pico32x.dirty_pal = 1;
837 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
840 static void PicoWrite16_32x_on(u32 a, u32 d)
842 if ((a & 0xfc00) == 0x5000)
843 elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
845 if ((a & 0xffc0) == 0x5100) { // a15100
846 p32x_reg_write16(a, d);
850 if ((a & 0xfc00) != 0x5000) {
851 PicoWrite16_io(a, d);
855 if (!(Pico32x.regs[0] & P32XS_FM)) {
856 if ((a & 0xfff0) == 0x5180) { // a15180
857 p32x_vdp_write16(a, d, NULL); // FIXME?
861 if ((a & 0xfe00) == 0x5200) { // a15200
862 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
863 Pico32x.dirty_pal = 1;
868 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
872 u32 PicoRead8_32x(u32 a)
875 if ((a & 0xffc0) == 0x5100) { // a15100
876 // regs are always readable
877 d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1];
881 if ((a & 0xfffc) == 0x30ec) { // a130ec
886 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
890 elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc);
894 u32 PicoRead16_32x(u32 a)
897 if ((a & 0xffc0) == 0x5100) { // a15100
898 d = Pico32x.regs[(a & 0x3f) / 2];
902 if ((a & 0xfffc) == 0x30ec) { // a130ec
903 d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S';
907 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
911 elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc);
915 void PicoWrite8_32x(u32 a, u32 d)
917 if ((a & 0xffc0) == 0x5100) { // a15100
918 u16 *r = Pico32x.regs;
920 elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
923 if ((d ^ r[0]) & d & P32XS_ADEN) {
925 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
927 p32x_reg_write8(a, d); // forward for reset processing
932 // allow only COMM for now
933 if ((a & 0x30) == 0x20) {
940 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
943 void PicoWrite16_32x(u32 a, u32 d)
945 if ((a & 0xffc0) == 0x5100) { // a15100
946 u16 *r = Pico32x.regs;
948 elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
951 if ((d ^ r[0]) & d & P32XS_ADEN) {
953 r[0] &= ~P32XS_nRES; // causes reset if specified by this write
955 p32x_reg_write16(a, d); // forward for reset processing
960 // allow only COMM for now
961 if ((a & 0x30) == 0x20)
966 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
969 /* quirk: in both normal and overwrite areas only nonzero values go through */
970 #define sh2_write8_dramN(n) \
971 if ((d & 0xff) != 0) { \
972 u8 *dram = (u8 *)Pico32xMem->dram[n]; \
973 dram[(a & 0x1ffff) ^ 1] = d; \
976 static void m68k_write8_dram0_ow(u32 a, u32 d)
981 static void m68k_write8_dram1_ow(u32 a, u32 d)
986 #define sh2_write16_dramN(n) \
987 u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
988 if (!(a & 0x20000)) { \
993 if (!(d & 0xff00)) d |= *pd & 0xff00; \
994 if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
997 static void m68k_write16_dram0_ow(u32 a, u32 d)
999 sh2_write16_dramN(0);
1002 static void m68k_write16_dram1_ow(u32 a, u32 d)
1004 sh2_write16_dramN(1);
1007 // -----------------------------------------------------------------
1009 // hint vector is writeable
1010 static void PicoWrite8_hint(u32 a, u32 d)
1012 if ((a & 0xfffc) == 0x0070) {
1013 Pico32xMem->m68k_rom[a ^ 1] = d;
1017 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
1020 static void PicoWrite16_hint(u32 a, u32 d)
1022 if ((a & 0xfffc) == 0x0070) {
1023 ((u16 *)Pico32xMem->m68k_rom)[a/2] = d;
1027 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
1030 static void bank_switch(int b)
1032 unsigned int rs, bank;
1035 if (bank >= Pico.romsize) {
1036 elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
1040 // 32X ROM (unbanked, XXX: consider mirroring?)
1041 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1045 cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1046 cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
1048 elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
1051 // setup FAME fetchmap
1052 for (rs = 0x90; rs < 0xa0; rs++)
1053 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
1057 // -----------------------------------------------------------------
1059 // -----------------------------------------------------------------
1062 static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
1064 elprintf_sh2(sh2, EL_32X, "unmapped r8 [%08x] %02x @%06x",
1069 static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
1073 sh2_burn_cycles(sh2, 1*2);
1075 // 0x3ff00 is veridied
1076 if ((a & 0x3ff00) == 0x4000) {
1077 d = p32x_sh2reg_read16(a, sh2);
1081 if ((a & 0x3ff00) == 0x4100) {
1082 d = p32x_vdp_read16(a);
1083 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1088 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1089 return Pico32xMem->sh2_rom_m[a ^ 1];
1090 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1091 return Pico32xMem->sh2_rom_s[a ^ 1];
1093 if ((a & 0x3fe00) == 0x4200) {
1094 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1098 return sh2_read8_unmapped(a, sh2);
1106 elprintf_sh2(sh2, EL_32X, "r8 [%08x] %02x @%06x",
1111 static u32 sh2_read8_da(u32 a, SH2 *sh2)
1113 return sh2->data_array[(a & 0xfff) ^ 1];
1117 static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
1119 elprintf_sh2(sh2, EL_32X, "unmapped r16 [%08x] %04x @%06x",
1124 static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
1128 sh2_burn_cycles(sh2, 1*2);
1130 if ((a & 0x3ff00) == 0x4000) {
1131 d = p32x_sh2reg_read16(a, sh2);
1132 if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
1137 if ((a & 0x3ff00) == 0x4100) {
1138 d = p32x_vdp_read16(a);
1139 sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
1143 if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
1144 return *(u16 *)(Pico32xMem->sh2_rom_m + a);
1145 if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
1146 return *(u16 *)(Pico32xMem->sh2_rom_s + a);
1148 if ((a & 0x3fe00) == 0x4200) {
1149 d = Pico32xMem->pal[(a & 0x1ff) / 2];
1153 return sh2_read16_unmapped(a, sh2);
1156 elprintf_sh2(sh2, EL_32X, "r16 [%08x] %04x @%06x",
1161 static u32 sh2_read16_da(u32 a, SH2 *sh2)
1163 return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
1167 static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
1172 static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
1174 elprintf_sh2(sh2, EL_32X, "unmapped w8 [%08x] %02x @%06x",
1175 a, d & 0xff, sh2_pc(sh2));
1178 static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
1180 elprintf_sh2(sh2, EL_32X, "w8 [%08x] %02x @%06x",
1181 a, d & 0xff, sh2_pc(sh2));
1183 if (Pico32x.regs[0] & P32XS_FM) {
1184 if ((a & 0x3ff00) == 0x4100) {
1186 p32x_vdp_write8(a, d);
1191 if ((a & 0x3ff00) == 0x4000) {
1192 p32x_sh2reg_write8(a, d, sh2);
1196 sh2_write8_unmapped(a, d, sh2);
1199 static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
1201 sh2_write8_dramN(0);
1204 static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
1206 sh2_write8_dramN(1);
1209 static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
1211 u32 a1 = a & 0x3ffff;
1213 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1215 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1217 Pico32xMem->sdram[a1 ^ 1] = d;
1220 static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
1224 sh2_end_run(sh2, 32);
1226 sh2_write8_sdram(a, d, sh2);
1229 static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
1233 int id = sh2->is_slave;
1234 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1236 sh2_drc_wcheck_da(a, t, id);
1238 sh2->data_array[a1 ^ 1] = d;
1242 static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
1244 elprintf_sh2(sh2, EL_32X, "unmapped w16 [%08x] %04x @%06x",
1245 a, d & 0xffff, sh2_pc(sh2));
1248 static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
1250 if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
1251 elprintf_sh2(sh2, EL_32X, "w16 [%08x] %04x @%06x",
1252 a, d & 0xffff, sh2_pc(sh2));
1254 if (Pico32x.regs[0] & P32XS_FM) {
1255 if ((a & 0x3ff00) == 0x4100) {
1257 p32x_vdp_write16(a, d, sh2);
1261 if ((a & 0x3fe00) == 0x4200) {
1262 Pico32xMem->pal[(a & 0x1ff) / 2] = d;
1263 Pico32x.dirty_pal = 1;
1268 if ((a & 0x3ff00) == 0x4000) {
1269 p32x_sh2reg_write16(a, d, sh2);
1273 sh2_write16_unmapped(a, d, sh2);
1276 static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
1278 sh2_write16_dramN(0);
1281 static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
1283 sh2_write16_dramN(1);
1286 static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
1288 u32 a1 = a & 0x3ffff;
1290 int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
1292 sh2_drc_wcheck_ram(a, t, sh2->is_slave);
1294 ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
1297 static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
1301 int id = sh2->is_slave;
1302 int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
1304 sh2_drc_wcheck_da(a, t, id);
1306 ((u16 *)sh2->data_array)[a1 / 2] = d;
1310 typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
1311 typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
1313 #define SH2MAP_ADDR2OFFS_R(a) \
1314 ((u32)(a) >> SH2_READ_SHIFT)
1316 #define SH2MAP_ADDR2OFFS_W(a) \
1317 ((u32)(a) >> SH2_WRITE_SHIFT)
1319 u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
1321 const sh2_memmap *sh2_map = sh2->read8_map;
1324 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1326 if (map_flag_set(p))
1327 return ((sh2_read_handler *)(p << 1))(a, sh2);
1329 return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
1332 u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
1334 const sh2_memmap *sh2_map = sh2->read16_map;
1337 sh2_map += SH2MAP_ADDR2OFFS_R(a);
1339 if (map_flag_set(p))
1340 return ((sh2_read_handler *)(p << 1))(a, sh2);
1342 return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1345 u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
1347 const sh2_memmap *sh2_map = sh2->read16_map;
1348 sh2_read_handler *handler;
1352 offs = SH2MAP_ADDR2OFFS_R(a);
1355 if (!map_flag_set(p)) {
1356 // XXX: maybe 32bit access instead with ror?
1357 u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
1358 return (pd[0] << 16) | pd[1];
1362 return sh2_peripheral_read32(a, sh2);
1364 handler = (sh2_read_handler *)(p << 1);
1365 return (handler(a, sh2) << 16) | handler(a + 2, sh2);
1368 void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
1370 const void **sh2_wmap = sh2->write8_tab;
1371 sh2_write_handler *wh;
1373 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1377 void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
1379 const void **sh2_wmap = sh2->write16_tab;
1380 sh2_write_handler *wh;
1382 wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
1386 void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
1388 const void **sh2_wmap = sh2->write16_tab;
1389 sh2_write_handler *wh;
1392 offs = SH2MAP_ADDR2OFFS_W(a);
1394 if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
1395 sh2_peripheral_write32(a, d, sh2);
1399 wh = sh2_wmap[offs];
1400 wh(a, d >> 16, sh2);
1404 // -----------------------------------------------------------------
1406 static const u16 msh2_code[] = {
1407 // trap instructions
1408 0xaffe, // bra <self>
1410 // have to wait a bit until m68k initial program finishes clearing stuff
1411 // to avoid races with game SH2 code, like in Tempo
1412 0xd004, // mov.l @(_m_ok,pc), r0
1413 0xd105, // mov.l @(_cnt,pc), r1
1414 0xd205, // mov.l @(_start,pc), r2
1415 0x71ff, // add #-1, r1
1416 0x4115, // cmp/pl r1
1418 0xc208, // mov.l r0, @(h'20,gbr)
1419 0x6822, // mov.l @r2, r8
1422 ('M'<<8)|'_', ('O'<<8)|'K',
1424 0x2200, 0x03e0 // master start pointer in ROM
1427 static const u16 ssh2_code[] = {
1428 0xaffe, // bra <self>
1430 // code to wait for master, in case authentic master BIOS is used
1431 0xd104, // mov.l @(_m_ok,pc), r1
1432 0xd206, // mov.l @(_start,pc), r2
1433 0xc608, // mov.l @(h'20,gbr), r0
1434 0x3100, // cmp/eq r0, r1
1436 0xd003, // mov.l @(_s_ok,pc), r0
1437 0xc209, // mov.l r0, @(h'24,gbr)
1438 0x6822, // mov.l @r2, r8
1441 ('M'<<8)|'_', ('O'<<8)|'K',
1442 ('S'<<8)|'_', ('O'<<8)|'K',
1443 0x2200, 0x03e4 // slave start pointer in ROM
1446 #define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
1447 static void get_bios(void)
1454 if (p32x_bios_g != NULL) {
1455 elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
1456 Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
1460 ps = (u16 *)Pico32xMem->m68k_rom;
1462 for (i = 1; i < 0xc0/4; i++)
1463 pl[i] = HWSWAP(0x880200 + (i - 1) * 6);
1466 for (i = 0xc0/2; i < 0x100/2; i++)
1470 ps[0xc0/2] = 0x46fc;
1471 ps[0xc2/2] = 0x2700; // move #0x2700,sr
1472 ps[0xfe/2] = 0x60fe; // jump to self
1474 ps[0xfe/2] = 0x4e75; // rts
1477 // fill remaining m68k_rom page with game ROM
1478 memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
1479 Pico.rom + sizeof(Pico32xMem->m68k_rom),
1480 sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
1483 if (p32x_bios_m != NULL) {
1484 elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS");
1485 Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m));
1488 pl = (u32 *)Pico32xMem->sh2_rom_m;
1490 // fill exception vector table to our trap address
1491 for (i = 0; i < 128; i++)
1492 pl[i] = HWSWAP(0x200);
1495 memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code));
1498 pl[1] = pl[3] = HWSWAP(0x6040000);
1500 pl[0] = pl[2] = HWSWAP(0x204);
1504 if (p32x_bios_s != NULL) {
1505 elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS");
1506 Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s));
1509 pl = (u32 *)Pico32xMem->sh2_rom_s;
1511 // fill exception vector table to our trap address
1512 for (i = 0; i < 128; i++)
1513 pl[i] = HWSWAP(0x200);
1516 memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code));
1519 pl[1] = pl[3] = HWSWAP(0x603f800);
1521 pl[0] = pl[2] = HWSWAP(0x204);
1525 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
1526 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
1528 static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
1529 // for writes we are using handlers only
1530 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
1532 void Pico32xSwapDRAM(int b)
1534 cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1535 cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
1536 cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1537 cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
1538 cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff,
1539 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
1540 cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
1541 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
1544 sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
1545 sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
1547 sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
1548 sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
1551 void PicoMemSetup32x(void)
1556 Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
1557 if (Pico32xMem == NULL) {
1558 elprintf(EL_STATUS, "OOM");
1564 // cartridge area becomes unmapped
1565 // XXX: we take the easy way and don't unmap ROM,
1566 // so that we can avoid handling the RV bit.
1567 // m68k_map_unmap(0x000000, 0x3fffff);
1570 rs = sizeof(Pico32xMem->m68k_rom_bank);
1571 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1572 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
1573 cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
1574 cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
1576 // 32X ROM (unbanked, XXX: consider mirroring?)
1577 rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
1580 cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1581 cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
1583 // setup FAME fetchmap
1584 PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
1585 for (rs = 0x88; rs < 0x90; rs++)
1586 PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
1593 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
1594 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1);
1595 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
1596 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
1598 // SH2 maps: A31,A30,A29,CS1,CS0
1599 // all unmapped by default
1600 for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
1601 sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
1602 sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
1605 for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
1606 sh2_write8_map[i] = sh2_write8_unmapped;
1607 sh2_write16_map[i] = sh2_write16_unmapped;
1611 for (i = 0x40; i <= 0x5f; i++) {
1612 sh2_write8_map[i >> 1] =
1613 sh2_write16_map[i >> 1] = sh2_write_ignore;
1617 sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
1618 sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
1619 sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
1620 sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
1622 sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
1623 sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
1624 sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
1625 sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
1626 // CS2 - DRAM - done by Pico32xSwapDRAM()
1627 sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
1628 sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
1630 sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
1631 sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
1632 sh2_write8_map[0x06/2] = sh2_write8_sdram;
1633 sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
1634 sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
1635 sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
1636 sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
1638 sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
1639 sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
1640 sh2_write8_map[0xc0/2] = sh2_write8_da;
1641 sh2_write16_map[0xc0/2] = sh2_write16_da;
1643 sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
1644 sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
1645 sh2_write8_map[0xff/2] = sh2_peripheral_write8;
1646 sh2_write16_map[0xff/2] = sh2_peripheral_write16;
1648 // map DRAM area, both 68k and SH2
1651 msh2.read8_map = ssh2.read8_map = sh2_read8_map;
1652 msh2.read16_map = ssh2.read16_map = sh2_read16_map;
1653 msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
1654 msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
1656 sh2_drc_mem_setup(&msh2);
1657 sh2_drc_mem_setup(&ssh2);
1660 void Pico32xMemStateLoaded(void)
1662 bank_switch(Pico32x.regs[4 / 2]);
1663 Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
1664 memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
1665 Pico32x.dirty_pal = 1;
1667 Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
1668 memset(&m68k_poll, 0, sizeof(m68k_poll));
1670 msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
1672 ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
1674 sh2_drc_flush_all();
1677 // vim:shiftwidth=2:ts=2:expandtab