2 * SH2 peripherals/"system on chip"
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 * rough fffffe00-ffffffff map:
9 * e00-e05 SCI serial communication interface
10 * e10-e1a FRT free-running timer
11 * e60-e68 VCRx irq vectors
12 * e71-e72 DRCR dma selection
13 * e80-e83 WDT watchdog timer
14 * e91 SBYCR standby control
15 * e92 CCR cache control
17 * ee2 IPRA irq priorities
18 * ee4 VCRWDT WDT irq vectors
20 * f40-f7b UBC user break controller
22 * fe0-ffb BSC bus state controller
25 #include "../pico_int.h"
26 #include "../memory.h"
30 unsigned int sar, dar; // src, dst addr
31 unsigned int tcr; // transfer count
32 unsigned int chcr; // chan ctl
33 // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de
34 // ts - transfer size: 1, 2, 4, 16 bytes
35 // ar - auto request if 1, else dreq signal
39 #define DMA_AR (1 << 9)
40 #define DMA_IE (1 << 2)
41 #define DMA_TE (1 << 1)
42 #define DMA_DE (1 << 0)
46 struct dma_chan chan[2];
48 unsigned int unknown0;
50 unsigned int unknown1;
53 // pr - priority: chan0 > chan1 or round-robin
55 // nmif - nmi occurred
56 // dme - DMA master enable
57 #define DMA_DME (1 << 0)
60 static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
62 char *regs = (void *)sh2->peri_regs;
63 struct dmac *dmac = (void *)(regs + 0x180);
64 int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
65 int vector = (chan == &dmac->chan[0]) ?
66 dmac->vcrdma0 : dmac->vcrdma1;
68 elprintf(EL_32XP, "dmac irq %d %d", level, vector);
69 sh2_internal_irq(sh2, level, vector & 0x7f);
72 static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
74 chan->chcr |= DMA_TE; // DMA has ended normally
76 p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
77 if (chan->chcr & DMA_IE)
78 dmac_te_irq(sh2, chan);
81 static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
85 size = (chan->chcr >> 10) & 3;
88 d = p32x_sh2_read8(chan->sar, sh2);
89 p32x_sh2_write8(chan->dar, d, sh2);
91 d = p32x_sh2_read16(chan->sar, sh2);
92 p32x_sh2_write16(chan->dar, d, sh2);
95 d = p32x_sh2_read32(chan->sar, sh2);
96 p32x_sh2_write32(chan->dar, d, sh2);
99 d = p32x_sh2_read32(chan->sar + 0x00, sh2);
100 p32x_sh2_write32(chan->dar + 0x00, d, sh2);
101 d = p32x_sh2_read32(chan->sar + 0x04, sh2);
102 p32x_sh2_write32(chan->dar + 0x04, d, sh2);
103 d = p32x_sh2_read32(chan->sar + 0x08, sh2);
104 p32x_sh2_write32(chan->dar + 0x08, d, sh2);
105 d = p32x_sh2_read32(chan->sar + 0x0c, sh2);
106 p32x_sh2_write32(chan->dar + 0x0c, d, sh2);
107 chan->sar += 16; // always?
108 if (chan->chcr & (1 << 15))
110 if (chan->chcr & (1 << 14))
118 if (chan->chcr & (1 << 15))
120 if (chan->chcr & (1 << 14))
122 if (chan->chcr & (1 << 13))
124 if (chan->chcr & (1 << 12))
128 // DMA trigger by SH2 register write
129 static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
131 elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
132 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
133 chan->tcr &= 0xffffff;
135 if (chan->chcr & DMA_AR) {
136 // auto-request transfer
137 while ((int)chan->tcr > 0)
138 dmac_transfer_one(sh2, chan);
139 dmac_transfer_complete(sh2, chan);
143 // DREQ0 is only sent after first 4 words are written.
144 // we do multiple of 4 words to avoid messing up alignment
145 if ((chan->sar & ~0x20000000) == 0x00004012) {
146 if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
147 elprintf(EL_32XP, "68k -> sh2 DMA");
148 p32x_dreq0_trigger();
153 elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
154 "%08x->%08x, cnt %d, chcr %04x @%06x",
155 chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
158 // timer state - FIXME
159 static int timer_cycles[2];
160 static int timer_tick_cycles[2];
163 void p32x_timers_recalc(void)
169 for (i = 0; i < 2; i++) {
170 tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
171 // Sclk cycles per timer tick
173 cycles = 0x20 << tmp;
176 timer_tick_cycles[i] = cycles;
178 elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles);
182 void p32x_timers_do(unsigned int m68k_slice)
184 unsigned int cycles = m68k_slice * 3;
188 for (i = 0; i < 2; i++) {
189 void *pregs = sh2s[i].peri_regs;
190 if (PREG8(pregs, 0x80) & 0x20) { // TME
191 timer_cycles[i] += cycles;
192 cnt = PREG8(pregs, 0x81);
193 while (timer_cycles[i] >= timer_tick_cycles[i]) {
194 timer_cycles[i] -= timer_tick_cycles[i];
198 int level = PREG8(pregs, 0xe3) >> 4;
199 int vector = PREG8(pregs, 0xe4) & 0x7f;
200 elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)",
201 i ? 's' : 'm', level, vector);
202 sh2_internal_irq(&sh2s[i], level, vector);
205 PREG8(pregs, 0x81) = cnt;
210 void sh2_peripheral_reset(SH2 *sh2)
212 memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
213 PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
214 PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
215 PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
216 PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
217 PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
220 // ------------------------------------------------------------------
221 // SH2 internal peripheral memhandlers
222 // we keep them in little endian format
224 u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
226 u8 *r = (void *)sh2->peri_regs;
232 elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
233 a | ~0x1ff, d, sh2_pc(sh2));
237 u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
239 u16 *r = (void *)sh2->peri_regs;
245 elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
246 a | ~0x1ff, d, sh2_pc(sh2));
250 u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
254 d = sh2->peri_regs[a / 4];
256 elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
257 a | ~0x1ff, d, sh2_pc(sh2));
261 static void sci_trigger(SH2 *sh2, u8 *r)
265 if (!(PREG8(r, 2) & 0x20))
266 return; // transmitter not enabled
267 if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
270 oregs = (u8 *)sh2->other_sh2->peri_regs;
271 if (!(PREG8(oregs, 2) & 0x10))
272 return; // receiver not enabled
274 PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
275 PREG8(r, 4) |= 0x80; // TDRE - TDR empty
276 PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
278 // might need to delay these a bit..
279 if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
280 int level = PREG8(oregs, 0x60) >> 4;
281 int vector = PREG8(oregs, 0x64) & 0x7f;
282 elprintf(EL_32XP, "SCI tx irq (%d, %d)",
284 sh2_internal_irq(sh2, level, vector);
287 if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
288 int level = PREG8(oregs, 0x60) >> 4;
289 int vector = PREG8(oregs, 0x63) & 0x7f;
290 elprintf(EL_32XP, "SCI rx irq (%d, %d)",
292 sh2_internal_irq(sh2->other_sh2, level, vector);
296 void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
298 u8 *r = (void *)sh2->peri_regs;
301 elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x",
302 sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
308 case 0x002: // SCR - serial control
309 if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
314 case 0x003: // TDR - transmit data
316 case 0x004: // SSR - serial status
317 d = (old & (d | 0x06)) | (d & 1);
321 case 0x005: // RDR - receive data
325 elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
335 void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
337 u16 *r = (void *)sh2->peri_regs;
338 elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
345 if ((d & 0xff00) == 0xa500) { // WTCSR
347 p32x_timers_recalc();
349 if ((d & 0xff00) == 0x5a00) // WTCNT
357 void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
359 u32 *r = sh2->peri_regs;
362 elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
370 // division unit (TODO: verify):
371 case 0x104: // DVDNT: divident L, starts divide
372 elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
375 signed int divisor = r[0x100 / 4];
376 r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
377 r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
380 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
383 elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
384 r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
386 signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
387 signed int divisor = r[0x100 / 4];
388 // XXX: undocumented mirroring to 0x118,0x11c?
389 r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
391 r[0x11c / 4] = r[0x114 / 4] = divident;
393 if ((unsigned long long)divident + 1 > 1) {
394 //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
395 r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
399 r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
403 // perhaps starting a DMA?
404 if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
405 struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
406 if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
408 if (!(dmac->dmaor & DMA_DME))
411 if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
412 dmac_trigger(sh2, &dmac->chan[0]);
413 if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
414 dmac_trigger(sh2, &dmac->chan[1]);
419 static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
421 unsigned short dreqlen = Pico32x.regs[0x10 / 2];
424 // debug/sanity checks
425 if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
426 elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
428 // note: DACK is not connected, single addr mode should not be used
429 if ((chan->chcr & 0x3f08) != 0x0400)
430 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
431 if ((chan->sar & ~0x20000000) != 0x00004012)
432 elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
434 // HACK: assume bus is busy and SH2 is halted
435 sh2->state |= SH2_STATE_SLEEP;
437 for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
438 elprintf(EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
439 chan->dar, Pico32x.dmac_fifo[i], dreqlen);
440 p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
445 if (Pico32x.dmac0_fifo_ptr != i)
446 memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
447 (Pico32x.dmac0_fifo_ptr - i) * 2);
448 Pico32x.dmac0_fifo_ptr -= i;
450 Pico32x.regs[6 / 2] &= ~P32XS_FULL;
452 dmac_transfer_complete(sh2, chan);
454 sh2_end_run(sh2, 16);
457 static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
459 // debug/sanity checks
460 if ((chan->chcr & 0xc308) != 0x0000)
461 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
462 if ((chan->dar & ~0xf) != 0x20004030)
463 elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
465 dmac_transfer_one(sh2, chan);
467 dmac_transfer_complete(sh2, chan);
470 void p32x_dreq0_trigger(void)
472 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
473 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
475 elprintf(EL_32XP, "dreq0_trigger");
476 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
477 dreq0_do(&msh2, &mdmac->chan[0]);
479 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
480 dreq0_do(&ssh2, &sdmac->chan[0]);
484 void p32x_dreq1_trigger(void)
486 struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
487 struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
490 elprintf(EL_32XP, "dreq1_trigger");
491 if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
492 dreq1_do(&msh2, &mdmac->chan[1]);
495 if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
496 dreq1_do(&ssh2, &sdmac->chan[1]);
501 elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
504 // vim:shiftwidth=2:ts=2:expandtab