pico/carthw/svp/compiler.c

   1 // SSP1601 to ARM recompiler
   2
   3 // (c) Copyright 2008, Grazvydas "notaz" Ignotas
   4 // Free for non-commercial use.
   5
   6 #include "../../pico_int.h"
   7 #include "../../../cpu/drc/cmn.h"
   8 #include "compiler.h"
   9
  10 #define u32 unsigned int
  11
  12 static u32 *tcache_ptr = NULL;
  13
  14 static int nblocks = 0;
  15 static int n_in_ops = 0;
  16
  17 extern ssp1601_t *ssp;
  18
  19 #define rPC    ssp->gr[SSP_PC].h
  20 #define rPMC   ssp->gr[SSP_PMC]
  21
  22 #define SSP_FLAG_Z (1<<0xd)
  23 #define SSP_FLAG_N (1<<0xf)
  24
  25 #ifndef ARM
  26 #define DUMP_BLOCK 0x0c9a
  27 void ssp_drc_next(void){}
  28 void ssp_drc_next_patch(void){}
  29 void ssp_drc_end(void){}
  30 #endif
  31
  32 #include "gen_arm.c"
  33
  34 // -----------------------------------------------------
  35
  36 static int get_inc(int mode)
  37 {
  38         int inc = (mode >> 11) & 7;
  39         if (inc != 0) {
  40                 if (inc != 7) inc--;
  41                 inc = 1 << inc; // 0 1 2 4 8 16 32 128
  42                 if (mode & 0x8000) inc = -inc; // decrement mode
  43         }
  44         return inc;
  45 }
  46
  47 u32 ssp_pm_read(int reg)
  48 {
  49         u32 d = 0, mode;
  50
  51         if (ssp->emu_status & SSP_PMC_SET)
  52         {
  53                 ssp->pmac_read[reg] = rPMC.v;
  54                 ssp->emu_status &= ~SSP_PMC_SET;
  55                 return 0;
  56         }
  57
  58         // just in case
  59         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
  60
  61         mode = ssp->pmac_read[reg]>>16;
  62         if      ((mode & 0xfff0) == 0x0800) // ROM
  63         {
  64                 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
  65                 ssp->pmac_read[reg] += 1;
  66         }
  67         else if ((mode & 0x47ff) == 0x0018) // DRAM
  68         {
  69                 unsigned short *dram = (unsigned short *)svp->dram;
  70                 int inc = get_inc(mode);
  71                 d = dram[ssp->pmac_read[reg]&0xffff];
  72                 ssp->pmac_read[reg] += inc;
  73         }
  74
  75         // PMC value corresponds to last PMR accessed
  76         rPMC.v = ssp->pmac_read[reg];
  77
  78         return d;
  79 }
  80
  81 #define overwrite_write(dst, d) \
  82 { \
  83         if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
  84         if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
  85         if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
  86         if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
  87 }
  88
  89 void ssp_pm_write(u32 d, int reg)
  90 {
  91         unsigned short *dram;
  92         int mode, addr;
  93
  94         if (ssp->emu_status & SSP_PMC_SET)
  95         {
  96                 ssp->pmac_write[reg] = rPMC.v;
  97                 ssp->emu_status &= ~SSP_PMC_SET;
  98                 return;
  99         }
 100
 101         // just in case
 102         ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
 103
 104         dram = (unsigned short *)svp->dram;
 105         mode = ssp->pmac_write[reg]>>16;
 106         addr = ssp->pmac_write[reg]&0xffff;
 107         if      ((mode & 0x43ff) == 0x0018) // DRAM
 108         {
 109                 int inc = get_inc(mode);
 110                 if (mode & 0x0400) {
 111                        overwrite_write(dram[addr], d);
 112                 } else dram[addr] = d;
 113                 ssp->pmac_write[reg] += inc;
 114         }
 115         else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
 116         {
 117                 if (mode & 0x0400) {
 118                        overwrite_write(dram[addr], d);
 119                 } else dram[addr] = d;
 120                 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
 121         }
 122         else if ((mode & 0x47ff) == 0x001c) // IRAM
 123         {
 124                 int inc = get_inc(mode);
 125                 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
 126                 ssp->pmac_write[reg] += inc;
 127                 ssp->drc.iram_dirty = 1;
 128         }
 129
 130         rPMC.v = ssp->pmac_write[reg];
 131 }
 132
 133
 134 // -----------------------------------------------------
 135
 136 // 14 IRAM blocks
 137 static unsigned char iram_context_map[] =
 138 {
 139          0, 0, 0, 0, 1, 0, 0, 0, // 04
 140          0, 0, 0, 0, 0, 0, 2, 0, // 0e
 141          0, 0, 0, 0, 0, 3, 0, 4, // 15 17
 142          5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
 143          8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
 144          0, 0, 0, 0, 0, 0, 0, 0,
 145          0, 0,11, 0, 0,12, 0, 0, // 32 35
 146         13,14, 0, 0, 0, 0, 0, 0  // 38 39
 147 };
 148
 149 int ssp_get_iram_context(void)
 150 {
 151         unsigned char *ir = (unsigned char *)svp->iram_rom;
 152         int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
 153         val1 = iram_context_map[(val>>1)&0x3f];
 154
 155         if (val1 == 0) {
 156                 elprintf(EL_ANOMALY, "svp: iram ctx val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
 157                 //debug_dump2file(name, svp->iram_rom, 0x800);
 158                 //exit(1);
 159         }
 160         return val1;
 161 }
 162
 163 // -----------------------------------------------------
 164
 165 /* regs with known values */
 166 static struct
 167 {
 168         ssp_reg_t gr[8];
 169         unsigned char r[8];
 170         unsigned int pmac_read[5];
 171         unsigned int pmac_write[5];
 172         ssp_reg_t pmc;
 173         unsigned int emu_status;
 174 } known_regs;
 175
 176 #define KRREG_X     (1 << SSP_X)
 177 #define KRREG_Y     (1 << SSP_Y)
 178 #define KRREG_A     (1 << SSP_A)        /* AH only */
 179 #define KRREG_ST    (1 << SSP_ST)
 180 #define KRREG_STACK (1 << SSP_STACK)
 181 #define KRREG_PC    (1 << SSP_PC)
 182 #define KRREG_P     (1 << SSP_P)
 183 #define KRREG_PR0   (1 << 8)
 184 #define KRREG_PR4   (1 << 12)
 185 #define KRREG_AL    (1 << 16)
 186 #define KRREG_PMCM  (1 << 18)           /* only mode word of PMC */
 187 #define KRREG_PMC   (1 << 19)
 188 #define KRREG_PM0R  (1 << 20)
 189 #define KRREG_PM1R  (1 << 21)
 190 #define KRREG_PM2R  (1 << 22)
 191 #define KRREG_PM3R  (1 << 23)
 192 #define KRREG_PM4R  (1 << 24)
 193 #define KRREG_PM0W  (1 << 25)
 194 #define KRREG_PM1W  (1 << 26)
 195 #define KRREG_PM2W  (1 << 27)
 196 #define KRREG_PM3W  (1 << 28)
 197 #define KRREG_PM4W  (1 << 29)
 198
 199 /* bitfield of known register values */
 200 static u32 known_regb = 0;
 201
 202 /* known vals, which need to be flushed
 203  * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
 204  * ST means flags are being held in ARM PSR
 205  * P means that it needs to be recalculated
 206  */
 207 static u32 dirty_regb = 0;
 208
 209 /* known values of host regs.
 210  * -1            - unknown
 211  * 000000-00ffff - 16bit value
 212  * 100000-10ffff - base reg (r7) + 16bit val
 213  * 0r0000        - means reg (low) eq gr[r].h, r != AL
 214  */
 215 static int hostreg_r[4];
 216
 217 static void hostreg_clear(void)
 218 {
 219         int i;
 220         for (i = 0; i < 4; i++)
 221                 hostreg_r[i] = -1;
 222 }
 223
 224 static void hostreg_sspreg_changed(int sspreg)
 225 {
 226         int i;
 227         for (i = 0; i < 4; i++)
 228                 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
 229 }
 230
 231
 232 #define PROGRAM(x)   ((unsigned short *)svp->iram_rom)[x]
 233 #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
 234
 235 void tr_unhandled(void)
 236 {
 237         //FILE *f = fopen("tcache.bin", "wb");
 238         //fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
 239         //fclose(f);
 240         elprintf(EL_ANOMALY, "unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
 241         //exit(1);
 242 }
 243
 244 /* update P, if needed. Trashes r0 */
 245 static void tr_flush_dirty_P(void)
 246 {
 247         // TODO: const regs
 248         if (!(dirty_regb & KRREG_P)) return;
 249         EOP_MOV_REG_ASR(10, 4, 16);             // mov  r10, r4, asr #16
 250         EOP_MOV_REG_LSL( 0, 4, 16);             // mov  r0,  r4, lsl #16
 251         EOP_MOV_REG_ASR( 0, 0, 15);             // mov  r0,  r0, asr #15
 252         EOP_MUL(10, 0, 10);                     // mul  r10, r0, r10
 253         dirty_regb &= ~KRREG_P;
 254         hostreg_r[0] = -1;
 255 }
 256
 257 /* write dirty pr to host reg. Nothing is trashed */
 258 static void tr_flush_dirty_pr(int r)
 259 {
 260         int ror = 0, reg;
 261
 262         if (!(dirty_regb & (1 << (r+8)))) return;
 263
 264         switch (r&3) {
 265                 case 0: ror =    0; break;
 266                 case 1: ror = 24/2; break;
 267                 case 2: ror = 16/2; break;
 268         }
 269         reg = (r < 4) ? 8 : 9;
 270         EOP_BIC_IMM(reg,reg,ror,0xff);
 271         if (known_regs.r[r] != 0)
 272                 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
 273         dirty_regb &= ~(1 << (r+8));
 274 }
 275
 276 /* write all dirty pr0-pr7 to host regs. Nothing is trashed */
 277 static void tr_flush_dirty_prs(void)
 278 {
 279         int i, ror = 0, reg;
 280         int dirty = dirty_regb >> 8;
 281         if ((dirty&7) == 7) {
 282                 emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
 283                 dirty &= ~7;
 284         }
 285         if ((dirty&0x70) == 0x70) {
 286                 emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
 287                 dirty &= ~0x70;
 288         }
 289         /* r0-r7 */
 290         for (i = 0; dirty && i < 8; i++, dirty >>= 1)
 291         {
 292                 if (!(dirty&1)) continue;
 293                 switch (i&3) {
 294                         case 0: ror =    0; break;
 295                         case 1: ror = 24/2; break;
 296                         case 2: ror = 16/2; break;
 297                 }
 298                 reg = (i < 4) ? 8 : 9;
 299                 EOP_BIC_IMM(reg,reg,ror,0xff);
 300                 if (known_regs.r[i] != 0)
 301                         EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
 302         }
 303         dirty_regb &= ~0xff00;
 304 }
 305
 306 /* write dirty pr and "forget" it. Nothing is trashed. */
 307 static void tr_release_pr(int r)
 308 {
 309         tr_flush_dirty_pr(r);
 310         known_regb &= ~(1 << (r+8));
 311 }
 312
 313 /* fush ARM PSR to r6. Trashes r1 */
 314 static void tr_flush_dirty_ST(void)
 315 {
 316         if (!(dirty_regb & KRREG_ST)) return;
 317         EOP_BIC_IMM(6,6,0,0x0f);
 318         EOP_MRS(1);
 319         EOP_ORR_REG_LSR(6,6,1,28);
 320         dirty_regb &= ~KRREG_ST;
 321         hostreg_r[1] = -1;
 322 }
 323
 324 /* inverse of above. Trashes r1 */
 325 static void tr_make_dirty_ST(void)
 326 {
 327         if (dirty_regb & KRREG_ST) return;
 328         if (known_regb & KRREG_ST) {
 329                 int flags = 0;
 330                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
 331                 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
 332                 EOP_MSR_IMM(4/2, flags);
 333         } else {
 334                 EOP_MOV_REG_LSL(1, 6, 28);
 335                 EOP_MSR_REG(1);
 336                 hostreg_r[1] = -1;
 337         }
 338         dirty_regb |= KRREG_ST;
 339 }
 340
 341 /* load 16bit val into host reg r0-r3. Nothing is trashed */
 342 static void tr_mov16(int r, int val)
 343 {
 344         if (hostreg_r[r] != val) {
 345                 emit_mov_const(A_COND_AL, r, val);
 346                 hostreg_r[r] = val;
 347         }
 348 }
 349
 350 static void tr_mov16_cond(int cond, int r, int val)
 351 {
 352         emit_mov_const(cond, r, val);
 353         hostreg_r[r] = -1;
 354 }
 355
 356 /* trashes r1 */
 357 static void tr_flush_dirty_pmcrs(void)
 358 {
 359         u32 i, val = (u32)-1;
 360         if (!(dirty_regb & 0x3ff80000)) return;
 361
 362         if (dirty_regb & KRREG_PMC) {
 363                 val = known_regs.pmc.v;
 364                 emit_mov_const(A_COND_AL, 1, val);
 365                 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
 366
 367                 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
 368                         elprintf(EL_ANOMALY, "!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
 369                         tr_unhandled();
 370                 }
 371         }
 372         for (i = 0; i < 5; i++)
 373         {
 374                 if (dirty_regb & (1 << (20+i))) {
 375                         if (val != known_regs.pmac_read[i]) {
 376                                 val = known_regs.pmac_read[i];
 377                                 emit_mov_const(A_COND_AL, 1, val);
 378                         }
 379                         EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
 380                 }
 381                 if (dirty_regb & (1 << (25+i))) {
 382                         if (val != known_regs.pmac_write[i]) {
 383                                 val = known_regs.pmac_write[i];
 384                                 emit_mov_const(A_COND_AL, 1, val);
 385                         }
 386                         EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
 387                 }
 388         }
 389         dirty_regb &= ~0x3ff80000;
 390         hostreg_r[1] = -1;
 391 }
 392
 393 /* read bank word to r0 (upper bits zero). Thrashes r1. */
 394 static void tr_bank_read(int addr) /* word addr 0-0x1ff */
 395 {
 396         int breg = 7;
 397         if (addr > 0x7f) {
 398                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 399                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 400                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 401                 }
 402                 breg = 1;
 403         }
 404         EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1);    // ldrh r0, [r1, (op&0x7f)<<1]
 405         hostreg_r[0] = -1;
 406 }
 407
 408 /* write r0 to bank. Trashes r1. */
 409 static void tr_bank_write(int addr)
 410 {
 411         int breg = 7;
 412         if (addr > 0x7f) {
 413                 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
 414                         EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1);  // add  r1, r7, ((op&0x180)<<1)
 415                         hostreg_r[1] = 0x100000|((addr&0x180)<<1);
 416                 }
 417                 breg = 1;
 418         }
 419         EOP_STRH_IMM(0,breg,(addr&0x7f)<<1);            // strh r0, [r1, (op&0x7f)<<1]
 420 }
 421
 422 /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
 423 static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
 424 {
 425         int modulo_shift = -1;  /* unknown */
 426
 427         if (mod == 0) return;
 428
 429         if (!need_modulo || mod == 1) // +!
 430                 modulo_shift = 8;
 431         else if (need_modulo && (known_regb & KRREG_ST)) {
 432                 modulo_shift = known_regs.gr[SSP_ST].h & 7;
 433                 if (modulo_shift == 0) modulo_shift = 8;
 434         }
 435
 436         if (modulo_shift == -1)
 437         {
 438                 int reg = (r < 4) ? 8 : 9;
 439                 tr_release_pr(r);
 440                 if (dirty_regb & KRREG_ST) {
 441                         // avoid flushing ARM flags
 442                         EOP_AND_IMM(1, 6, 0, 0x70);
 443                         EOP_SUB_IMM(1, 1, 0, 0x10);
 444                         EOP_AND_IMM(1, 1, 0, 0x70);
 445                         EOP_ADD_IMM(1, 1, 0, 0x10);
 446                 } else {
 447                         EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands  r1, r6, #0x70
 448                         EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
 449                 }
 450                 EOP_MOV_REG_LSR(1, 1, 4);               // mov r1, r1, lsr #4
 451                 EOP_RSB_IMM(2, 1, 0, 8);                // rsb r1, r1, #8
 452                 EOP_MOV_IMM(3, 8/2, count);             // mov r3, #0x01000000
 453                 if (r&3)
 454                         EOP_ADD_IMM(1, 1, 0, (r&3)*8);  // add r1, r1, #(r&3)*8
 455                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 456                 if (mod == 2)
 457                      EOP_SUB_REG2_LSL(reg,reg,3,2);     // sub reg, reg, #0x01000000 << r2
 458                 else EOP_ADD_REG2_LSL(reg,reg,3,2);
 459                 EOP_RSB_IMM(1, 1, 0, 32);               // rsb r1, r1, #32
 460                 EOP_MOV_REG2_ROR(reg,reg,1);            // mov reg, reg, ror r1
 461                 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
 462         }
 463         else if (known_regb & (1 << (r + 8)))
 464         {
 465                 int modulo = (1 << modulo_shift) - 1;
 466                 if (mod == 2)
 467                      known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
 468                 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
 469         }
 470         else
 471         {
 472                 int reg = (r < 4) ? 8 : 9;
 473                 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
 474                 EOP_MOV_REG_ROR(reg,reg,ror);
 475                 // {add|sub} reg, reg, #1<<shift
 476                 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
 477                 EOP_MOV_REG_ROR(reg,reg,32-ror);
 478         }
 479 }
 480
 481 /* handle writes r0 to (rX). Trashes r1.
 482  * fortunately we can ignore modulo increment modes for writes. */
 483 static void tr_rX_write(int op)
 484 {
 485         if ((op&3) == 3)
 486         {
 487                 int mod = (op>>2) & 3; // direct addressing
 488                 tr_bank_write((op & 0x100) + mod);
 489         }
 490         else
 491         {
 492                 int r = (op&3) | ((op>>6)&4);
 493                 if (known_regb & (1 << (r + 8))) {
 494                         tr_bank_write((op&0x100) | known_regs.r[r]);
 495                 } else {
 496                         int reg = (r < 4) ? 8 : 9;
 497                         int ror = ((4 - (r&3))*8) & 0x1f;
 498                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 499                         if (r >= 4)
 500                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 501                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 502                         else     EOP_ADD_REG_LSL(1,7,1,1);
 503                         EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 504                         hostreg_r[1] = -1;
 505                 }
 506                 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
 507         }
 508 }
 509
 510 /* read (rX) to r0. Trashes r1-r3. */
 511 static void tr_rX_read(int r, int mod)
 512 {
 513         if ((r&3) == 3)
 514         {
 515                 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
 516         }
 517         else
 518         {
 519                 if (known_regb & (1 << (r + 8))) {
 520                         tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
 521                 } else {
 522                         int reg = (r < 4) ? 8 : 9;
 523                         int ror = ((4 - (r&3))*8) & 0x1f;
 524                         EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 525                         if (r >= 4)
 526                                 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 527                         if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 528                         else     EOP_ADD_REG_LSL(1,7,1,1);
 529                         EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 530                         hostreg_r[0] = hostreg_r[1] = -1;
 531                 }
 532                 tr_ptrr_mod(r, mod, 1, 1);
 533         }
 534 }
 535
 536 /* read ((rX)) to r0. Trashes r1,r2. */
 537 static void tr_rX_read2(int op)
 538 {
 539         int r = (op&3) | ((op>>6)&4); // src
 540
 541         if ((r&3) == 3) {
 542                 tr_bank_read((op&0x100) | ((op>>2)&3));
 543         } else if (known_regb & (1 << (r+8))) {
 544                 tr_bank_read((op&0x100) | known_regs.r[r]);
 545         } else {
 546                 int reg = (r < 4) ? 8 : 9;
 547                 int ror = ((4 - (r&3))*8) & 0x1f;
 548                 EOP_AND_IMM(1,reg,ror/2,0xff);                  // and r1, r{7,8}, <mask>
 549                 if (r >= 4)
 550                         EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1);            // orr r1, r1, 1<<shift
 551                 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1);     // add r1, r7, r1, lsr #lsr
 552                 else     EOP_ADD_REG_LSL(1,7,1,1);
 553                 EOP_LDRH_SIMPLE(0,1);                           // ldrh r0, [r1]
 554         }
 555         EOP_LDR_IMM(2,7,0x48c);                                 // ptr_iram_rom
 556         EOP_ADD_REG_LSL(2,2,0,1);                               // add  r2, r2, r0, lsl #1
 557         EOP_ADD_IMM(0,0,0,1);                                   // add  r0, r0, #1
 558         if ((r&3) == 3) {
 559                 tr_bank_write((op&0x100) | ((op>>2)&3));
 560         } else if (known_regb & (1 << (r+8))) {
 561                 tr_bank_write((op&0x100) | known_regs.r[r]);
 562         } else {
 563                 EOP_STRH_SIMPLE(0,1);                           // strh r0, [r1]
 564                 hostreg_r[1] = -1;
 565         }
 566         EOP_LDRH_SIMPLE(0,2);                                   // ldrh r0, [r2]
 567         hostreg_r[0] = hostreg_r[2] = -1;
 568 }
 569
 570 // check if AL is going to be used later in block
 571 static int tr_predict_al_need(void)
 572 {
 573         int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
 574
 575         while (1)
 576         {
 577                 op = PROGRAM(pc);
 578                 switch (op >> 9)
 579                 {
 580                         // ld d, s
 581                         case 0x00:
 582                                 tmpv2 = (op >> 4) & 0xf; // dst
 583                                 tmpv  = op & 0xf; // src
 584                                 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
 585                                         return 0;
 586                                 break;
 587
 588                         // ld (ri), s
 589                         case 0x02:
 590                         // ld ri, s
 591                         case 0x0a:
 592                         // OP a, s
 593                         case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
 594                                 tmpv  = op & 0xf; // src
 595                                 if (tmpv == SSP_AL) // OP *, AL
 596                                         return 1;
 597                                 break;
 598
 599                         case 0x04:
 600                         case 0x06:
 601                         case 0x14:
 602                         case 0x34:
 603                         case 0x44:
 604                         case 0x64:
 605                         case 0x74: pc++; break;
 606
 607                         // call cond, addr
 608                         case 0x24:
 609                         // bra cond, addr
 610                         case 0x26:
 611                         // mod cond, op
 612                         case 0x48:
 613                         // mpys?
 614                         case 0x1b:
 615                         // mpya (rj), (ri), b
 616                         case 0x4b: return 1;
 617
 618                         // mld (rj), (ri), b
 619                         case 0x5b: return 0; // cleared anyway
 620
 621                         // and A, *
 622                         case 0x50:
 623                                 tmpv  = op & 0xf; // src
 624                                 if (tmpv == SSP_AL) return 1;
 625                         case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
 626                                 return 0;
 627                 }
 628                 pc++;
 629         }
 630 }
 631
 632
 633 /* get ARM cond which would mean that SSP cond is satisfied. No trash. */
 634 static int tr_cond_check(int op)
 635 {
 636         int f = (op & 0x100) >> 8;
 637         switch (op&0xf0) {
 638                 case 0x00: return A_COND_AL;    /* always true */
 639                 case 0x50:                      /* Z matches f(?) bit */
 640                         if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
 641                         EOP_TST_IMM(6, 0, 4);
 642                         return f ? A_COND_NE : A_COND_EQ;
 643                 case 0x70:                      /* N matches f(?) bit */
 644                         if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
 645                         EOP_TST_IMM(6, 0, 8);
 646                         return f ? A_COND_NE : A_COND_EQ;
 647                 default:
 648                         elprintf(EL_ANOMALY, "unimplemented cond?\n");
 649                         tr_unhandled();
 650                         return 0;
 651         }
 652 }
 653
 654 static int tr_neg_cond(int cond)
 655 {
 656         switch (cond) {
 657                 case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
 658                 case A_COND_EQ: return A_COND_NE;
 659                 case A_COND_NE: return A_COND_EQ;
 660                 case A_COND_MI: return A_COND_PL;
 661                 case A_COND_PL: return A_COND_MI;
 662                 default:        elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
 663         }
 664         return 0;
 665 }
 666
 667 static int tr_aop_ssp2arm(int op)
 668 {
 669         switch (op) {
 670                 case 1: return A_OP_SUB;
 671                 case 3: return A_OP_CMP;
 672                 case 4: return A_OP_ADD;
 673                 case 5: return A_OP_AND;
 674                 case 6: return A_OP_ORR;
 675                 case 7: return A_OP_EOR;
 676         }
 677
 678         tr_unhandled();
 679         return 0;
 680 }
 681
 682 // -----------------------------------------------------
 683
 684 //@ r4:  XXYY
 685 //@ r5:  A
 686 //@ r6:  STACK and emu flags
 687 //@ r7:  SSP context
 688 //@ r10: P
 689
 690 // read general reg to r0. Trashes r1
 691 static void tr_GR0_to_r0(int op)
 692 {
 693         tr_mov16(0, 0xffff);
 694 }
 695
 696 static void tr_X_to_r0(int op)
 697 {
 698         if (hostreg_r[0] != (SSP_X<<16)) {
 699                 EOP_MOV_REG_LSR(0, 4, 16);      // mov  r0, r4, lsr #16
 700                 hostreg_r[0] = SSP_X<<16;
 701         }
 702 }
 703
 704 static void tr_Y_to_r0(int op)
 705 {
 706         if (hostreg_r[0] != (SSP_Y<<16)) {
 707                 EOP_MOV_REG_SIMPLE(0, 4);       // mov  r0, r4
 708                 hostreg_r[0] = SSP_Y<<16;
 709         }
 710 }
 711
 712 static void tr_A_to_r0(int op)
 713 {
 714         if (hostreg_r[0] != (SSP_A<<16)) {
 715                 EOP_MOV_REG_LSR(0, 5, 16);      // mov  r0, r5, lsr #16  @ AH
 716                 hostreg_r[0] = SSP_A<<16;
 717         }
 718 }
 719
 720 static void tr_ST_to_r0(int op)
 721 {
 722         // VR doesn't need much accuracy here..
 723         EOP_MOV_REG_LSR(0, 6, 4);               // mov  r0, r6, lsr #4
 724         EOP_AND_IMM(0, 0, 0, 0x67);             // and  r0, r0, #0x67
 725         hostreg_r[0] = -1;
 726 }
 727
 728 static void tr_STACK_to_r0(int op)
 729 {
 730         // 448
 731         EOP_SUB_IMM(6, 6,  8/2, 0x20);          // sub  r6, r6, #1<<29
 732         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 733         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 734         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 735         EOP_LDRH_SIMPLE(0, 1);                  // ldrh r0, [r1]
 736         hostreg_r[0] = hostreg_r[1] = -1;
 737 }
 738
 739 static void tr_PC_to_r0(int op)
 740 {
 741         tr_mov16(0, known_regs.gr[SSP_PC].h);
 742 }
 743
 744 static void tr_P_to_r0(int op)
 745 {
 746         tr_flush_dirty_P();
 747         EOP_MOV_REG_LSR(0, 10, 16);             // mov  r0, r10, lsr #16
 748         hostreg_r[0] = -1;
 749 }
 750
 751 static void tr_AL_to_r0(int op)
 752 {
 753         if (op == 0x000f) {
 754                 if (known_regb & KRREG_PMC) {
 755                         known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 756                 } else {
 757                         EOP_LDR_IMM(0,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 758                         EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
 759                         EOP_STR_IMM(0,7,0x484);
 760                 }
 761         }
 762
 763         if (hostreg_r[0] != (SSP_AL<<16)) {
 764                 EOP_MOV_REG_SIMPLE(0, 5);       // mov  r0, r5
 765                 hostreg_r[0] = SSP_AL<<16;
 766         }
 767 }
 768
 769 static void tr_PMX_to_r0(int reg)
 770 {
 771         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
 772         {
 773                 known_regs.pmac_read[reg] = known_regs.pmc.v;
 774                 known_regs.emu_status &= ~SSP_PMC_SET;
 775                 known_regb |= 1 << (20+reg);
 776                 dirty_regb |= 1 << (20+reg);
 777                 return;
 778         }
 779
 780         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
 781         {
 782                 u32 pmcv = known_regs.pmac_read[reg];
 783                 int mode = pmcv>>16;
 784                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 785
 786                 if      ((mode & 0xfff0) == 0x0800)
 787                 {
 788                         EOP_LDR_IMM(1,7,0x488);         // rom_ptr
 789                         emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
 790                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 791                         known_regs.pmac_read[reg] += 1;
 792                 }
 793                 else if ((mode & 0x47ff) == 0x0018) // DRAM
 794                 {
 795                         int inc = get_inc(mode);
 796                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
 797                         emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
 798                         EOP_LDRH_REG(0,1,0);            // ldrh r0, [r1, r0]
 799                         if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
 800                         {
 801                                 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
 802                                 tr_flush_dirty_ST();
 803                                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 804                                 EOP_TST_REG_SIMPLE(0,0);
 805                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1);       // subeq r11, r11, #1024
 806                                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
 807                                 EOP_STR_IMM(1,7,0x484);                 // str r1, [r7, #0x484] // emu_status
 808                         }
 809                         known_regs.pmac_read[reg] += inc;
 810                 }
 811                 else
 812                 {
 813                         tr_unhandled();
 814                 }
 815                 known_regs.pmc.v = known_regs.pmac_read[reg];
 816                 //known_regb |= KRREG_PMC;
 817                 dirty_regb |= KRREG_PMC;
 818                 dirty_regb |= 1 << (20+reg);
 819                 hostreg_r[0] = hostreg_r[1] = -1;
 820                 return;
 821         }
 822
 823         known_regb &= ~KRREG_PMC;
 824         dirty_regb &= ~KRREG_PMC;
 825         known_regb &= ~(1 << (20+reg));
 826         dirty_regb &= ~(1 << (20+reg));
 827
 828         // call the C code to handle this
 829         tr_flush_dirty_ST();
 830         //tr_flush_dirty_pmcrs();
 831         tr_mov16(0, reg);
 832         emit_call(A_COND_AL, ssp_pm_read);
 833         hostreg_clear();
 834 }
 835
 836 static void tr_PM0_to_r0(int op)
 837 {
 838         tr_PMX_to_r0(0);
 839 }
 840
 841 static void tr_PM1_to_r0(int op)
 842 {
 843         tr_PMX_to_r0(1);
 844 }
 845
 846 static void tr_PM2_to_r0(int op)
 847 {
 848         tr_PMX_to_r0(2);
 849 }
 850
 851 static void tr_XST_to_r0(int op)
 852 {
 853         EOP_ADD_IMM(0, 7, 24/2, 4);     // add r0, r7, #0x400
 854         EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
 855 }
 856
 857 static void tr_PM4_to_r0(int op)
 858 {
 859         tr_PMX_to_r0(4);
 860 }
 861
 862 static void tr_PMC_to_r0(int op)
 863 {
 864         if (known_regb & KRREG_PMC)
 865         {
 866                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
 867                         known_regs.emu_status |= SSP_PMC_SET;
 868                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
 869                         // do nothing - this is handled elsewhere
 870                 } else {
 871                         tr_mov16(0, known_regs.pmc.l);
 872                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
 873                 }
 874         }
 875         else
 876         {
 877                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
 878                 tr_flush_dirty_ST();
 879                 if (op != 0x000e)
 880                         EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
 881                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
 882                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
 883                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
 884                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
 885                 EOP_STR_IMM(1,7,0x484);
 886                 hostreg_r[0] = hostreg_r[1] = -1;
 887         }
 888 }
 889
 890
 891 typedef void (tr_read_func)(int op);
 892
 893 static tr_read_func *tr_read_funcs[16] =
 894 {
 895         tr_GR0_to_r0,
 896         tr_X_to_r0,
 897         tr_Y_to_r0,
 898         tr_A_to_r0,
 899         tr_ST_to_r0,
 900         tr_STACK_to_r0,
 901         tr_PC_to_r0,
 902         tr_P_to_r0,
 903         tr_PM0_to_r0,
 904         tr_PM1_to_r0,
 905         tr_PM2_to_r0,
 906         tr_XST_to_r0,
 907         tr_PM4_to_r0,
 908         (tr_read_func *)tr_unhandled,
 909         tr_PMC_to_r0,
 910         tr_AL_to_r0
 911 };
 912
 913
 914 // write r0 to general reg handlers. Trashes r1
 915 #define TR_WRITE_R0_TO_REG(reg) \
 916 { \
 917         hostreg_sspreg_changed(reg); \
 918         hostreg_r[0] = (reg)<<16; \
 919         if (const_val != -1) { \
 920                 known_regs.gr[reg].h = const_val; \
 921                 known_regb |= 1 << (reg); \
 922         } else { \
 923                 known_regb &= ~(1 << (reg)); \
 924         } \
 925 }
 926
 927 static void tr_r0_to_GR0(int const_val)
 928 {
 929         // do nothing
 930 }
 931
 932 static void tr_r0_to_X(int const_val)
 933 {
 934         EOP_MOV_REG_LSL(4, 4, 16);              // mov  r4, r4, lsl #16
 935         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 936         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 937         dirty_regb |= KRREG_P;                  // touching X or Y makes P dirty.
 938         TR_WRITE_R0_TO_REG(SSP_X);
 939 }
 940
 941 static void tr_r0_to_Y(int const_val)
 942 {
 943         EOP_MOV_REG_LSR(4, 4, 16);              // mov  r4, r4, lsr #16
 944         EOP_ORR_REG_LSL(4, 4, 0, 16);           // orr  r4, r4, r0, lsl #16
 945         EOP_MOV_REG_ROR(4, 4, 16);              // mov  r4, r4, ror #16
 946         dirty_regb |= KRREG_P;
 947         TR_WRITE_R0_TO_REG(SSP_Y);
 948 }
 949
 950 static void tr_r0_to_A(int const_val)
 951 {
 952         if (tr_predict_al_need()) {
 953                 EOP_MOV_REG_LSL(5, 5, 16);      // mov  r5, r5, lsl #16
 954                 EOP_MOV_REG_LSR(5, 5, 16);      // mov  r5, r5, lsr #16  @ AL
 955                 EOP_ORR_REG_LSL(5, 5, 0, 16);   // orr  r5, r5, r0, lsl #16
 956         }
 957         else
 958                 EOP_MOV_REG_LSL(5, 0, 16);
 959         TR_WRITE_R0_TO_REG(SSP_A);
 960 }
 961
 962 static void tr_r0_to_ST(int const_val)
 963 {
 964         // VR doesn't need much accuracy here..
 965         EOP_AND_IMM(1, 0,   0, 0x67);           // and   r1, r0, #0x67
 966         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
 967         EOP_ORR_REG_LSL(6, 6, 1, 4);            // orr   r6, r6, r1, lsl #4
 968         TR_WRITE_R0_TO_REG(SSP_ST);
 969         hostreg_r[1] = -1;
 970         dirty_regb &= ~KRREG_ST;
 971 }
 972
 973 static void tr_r0_to_STACK(int const_val)
 974 {
 975         // 448
 976         EOP_ADD_IMM(1, 7, 24/2, 0x04);          // add  r1, r7, 0x400
 977         EOP_ADD_IMM(1, 1, 0, 0x48);             // add  r1, r1, 0x048
 978         EOP_ADD_REG_LSR(1, 1, 6, 28);           // add  r1, r1, r6, lsr #28
 979         EOP_STRH_SIMPLE(0, 1);                  // strh r0, [r1]
 980         EOP_ADD_IMM(6, 6,  8/2, 0x20);          // add  r6, r6, #1<<29
 981         hostreg_r[1] = -1;
 982 }
 983
 984 static void tr_r0_to_PC(int const_val)
 985 {
 986 /*
 987  * do nothing - dispatcher will take care of this
 988         EOP_MOV_REG_LSL(1, 0, 16);              // mov  r1, r0, lsl #16
 989         EOP_STR_IMM(1,7,0x400+6*4);             // str  r1, [r7, #(0x400+6*8)]
 990         hostreg_r[1] = -1;
 991 */
 992 }
 993
 994 static void tr_r0_to_AL(int const_val)
 995 {
 996         EOP_MOV_REG_LSR(5, 5, 16);              // mov  r5, r5, lsr #16
 997         EOP_ORR_REG_LSL(5, 5, 0, 16);           // orr  r5, r5, r0, lsl #16
 998         EOP_MOV_REG_ROR(5, 5, 16);              // mov  r5, r5, ror #16
 999         hostreg_sspreg_changed(SSP_AL);
1000         if (const_val != -1) {
1001                 known_regs.gr[SSP_A].l = const_val;
1002                 known_regb |= 1 << SSP_AL;
1003         } else
1004                 known_regb &= ~(1 << SSP_AL);
1005 }
1006
1007 static void tr_r0_to_PMX(int reg)
1008 {
1009         if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1010         {
1011                 known_regs.pmac_write[reg] = known_regs.pmc.v;
1012                 known_regs.emu_status &= ~SSP_PMC_SET;
1013                 known_regb |= 1 << (25+reg);
1014                 dirty_regb |= 1 << (25+reg);
1015                 return;
1016         }
1017
1018         if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1019         {
1020                 int mode, addr;
1021
1022                 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1023
1024                 mode = known_regs.pmac_write[reg]>>16;
1025                 addr = known_regs.pmac_write[reg]&0xffff;
1026                 if      ((mode & 0x43ff) == 0x0018) // DRAM
1027                 {
1028                         int inc = get_inc(mode);
1029                         if (mode & 0x0400) tr_unhandled();
1030                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1031                         emit_mov_const(A_COND_AL, 2, addr<<1);
1032                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1033                         known_regs.pmac_write[reg] += inc;
1034                 }
1035                 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1036                 {
1037                         if (mode & 0x0400) tr_unhandled();
1038                         EOP_LDR_IMM(1,7,0x490);         // dram_ptr
1039                         emit_mov_const(A_COND_AL, 2, addr<<1);
1040                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1041                         known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1042                 }
1043                 else if ((mode & 0x47ff) == 0x001c) // IRAM
1044                 {
1045                         int inc = get_inc(mode);
1046                         EOP_LDR_IMM(1,7,0x48c);         // iram_ptr
1047                         emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
1048                         EOP_STRH_REG(0,1,2);            // strh r0, [r1, r2]
1049                         EOP_MOV_IMM(1,0,1);
1050                         EOP_STR_IMM(1,7,0x494);         // iram_dirty
1051                         known_regs.pmac_write[reg] += inc;
1052                 }
1053                 else
1054                         tr_unhandled();
1055
1056                 known_regs.pmc.v = known_regs.pmac_write[reg];
1057                 //known_regb |= KRREG_PMC;
1058                 dirty_regb |= KRREG_PMC;
1059                 dirty_regb |= 1 << (25+reg);
1060                 hostreg_r[1] = hostreg_r[2] = -1;
1061                 return;
1062         }
1063
1064         known_regb &= ~KRREG_PMC;
1065         dirty_regb &= ~KRREG_PMC;
1066         known_regb &= ~(1 << (25+reg));
1067         dirty_regb &= ~(1 << (25+reg));
1068
1069         // call the C code to handle this
1070         tr_flush_dirty_ST();
1071         //tr_flush_dirty_pmcrs();
1072         tr_mov16(1, reg);
1073         emit_call(A_COND_AL, ssp_pm_write);
1074         hostreg_clear();
1075 }
1076
1077 static void tr_r0_to_PM0(int const_val)
1078 {
1079         tr_r0_to_PMX(0);
1080 }
1081
1082 static void tr_r0_to_PM1(int const_val)
1083 {
1084         tr_r0_to_PMX(1);
1085 }
1086
1087 static void tr_r0_to_PM2(int const_val)
1088 {
1089         tr_r0_to_PMX(2);
1090 }
1091
1092 static void tr_r0_to_PM4(int const_val)
1093 {
1094         tr_r0_to_PMX(4);
1095 }
1096
1097 static void tr_r0_to_PMC(int const_val)
1098 {
1099         if ((known_regb & KRREG_PMC) && const_val != -1)
1100         {
1101                 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1102                         known_regs.emu_status |= SSP_PMC_SET;
1103                         known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1104                         known_regs.pmc.h = const_val;
1105                 } else {
1106                         known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1107                         known_regs.pmc.l = const_val;
1108                 }
1109         }
1110         else
1111         {
1112                 tr_flush_dirty_ST();
1113                 if (known_regb & KRREG_PMC) {
1114                         emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1115                         EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1116                         known_regb &= ~KRREG_PMC;
1117                         dirty_regb &= ~KRREG_PMC;
1118                 }
1119                 EOP_LDR_IMM(1,7,0x484);                 // ldr r1, [r7, #0x484] // emu_status
1120                 EOP_ADD_IMM(2,7,24/2,4);                // add r2, r7, #0x400
1121                 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1122                 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4);         // strxx r0, [r2, #SSP_PMC]
1123                 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1124                 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1125                 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1126                 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET);       // orrne r1, r1, #..
1127                 EOP_STR_IMM(1,7,0x484);
1128                 hostreg_r[1] = hostreg_r[2] = -1;
1129         }
1130 }
1131
1132 typedef void (tr_write_func)(int const_val);
1133
1134 static tr_write_func *tr_write_funcs[16] =
1135 {
1136         tr_r0_to_GR0,
1137         tr_r0_to_X,
1138         tr_r0_to_Y,
1139         tr_r0_to_A,
1140         tr_r0_to_ST,
1141         tr_r0_to_STACK,
1142         tr_r0_to_PC,
1143         (tr_write_func *)tr_unhandled,
1144         tr_r0_to_PM0,
1145         tr_r0_to_PM1,
1146         tr_r0_to_PM2,
1147         (tr_write_func *)tr_unhandled,
1148         tr_r0_to_PM4,
1149         (tr_write_func *)tr_unhandled,
1150         tr_r0_to_PMC,
1151         tr_r0_to_AL
1152 };
1153
1154 static void tr_mac_load_XY(int op)
1155 {
1156         tr_rX_read(op&3, (op>>2)&3); // X
1157         EOP_MOV_REG_LSL(4, 0, 16);
1158         tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1159         EOP_ORR_REG_SIMPLE(4, 0);
1160         dirty_regb |= KRREG_P;
1161         hostreg_sspreg_changed(SSP_X);
1162         hostreg_sspreg_changed(SSP_Y);
1163         known_regb &= ~KRREG_X;
1164         known_regb &= ~KRREG_Y;
1165 }
1166
1167 // -----------------------------------------------------
1168
1169 static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
1170 {
1171         u32 pmcv, tmpv;
1172         if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1173
1174         // programming PMC:
1175         // ldi PMC, imm1
1176         // ldi PMC, imm2
1177         (*pc)++;
1178         pmcv = imm | (PROGRAM((*pc)++) << 16);
1179         known_regs.pmc.v = pmcv;
1180         known_regb |= KRREG_PMC;
1181         dirty_regb |= KRREG_PMC;
1182         known_regs.emu_status |= SSP_PMC_SET;
1183         n_in_ops++;
1184
1185         // check for possible reg programming
1186         tmpv = PROGRAM(*pc);
1187         if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1188         {
1189                 int is_write = (tmpv & 0xff8f) == 0x80;
1190                 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1191                 if (reg > 4) tr_unhandled();
1192                 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
1193                 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1194                 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1195                 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
1196                 known_regs.emu_status &= ~SSP_PMC_SET;
1197                 (*pc)++;
1198                 n_in_ops++;
1199                 return 5;
1200         }
1201
1202         tr_unhandled();
1203         return 4;
1204 }
1205
1206 static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1207
1208 static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1209 {
1210         // ldi ST, 0
1211         // ldi PM0, 0
1212         // ldi PM0, 0
1213         // ldi ST, 60h
1214         unsigned short *pp;
1215         if (op != 0x0840 || imm != 0) return 0;
1216         pp = PROGRAM_P(*pc);
1217         if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1218
1219         EOP_AND_IMM(6, 6, 8/2, 0xe0);           // and   r6, r6, #7<<29     @ preserve STACK
1220         EOP_ORR_IMM(6, 6, 24/2, 6);             // orr   r6, r6, 0x600
1221         hostreg_sspreg_changed(SSP_ST);
1222         known_regs.gr[SSP_ST].h = 0x60;
1223         known_regb |= 1 << SSP_ST;
1224         dirty_regb &= ~KRREG_ST;
1225         (*pc) += 3*2;
1226         n_in_ops += 3;
1227         return 4*2;
1228 }
1229
1230 static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1231 {
1232         // @ 3DA2 and 426A
1233         // ld PMC, (r3|00)
1234         // ld (r3|00), PMC
1235         // ld -, AL
1236         if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1237
1238         tr_bank_read(0);
1239         EOP_MOV_REG_LSL(0, 0, 4);
1240         EOP_ORR_REG_LSR(0, 0, 0, 16);
1241         tr_bank_write(0);
1242         (*pc) += 2;
1243         n_in_ops += 2;
1244         return 3;
1245 }
1246
1247 // -----------------------------------------------------
1248
1249 static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
1250 {
1251         u32 tmpv, tmpv2, tmpv3;
1252         int ret = 0;
1253         known_regs.gr[SSP_PC].h = *pc;
1254
1255         switch (op >> 9)
1256         {
1257                 // ld d, s
1258                 case 0x00:
1259                         if (op == 0) { ret++; break; } // nop
1260                         tmpv  = op & 0xf; // src
1261                         tmpv2 = (op >> 4) & 0xf; // dst
1262                         if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1263                                 tr_flush_dirty_P();
1264                                 EOP_MOV_REG_SIMPLE(5, 10);
1265                                 hostreg_sspreg_changed(SSP_A);
1266                                 known_regb &= ~(KRREG_A|KRREG_AL);
1267                                 ret++; break;
1268                         }
1269                         tr_read_funcs[tmpv](op);
1270                         tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
1271                         if (tmpv2 == SSP_PC) {
1272                                 ret |= 0x10000;
1273                                 *end_cond = -A_COND_AL;
1274                         }
1275                         ret++; break;
1276
1277                 // ld d, (ri)
1278                 case 0x01: {
1279                         int r = (op&3) | ((op>>6)&4);
1280                         int mod = (op>>2)&3;
1281                         tmpv = (op >> 4) & 0xf; // dst
1282                         ret = tr_detect_rotate(op, pc, imm);
1283                         if (ret > 0) break;
1284                         if (tmpv != 0)
1285                                 tr_rX_read(r, mod);
1286                         else {
1287                                 int cnt = 1;
1288                                 while (PROGRAM(*pc) == op) {
1289                                         (*pc)++; cnt++; ret++;
1290                                         n_in_ops++;
1291                                 }
1292                                 tr_ptrr_mod(r, mod, 1, cnt); // skip
1293                         }
1294                         tr_write_funcs[tmpv](-1);
1295                         if (tmpv == SSP_PC) {
1296                                 ret |= 0x10000;
1297                                 *end_cond = -A_COND_AL;
1298                         }
1299                         ret++; break;
1300                 }
1301
1302                 // ld (ri), s
1303                 case 0x02:
1304                         tmpv = (op >> 4) & 0xf; // src
1305                         tr_read_funcs[tmpv](op);
1306                         tr_rX_write(op);
1307                         ret++; break;
1308
1309                 // ld a, adr
1310                 case 0x03:
1311                         tr_bank_read(op&0x1ff);
1312                         tr_r0_to_A(-1);
1313                         ret++; break;
1314
1315                 // ldi d, imm
1316                 case 0x04:
1317                         tmpv = (op & 0xf0) >> 4; // dst
1318                         ret = tr_detect_pm0_block(op, pc, imm);
1319                         if (ret > 0) break;
1320                         ret = tr_detect_set_pm(op, pc, imm);
1321                         if (ret > 0) break;
1322                         tr_mov16(0, imm);
1323                         tr_write_funcs[tmpv](imm);
1324                         if (tmpv == SSP_PC) {
1325                                 ret |= 0x10000;
1326                                 *jump_pc = imm;
1327                         }
1328                         ret += 2; break;
1329
1330                 // ld d, ((ri))
1331                 case 0x05:
1332                         tmpv2 = (op >> 4) & 0xf;  // dst
1333                         tr_rX_read2(op);
1334                         tr_write_funcs[tmpv2](-1);
1335                         if (tmpv2 == SSP_PC) {
1336                                 ret |= 0x10000;
1337                                 *end_cond = -A_COND_AL;
1338                         }
1339                         ret += 3; break;
1340
1341                 // ldi (ri), imm
1342                 case 0x06:
1343                         tr_mov16(0, imm);
1344                         tr_rX_write(op);
1345                         ret += 2; break;
1346
1347                 // ld adr, a
1348                 case 0x07:
1349                         tr_A_to_r0(op);
1350                         tr_bank_write(op&0x1ff);
1351                         ret++; break;
1352
1353                 // ld d, ri
1354                 case 0x09: {
1355                         int r;
1356                         r = (op&3) | ((op>>6)&4); // src
1357                         tmpv2 = (op >> 4) & 0xf;  // dst
1358                         if ((r&3) == 3) tr_unhandled();
1359
1360                         if (known_regb & (1 << (r+8))) {
1361                                 tr_mov16(0, known_regs.r[r]);
1362                                 tr_write_funcs[tmpv2](known_regs.r[r]);
1363                         } else {
1364                                 int reg = (r < 4) ? 8 : 9;
1365                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1366                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1367                                 hostreg_r[0] = -1;
1368                                 tr_write_funcs[tmpv2](-1);
1369                         }
1370                         ret++; break;
1371                 }
1372
1373                 // ld ri, s
1374                 case 0x0a: {
1375                         int r;
1376                         r = (op&3) | ((op>>6)&4); // dst
1377                         tmpv = (op >> 4) & 0xf;   // src
1378                         if ((r&3) == 3) tr_unhandled();
1379
1380                         if (known_regb & (1 << tmpv)) {
1381                                 known_regs.r[r] = known_regs.gr[tmpv].h;
1382                                 known_regb |= 1 << (r + 8);
1383                                 dirty_regb |= 1 << (r + 8);
1384                         } else {
1385                                 int reg = (r < 4) ? 8 : 9;
1386                                 int ror = ((4 - (r&3))*8) & 0x1f;
1387                                 tr_read_funcs[tmpv](op);
1388                                 EOP_BIC_IMM(reg, reg, ror/2, 0xff);             // bic r{7,8}, r{7,8}, <mask>
1389                                 EOP_AND_IMM(0, 0, 0, 0xff);                     // and r0, r0, 0xff
1390                                 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8);          // orr r{7,8}, r{7,8}, r0, lsl #lsl
1391                                 hostreg_r[0] = -1;
1392                                 known_regb &= ~(1 << (r+8));
1393                                 dirty_regb &= ~(1 << (r+8));
1394                         }
1395                         ret++; break;
1396                 }
1397
1398                 // ldi ri, simm
1399                 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1400                         tmpv = (op>>8)&7;
1401                         known_regs.r[tmpv] = op;
1402                         known_regb |= 1 << (tmpv + 8);
1403                         dirty_regb |= 1 << (tmpv + 8);
1404                         ret++; break;
1405
1406                 // call cond, addr
1407                 case 0x24: {
1408                         u32 *jump_op = NULL;
1409                         tmpv = tr_cond_check(op);
1410                         if (tmpv != A_COND_AL) {
1411                                 jump_op = tcache_ptr;
1412                                 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1413                         }
1414                         tr_mov16(0, *pc);
1415                         tr_r0_to_STACK(*pc);
1416                         if (tmpv != A_COND_AL) {
1417                                 u32 *real_ptr = tcache_ptr;
1418                                 tcache_ptr = jump_op;
1419                                 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1420                                 tcache_ptr = real_ptr;
1421                         }
1422                         tr_mov16_cond(tmpv, 0, imm);
1423                         if (tmpv != A_COND_AL)
1424                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1425                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1426                         ret |= 0x10000;
1427                         *end_cond = tmpv;
1428                         *jump_pc = imm;
1429                         ret += 2; break;
1430                 }
1431
1432                 // ld d, (a)
1433                 case 0x25:
1434                         tmpv2 = (op >> 4) & 0xf;  // dst
1435                         tr_A_to_r0(op);
1436                         EOP_LDR_IMM(1,7,0x48c);                                 // ptr_iram_rom
1437                         EOP_ADD_REG_LSL(0,1,0,1);                               // add  r0, r1, r0, lsl #1
1438                         EOP_LDRH_SIMPLE(0,0);                                   // ldrh r0, [r0]
1439                         hostreg_r[0] = hostreg_r[1] = -1;
1440                         tr_write_funcs[tmpv2](-1);
1441                         if (tmpv2 == SSP_PC) {
1442                                 ret |= 0x10000;
1443                                 *end_cond = -A_COND_AL;
1444                         }
1445                         ret += 3; break;
1446
1447                 // bra cond, addr
1448                 case 0x26:
1449                         tmpv = tr_cond_check(op);
1450                         tr_mov16_cond(tmpv, 0, imm);
1451                         if (tmpv != A_COND_AL)
1452                                 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
1453                         tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
1454                         ret |= 0x10000;
1455                         *end_cond = tmpv;
1456                         *jump_pc = imm;
1457                         ret += 2; break;
1458
1459                 // mod cond, op
1460                 case 0x48: {
1461                         // check for repeats of this op
1462                         tmpv = 1; // count
1463                         while (PROGRAM(*pc) == op && (op & 7) != 6) {
1464                                 (*pc)++; tmpv++;
1465                                 n_in_ops++;
1466                         }
1467                         if ((op&0xf0) != 0) // !always
1468                                 tr_make_dirty_ST();
1469
1470                         tmpv2 = tr_cond_check(op);
1471                         switch (op & 7) {
1472                                 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1473                                 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1474                                 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
1475                                 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor  r1, r5, r5, asr #31
1476                                         EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
1477                                         hostreg_r[1] = -1; break; // abs
1478                                 default: tr_unhandled();
1479                         }
1480
1481                         hostreg_sspreg_changed(SSP_A);
1482                         dirty_regb |=  KRREG_ST;
1483                         known_regb &= ~KRREG_ST;
1484                         known_regb &= ~(KRREG_A|KRREG_AL);
1485                         ret += tmpv; break;
1486                 }
1487
1488                 // mpys?
1489                 case 0x1b:
1490                         tr_flush_dirty_P();
1491                         tr_mac_load_XY(op);
1492                         tr_make_dirty_ST();
1493                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1494                         hostreg_sspreg_changed(SSP_A);
1495                         known_regb &= ~(KRREG_A|KRREG_AL);
1496                         dirty_regb |= KRREG_ST;
1497                         ret++; break;
1498
1499                 // mpya (rj), (ri), b
1500                 case 0x4b:
1501                         tr_flush_dirty_P();
1502                         tr_mac_load_XY(op);
1503                         tr_make_dirty_ST();
1504                         EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1505                         hostreg_sspreg_changed(SSP_A);
1506                         known_regb &= ~(KRREG_A|KRREG_AL);
1507                         dirty_regb |= KRREG_ST;
1508                         ret++; break;
1509
1510                 // mld (rj), (ri), b
1511                 case 0x5b:
1512                         EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1513                         hostreg_sspreg_changed(SSP_A);
1514                         known_regs.gr[SSP_A].v = 0;
1515                         known_regb |= (KRREG_A|KRREG_AL);
1516                         dirty_regb |= KRREG_ST;
1517                         tr_mac_load_XY(op);
1518                         ret++; break;
1519
1520                 // OP a, s
1521                 case 0x10:
1522                 case 0x30:
1523                 case 0x40:
1524                 case 0x50:
1525                 case 0x60:
1526                 case 0x70:
1527                         tmpv = op & 0xf; // src
1528                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1529                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1530                         if (tmpv == SSP_P) {
1531                                 tr_flush_dirty_P();
1532                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1533                         } else if (tmpv == SSP_A) {
1534                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1535                         } else {
1536                                 tr_read_funcs[tmpv](op);
1537                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1538                         }
1539                         hostreg_sspreg_changed(SSP_A);
1540                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1541                         dirty_regb |= KRREG_ST;
1542                         ret++; break;
1543
1544                 // OP a, (ri)
1545                 case 0x11:
1546                 case 0x31:
1547                 case 0x41:
1548                 case 0x51:
1549                 case 0x61:
1550                 case 0x71:
1551                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1552                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1553                         tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1554                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1555                         hostreg_sspreg_changed(SSP_A);
1556                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1557                         dirty_regb |= KRREG_ST;
1558                         ret++; break;
1559
1560                 // OP a, adr
1561                 case 0x13:
1562                 case 0x33:
1563                 case 0x43:
1564                 case 0x53:
1565                 case 0x63:
1566                 case 0x73:
1567                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1568                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1569                         tr_bank_read(op&0x1ff);
1570                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1571                         hostreg_sspreg_changed(SSP_A);
1572                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1573                         dirty_regb |= KRREG_ST;
1574                         ret++; break;
1575
1576                 // OP a, imm
1577                 case 0x14:
1578                 case 0x34:
1579                 case 0x44:
1580                 case 0x54:
1581                 case 0x64:
1582                 case 0x74:
1583                         tmpv = (op & 0xf0) >> 4;
1584                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1585                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1586                         tr_mov16(0, imm);
1587                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1588                         hostreg_sspreg_changed(SSP_A);
1589                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1590                         dirty_regb |= KRREG_ST;
1591                         ret += 2; break;
1592
1593                 // OP a, ((ri))
1594                 case 0x15:
1595                 case 0x35:
1596                 case 0x45:
1597                 case 0x55:
1598                 case 0x65:
1599                 case 0x75:
1600                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1601                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1602                         tr_rX_read2(op);
1603                         EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1604                         hostreg_sspreg_changed(SSP_A);
1605                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1606                         dirty_regb |= KRREG_ST;
1607                         ret += 3; break;
1608
1609                 // OP a, ri
1610                 case 0x19:
1611                 case 0x39:
1612                 case 0x49:
1613                 case 0x59:
1614                 case 0x69:
1615                 case 0x79: {
1616                         int r;
1617                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1618                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1619                         r = (op&3) | ((op>>6)&4); // src
1620                         if ((r&3) == 3) tr_unhandled();
1621
1622                         if (known_regb & (1 << (r+8))) {
1623                                 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]);  // OPs r5, r5, #val<<16
1624                         } else {
1625                                 int reg = (r < 4) ? 8 : 9;
1626                                 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8);      // mov r0, r{7,8}, lsr #lsr
1627                                 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff);           // and r0, r{7,8}, <mask>
1628                                 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0);   // OPs r5, r5, r0, lsl #16
1629                                 hostreg_r[0] = -1;
1630                         }
1631                         hostreg_sspreg_changed(SSP_A);
1632                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1633                         dirty_regb |= KRREG_ST;
1634                         ret++; break;
1635                 }
1636
1637                 // OP simm
1638                 case 0x1c:
1639                 case 0x3c:
1640                 case 0x4c:
1641                 case 0x5c:
1642                 case 0x6c:
1643                 case 0x7c:
1644                         tmpv2 = tr_aop_ssp2arm(op>>13); // op
1645                         tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1646                         EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff);        // OPs r5, r5, #val<<16
1647                         hostreg_sspreg_changed(SSP_A);
1648                         known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1649                         dirty_regb |= KRREG_ST;
1650                         ret++; break;
1651         }
1652
1653         n_in_ops++;
1654
1655         return ret;
1656 }
1657
1658 static void emit_block_prologue(void)
1659 {
1660         // check if there are enough cycles..
1661         // note: r0 must contain PC of current block
1662         EOP_CMP_IMM(11,0,0);                    // cmp r11, #0
1663         emit_jump(A_COND_LE, ssp_drc_end);
1664 }
1665
1666 /* cond:
1667  * >0: direct (un)conditional jump
1668  * <0: indirect jump
1669  */
1670 static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1671 {
1672         if (cycles > 0xff) { elprintf(EL_ANOMALY, "large cycle count: %i\n", cycles); cycles = 0xff; }
1673         EOP_SUB_IMM(11,11,0,cycles);            // sub r11, r11, #cycles
1674
1675         if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1676                 // indirect jump, or rom -> iram jump, must use dispatcher
1677                 emit_jump(A_COND_AL, ssp_drc_next);
1678         }
1679         else if (cond == A_COND_AL) {
1680                 u32 *target = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1681                 if (target != NULL)
1682                         emit_jump(A_COND_AL, target);
1683                 else {
1684                         int ops = emit_jump(A_COND_AL, ssp_drc_next);
1685                         // cause the next block to be emitted over jump instruction
1686                         tcache_ptr -= ops;
1687                 }
1688         }
1689         else {
1690                 u32 *target1 = (pc     < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1691                 u32 *target2 = (end_pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][end_pc] : ssp_block_table[end_pc];
1692                 if (target1 != NULL)
1693                      emit_jump(cond, target1);
1694                 if (target2 != NULL)
1695                      emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1696 #ifndef __EPOC32__
1697                 // emit patchable branches
1698                 if (target1 == NULL)
1699                         emit_call(cond, ssp_drc_next_patch);
1700                 if (target2 == NULL)
1701                         emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1702 #else
1703                 // won't patch indirect jumps
1704                 if (target1 == NULL || target2 == NULL)
1705                         emit_jump(A_COND_AL, ssp_drc_next);
1706 #endif
1707         }
1708 }
1709
1710 void *ssp_translate_block(int pc)
1711 {
1712         unsigned int op, op1, imm, ccount = 0;
1713         unsigned int *block_start;
1714         int ret, end_cond = A_COND_AL, jump_pc = -1;
1715
1716         //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
1717
1718         block_start = tcache_ptr;
1719         known_regb = 0;
1720         dirty_regb = KRREG_P;
1721         known_regs.emu_status = 0;
1722         hostreg_clear();
1723
1724         emit_block_prologue();
1725
1726         for (; ccount < 100;)
1727         {
1728                 op = PROGRAM(pc++);
1729                 op1 = op >> 9;
1730                 imm = (u32)-1;
1731
1732                 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1733                         imm = PROGRAM(pc++); // immediate
1734
1735                 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
1736                 if (ret <= 0)
1737                 {
1738                         elprintf(EL_ANOMALY, "NULL func! op=%08x (%02x)\n", op, op1);
1739                         //exit(1);
1740                 }
1741
1742                 ccount += ret & 0xffff;
1743                 if (ret & 0x10000) break;
1744         }
1745
1746         if (ccount >= 100) {
1747                 end_cond = A_COND_AL;
1748                 jump_pc = pc;
1749                 emit_mov_const(A_COND_AL, 0, pc);
1750         }
1751
1752         tr_flush_dirty_prs();
1753         tr_flush_dirty_ST();
1754         tr_flush_dirty_pmcrs();
1755         emit_block_epilogue(ccount, end_cond, jump_pc, pc);
1756
1757         if (tcache_ptr - tcache > SSP_TCACHE_SIZE/4) {
1758                 elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n");
1759                 fflush(stdout);
1760                 exit(1);
1761         }
1762
1763         // stats
1764         nblocks++;
1765         //printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1766         //      (double)(tcache_ptr - tcache) / (double)n_in_ops);
1767
1768 #ifdef DUMP_BLOCK
1769         {
1770                 FILE *f = fopen("tcache.bin", "wb");
1771                 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1772                 fclose(f);
1773         }
1774         printf("dumped tcache.bin\n");
1775         exit(0);
1776 #endif
1777
1778         handle_caches();
1779
1780         return block_start;
1781 }
1782
1783
1784
1785 // -----------------------------------------------------
1786
1787 static void ssp1601_state_load(void)
1788 {
1789         ssp->drc.iram_dirty = 1;
1790         ssp->drc.iram_context = 0;
1791 }
1792
1793 int ssp1601_dyn_startup(void)
1794 {
1795         drc_cmn_init();
1796
1797         memset(tcache, 0, SSP_TCACHE_SIZE);
1798         memset(ssp_block_table, 0, sizeof(ssp_block_table));
1799         memset(ssp_block_table_iram, 0, sizeof(ssp_block_table_iram));
1800         tcache_ptr = tcache;
1801
1802         PicoLoadStateHook = ssp1601_state_load;
1803
1804         n_in_ops = 0;
1805 #ifdef ARM
1806         // hle'd blocks
1807         ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1808         ssp_block_table[0x902/2] = (void *) ssp_hle_902;
1809         ssp_block_table_iram[ 7][0x030/2] = (void *) ssp_hle_07_030;
1810         ssp_block_table_iram[ 7][0x036/2] = (void *) ssp_hle_07_036;
1811         ssp_block_table_iram[ 7][0x6d6/2] = (void *) ssp_hle_07_6d6;
1812         ssp_block_table_iram[11][0x12c/2] = (void *) ssp_hle_11_12c;
1813         ssp_block_table_iram[11][0x384/2] = (void *) ssp_hle_11_384;
1814         ssp_block_table_iram[11][0x38a/2] = (void *) ssp_hle_11_38a;
1815 #endif
1816
1817         return 0;
1818 }
1819
1820
1821 void ssp1601_dyn_reset(ssp1601_t *ssp)
1822 {
1823         ssp1601_reset(ssp);
1824         ssp->drc.iram_dirty = 1;
1825         ssp->drc.iram_context = 0;
1826         // must do this here because ssp is not available @ startup()
1827         ssp->drc.ptr_rom = (u32) Pico.rom;
1828         ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1829         ssp->drc.ptr_dram = (u32) svp->dram;
1830         ssp->drc.ptr_btable = (u32) ssp_block_table;
1831         ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
1832
1833         // prevent new versions of IRAM from appearing
1834         memset(svp->iram_rom, 0, 0x800);
1835 }
1836
1837
1838 void ssp1601_dyn_run(int cycles)
1839 {
1840         if (ssp->emu_status & SSP_WAIT_MASK) return;
1841
1842 #ifdef DUMP_BLOCK
1843         ssp_translate_block(DUMP_BLOCK >> 1);
1844 #endif
1845 #ifdef ARM
1846         ssp_drc_entry(cycles);
1847 #endif
1848 }
1849