pico/carthw/svp/gen_arm.c

   1 // Basic macros to emit ARM instructions and some utils
   2
   3 // (c) Copyright 2008, Grazvydas "notaz" Ignotas
   4 // Free for non-commercial use.
   5
   6 #define EMIT(x) *tcache_ptr++ = x
   7
   8 #define A_R4M  (1 << 4)
   9 #define A_R5M  (1 << 5)
  10 #define A_R6M  (1 << 6)
  11 #define A_R7M  (1 << 7)
  12 #define A_R8M  (1 << 8)
  13 #define A_R9M  (1 << 9)
  14 #define A_R10M (1 << 10)
  15 #define A_R11M (1 << 11)
  16 #define A_R14M (1 << 14)
  17
  18 #define A_COND_AL 0xe
  19 #define A_COND_EQ 0x0
  20 #define A_COND_NE 0x1
  21 #define A_COND_MI 0x4
  22 #define A_COND_PL 0x5
  23 #define A_COND_LE 0xd
  24
  25 /* addressing mode 1 */
  26 #define A_AM1_LSL 0
  27 #define A_AM1_LSR 1
  28 #define A_AM1_ASR 2
  29 #define A_AM1_ROR 3
  30
  31 #define A_AM1_IMM(ror2,imm8)                  (((ror2)<<8) | (imm8) | 0x02000000)
  32 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
  33 #define A_AM1_REG_XREG(rs,shift_op,rm)        (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
  34
  35 /* data processing op */
  36 #define A_OP_AND 0x0
  37 #define A_OP_EOR 0x1
  38 #define A_OP_SUB 0x2
  39 #define A_OP_RSB 0x3
  40 #define A_OP_ADD 0x4
  41 #define A_OP_TST 0x8
  42 #define A_OP_CMP 0xa
  43 #define A_OP_ORR 0xc
  44 #define A_OP_MOV 0xd
  45 #define A_OP_BIC 0xe
  46
  47 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
  48         EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
  49
  50 #define EOP_C_DOP_IMM(     cond,op,s,rn,rd,ror2,imm8)             EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
  51 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
  52 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs,       shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs,       shift_op,rm))
  53
  54 #define EOP_MOV_IMM(rd,   ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
  55 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
  56 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
  57 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
  58 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
  59 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
  60 #define EOP_TST_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
  61 #define EOP_CMP_IMM(   rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
  62 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
  63
  64 #define EOP_MOV_REG(s,   rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
  65 #define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
  66 #define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
  67 #define EOP_TST_REG(  rn,   shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
  68
  69 #define EOP_MOV_REG2(s,   rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
  70 #define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
  71 #define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
  72
  73 #define EOP_MOV_REG_SIMPLE(rd,rm)           EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
  74 #define EOP_MOV_REG_LSL(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
  75 #define EOP_MOV_REG_LSR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
  76 #define EOP_MOV_REG_ASR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
  77 #define EOP_MOV_REG_ROR(rd,   rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
  78
  79 #define EOP_ORR_REG_SIMPLE(rd,rm)           EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
  80 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  81 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  82 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
  83 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
  84
  85 #define EOP_ADD_REG_SIMPLE(rd,rm)           EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
  86 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
  87 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
  88
  89 #define EOP_TST_REG_SIMPLE(rn,rm)           EOP_TST_REG(  rn,   0,A_AM1_LSL,rm)
  90
  91 #define EOP_MOV_REG2_LSL(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_LSL,rm)
  92 #define EOP_MOV_REG2_ROR(rd,   rm,rs)       EOP_MOV_REG2(0,   rd,rs,A_AM1_ROR,rm)
  93 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs)       EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
  94 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs)       EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
  95
  96 /* addressing mode 2 */
  97 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
  98         EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
  99
 100 /* addressing mode 3 */
 101 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
 102         EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
 103                         ((s)<<6) | ((h)<<5) | (immed_reg))
 104
 105 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
 106
 107 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm)       EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
 108
 109 /* ldr and str */
 110 #define EOP_LDR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
 111 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
 112 #define EOP_LDR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
 113 #define EOP_STR_IMM(   rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
 114 #define EOP_STR_SIMPLE(rd,rn)           EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
 115
 116 #define EOP_LDRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
 117 #define EOP_LDRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
 118 #define EOP_LDRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
 119 #define EOP_STRH_IMM(   rd,rn,offset_8)  EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
 120 #define EOP_STRH_SIMPLE(rd,rn)           EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
 121 #define EOP_STRH_REG(   rd,rn,rm)        EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
 122
 123 /* ldm and stm */
 124 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
 125         EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
 126
 127 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
 128 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
 129
 130 /* branches */
 131 #define EOP_C_BX(cond,rm) \
 132         EMIT(((cond)<<28) | 0x012fff10 | (rm))
 133
 134 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
 135
 136 #define EOP_C_B(cond,l,signed_immed_24) \
 137         EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
 138
 139 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
 140 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
 141
 142 /* misc */
 143 #define EOP_C_MUL(cond,s,rd,rs,rm) \
 144         EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
 145
 146 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
 147
 148 #define EOP_C_MRS(cond,rd) \
 149         EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
 150
 151 #define EOP_C_MSR_IMM(cond,ror2,imm) \
 152         EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
 153
 154 #define EOP_C_MSR_REG(cond,rm) \
 155         EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
 156
 157 #define EOP_MRS(rd)           EOP_C_MRS(A_COND_AL,rd)
 158 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
 159 #define EOP_MSR_REG(rm)       EOP_C_MSR_REG(A_COND_AL,rm)
 160
 161
 162 static void emit_mov_const(int cond, int d, unsigned int val)
 163 {
 164         int need_or = 0;
 165         if (val & 0xff000000) {
 166                 EOP_C_DOP_IMM(cond, A_OP_MOV, 0, 0, d, 8/2, (val>>24)&0xff);
 167                 need_or = 1;
 168         }
 169         if (val & 0x00ff0000) {
 170                 EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
 171                 need_or = 1;
 172         }
 173         if (val & 0x0000ff00) {
 174                 EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
 175                 need_or = 1;
 176         }
 177         if ((val &0x000000ff) || !need_or)
 178                 EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
 179 }
 180
 181 static int is_offset_24(int val)
 182 {
 183         if (val >= (int)0xff000000 && val <= 0x00ffffff) return 1;
 184         return 0;
 185 }
 186
 187 static int emit_xbranch(int cond, void *target, int is_call)
 188 {
 189         int val = (unsigned int *)target - tcache_ptr - 2;
 190         int direct = is_offset_24(val);
 191         u32 *start_ptr = tcache_ptr;
 192
 193         if (direct)
 194         {
 195                 EOP_C_B(cond,is_call,val & 0xffffff);           // b, bl target
 196         }
 197         else
 198         {
 199 #ifdef __EPOC32__
 200 //              elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
 201                 if (is_call)
 202                         EOP_ADD_IMM(14,15,0,8);                 // add lr,pc,#8
 203                 EOP_C_AM2_IMM(cond,1,0,1,15,15,0);              // ldrcc pc,[pc]
 204                 EOP_MOV_REG_SIMPLE(15,15);                      // mov pc, pc
 205                 EMIT((u32)target);
 206 #else
 207                 // should never happen
 208                 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
 209                 exit(1);
 210 #endif
 211         }
 212
 213         return tcache_ptr - start_ptr;
 214 }
 215
 216 static int emit_call(int cond, void *target)
 217 {
 218         return emit_xbranch(cond, target, 1);
 219 }
 220
 221 static int emit_jump(int cond, void *target)
 222 {
 223         return emit_xbranch(cond, target, 0);
 224 }
 225
 226 static void handle_caches(void)
 227 {
 228 #ifdef ARM
 229         extern void cache_flush_d_inval_i(const void *start_addr, const void *end_addr);
 230         cache_flush_d_inval_i(tcache, tcache_ptr);
 231 #endif
 232 }
 233
 234