3 @ Compiler helper functions and some SVP HLE code
5 @ (c) Copyright 2008, Grazvydas "notaz" Ignotas
6 @ Free for non-commercial use.
10 .global ssp_drc_next_patch
14 .global ssp_hle_07_030
15 .global ssp_hle_07_036
16 .global ssp_hle_07_6d6
17 .global ssp_hle_11_12c
18 .global ssp_hle_11_384
19 .global ssp_hle_11_38a
24 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
25 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
26 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
27 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
32 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
41 #define SSP_OFFS_GR 0x400
46 #define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
47 #define SSP_OFFS_EMUSTAT 0x484 // emu_status
48 #define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
49 #define SSP_OFFS_DRAM 0x490 // ptr_dram
50 #define SSP_OFFS_IRAM_DIRTY 0x494
51 #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
52 #define SSP_OFFS_BLTAB 0x49c // block_table
53 #define SSP_OFFS_BLTAB_IRAM 0x4a0
54 #define SSP_OFFS_TMP0 0x4a4 // for entry PC
55 #define SSP_OFFS_TMP1 0x4a8
56 #define SSP_OFFS_TMP2 0x4ac
57 #define SSP_WAIT_PM0 0x2000
60 .macro ssp_drc_do_next patch_jump=0
62 str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
66 str r0, [r7, #SSP_OFFS_TMP0]
70 ldr r2, [r7, #SSP_OFFS_BLTAB]
71 ldr r2, [r2, r0, lsl #2]
78 bl ssp_translate_block
80 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
81 ldr r1, [r7, #SSP_OFFS_BLTAB]
82 str r2, [r1, r0, lsl #2]
90 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
92 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
93 beq 1f @ ssp_de_iram_ctx
95 bl ssp_get_iram_context
97 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
99 str r1, [r7, #SSP_OFFS_IRAM_CTX]
100 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
102 1: @ ssp_de_iram_ctx:
103 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
104 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
105 add r1, r2, r0, lsl #2
113 str r1, [r7, #SSP_OFFS_TMP1]
114 bl ssp_translate_block
116 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
117 ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
124 .endm @ ssp_drc_do_next
128 stmfd sp!, {r4-r11, lr}
135 ldmia r2, {r3,r4,r5,r6,r8}
138 orr r4, r3, r4, lsr #16 @ XXYY
140 and r8, r8, #0x0f0000
141 mov r8, r8, lsl #13 @ sss0 *
142 and r9, r6, #0x670000
146 orrne r8, r8, #0x4 @ sss0 * NZ..
147 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
149 ldr r8, [r7, #0x440] @ r0-r2
150 ldr r9, [r7, #0x444] @ r4-r6
151 ldr r10,[r7, #(0x400+SSP_P*4)] @ P
153 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
165 ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
167 moveq r3, #0xe1000000
168 orreq r3, r3, #0x00a00000 @ nop
175 streq r3, [r1, #-4] @ move the other cond up
176 moveq r3, #0xe1000000
177 orreq r3, r3, #0x00a00000
178 streq r3, [r1] @ fill it's place with nop
184 bic r3, r3, #1 @ L bit
185 orr r3, r3, r12,lsl #6
186 mov r3, r3, ror #8 @ patched branch instruction
187 str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
190 str r2, [r7, #SSP_OFFS_TMP1]
193 bl cache_flush_d_inval_i
194 ldr r2, [r7, #SSP_OFFS_TMP1]
195 ldr r0, [r7, #SSP_OFFS_TMP0]
201 str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
204 str r10,[r7, #(0x400+SSP_P*4)] @ P
205 str r8, [r7, #0x440] @ r0-r2
206 str r9, [r7, #0x444] @ r4-r6
209 and r9, r9, #(7<<16) @ STACK
211 msr cpsr_flg, r3 @ to to ARM PSR
214 orrmi r6, r6, #0x80000000 @ N
215 orreq r6, r6, #0x20000000 @ Z
217 mov r3, r4, lsl #16 @ Y
219 mov r2, r2, lsl #16 @ X
222 stmia r8, {r2,r3,r5,r6,r9}
225 ldmfd sp!, {r4-r11, lr}
234 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
235 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
237 orreq r1, r1, #SSP_WAIT_PM0
239 streq r1, [r7, #SSP_OFFS_EMUSTAT]
246 .macro hle_flushflags
249 orr r6, r6, r1, lsr #28
253 sub r6, r6, #0x20000000
255 add r1, r1, #0x048 @ stack
256 add r1, r1, r6, lsr #28
266 ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
267 add r2, r3, r0, lsl #1 @ (r7|00)
272 add r3, r3, r0, lsl #1 @ IRAM dest
273 ldrh r12,[r2], #2 @ length
274 bic r3, r3, #3 @ always seen aligned
275 @ orr r5, r5, #0x08000000
276 @ orr r5, r5, #0x00880000
277 @ sub r5, r5, r12, lsl #16
281 str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
282 sub r11,r11,r12,lsl #1
283 sub r11,r11,r12 @ -= length*3
289 orr r0, r0, r1, lsl #16
297 ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
301 strh r2, [r1] @ (r7|00)
305 orr r0, r0, #0x08000000
306 orr r0, r0, #0x001c8000
307 str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
308 str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
311 subs r11,r11,#16 @ timeslice is likely to end
316 @ this one is car rendering related
317 .macro hle_11_12c_mla offs_in
318 ldrsh r5, [r7, #(\offs_in+0)]
319 ldrsh r0, [r7, #(\offs_in+2)]
320 ldrsh r1, [r7, #(\offs_in+4)]
322 ldrsh r12,[r7, #(\offs_in+6)]
325 add r5, r5, r12,lsl #11
328 add r1, r7, r8, lsr #23
349 mov r2, r2, asr #15 @ (r7|00) << 1
351 mov r3, r3, asr #15 @ (r7|01) << 1
353 mov r4, r4, asr #15 @ (r7|10) << 1
381 mov r2, #0 @ EFh, EEh
383 add r0, r7, #0x1c0 @ r0 (based)
389 eor r5, r5, r5, asr #31
390 add r5, r5, r5, lsr #31 @ abs(r5)
392 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
397 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
407 bpl ssp_hle_11_38x_loop
412 orr r8, r8, r0, lsr #1
418 sub r11,r11,#(9+30*4)
427 and r0, r8, #0xff @ assuming alignment
428 add r0, r7, r0, lsl #1
430 mov r1, r1, lsl #16 @ 106h << 16
431 mov r2, r2, lsl #16 @ 107h << 16
436 bmi ssp_hle_07_6d6_end
442 bmi ssp_hle_07_6d6_loop
444 b ssp_hle_07_6d6_loop
451 orr r1, r2, r1, lsr #16
461 orr r0, r0, r0, lsr #16
466 ldr r1, [r7, #0x1e0] @ F1h F0h
467 rsb r5, r1, r1, lsr #16
468 mov r5, r5, lsl #16 @ AL not needed
471 bmi hle_07_036_ending2
472 ldr r1, [r7, #0x1dc] @ EEh
479 strh r0, [r1, #0xea] @ F5h
480 ldr r0, [r7, #0x1e0] @ F0h
482 strh r0, [r1, #0xf0] @ F8h
483 add r2, r0, #0xc0 @ r2
484 add r2, r7, r2, lsl #1
490 @ will handle PMC later
491 ldr r0, [r7, #0x1e8] @ F5h << 16
492 ldr r1, [r7, #0x1f0] @ F8h
493 ldr r2, [r7, #0x1d4] @ EAh
495 add r0, r0, r1, lsl #16
496 sub r0, r2, r0, asr #18
498 rsbs r0, r0, #0x78 @ length
499 ble hle_07_036_ending1
504 ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
505 ldr r2, [r7, #SSP_OFFS_DRAM]
507 add r1, r2, r1, lsr #15 @ addr (based)
508 ldrh r2, [r7, #0] @ pattern
509 ldrh r3, [r7, #6] @ mode
514 subnes r12,r12,#0x0400
517 orr r2, r2, r2, lsl #16
523 strneh r2, [r1], #0x3e @ align
536 strne r2, [r1], #0x40
539 b hle_07_036_end_copy
543 orreq r12,r12,#0x000f
545 orreq r12,r12,#0x00f0
547 orreq r12,r12,#0x0f00
549 orreq r12,r12,#0xf000
550 orrs r12,r12,r12,lsl #16
551 beq hle_07_036_no_ovrwr
558 strh r3, [r1], #0x3e @ align
581 ldr r2, [r7, #SSP_OFFS_DRAM]
583 sub r0, r1, r2 @ new addr
585 strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
588 ldr r0, [r7, #0x1e0] @ F1h << 16
591 add r0, r0, #(0xc4<<16)
592 bic r8, r8, #0xff0000
594 add r0, r7, r0, lsr #15
600 ldr r1, [r7, #4] @ new mode
602 strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
616 b ssp_drc_next @ let the dispatcher finish this