2 @* Compiler helper functions and some SVP HLE code
3 @* (C) notaz, 2008,2009
5 @* This work is licensed under the terms of MAME license.
6 @* See COPYING file in the top-level directory.
11 .global ssp_drc_next_patch
15 .global ssp_hle_07_030
16 .global ssp_hle_07_036
17 .global ssp_hle_07_6d6
18 .global ssp_hle_11_12c
19 .global ssp_hle_11_384
20 .global ssp_hle_11_38a
25 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
26 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
27 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
28 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
33 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
42 #define SSP_OFFS_GR 0x400
47 #define SSP_OFFS_PM_WRITE 0x46c // pmac_write[]
48 #define SSP_OFFS_EMUSTAT 0x484 // emu_status
49 #define SSP_OFFS_IRAM_ROM 0x48c // ptr_iram_rom
50 #define SSP_OFFS_DRAM 0x490 // ptr_dram
51 #define SSP_OFFS_IRAM_DIRTY 0x494
52 #define SSP_OFFS_IRAM_CTX 0x498 // iram_context
53 #define SSP_OFFS_BLTAB 0x49c // block_table
54 #define SSP_OFFS_BLTAB_IRAM 0x4a0
55 #define SSP_OFFS_TMP0 0x4a4 // for entry PC
56 #define SSP_OFFS_TMP1 0x4a8
57 #define SSP_OFFS_TMP2 0x4ac
58 #define SSP_WAIT_PM0 0x2000
61 .macro ssp_drc_do_next patch_jump=0
63 str lr, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
67 str r0, [r7, #SSP_OFFS_TMP0]
71 ldr r2, [r7, #SSP_OFFS_BLTAB]
72 ldr r2, [r2, r0, lsl #2]
79 bl ssp_translate_block
81 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
82 ldr r1, [r7, #SSP_OFFS_BLTAB]
83 str r2, [r1, r0, lsl #2]
91 ldr r1, [r7, #SSP_OFFS_IRAM_DIRTY]
93 ldreq r1, [r7, #SSP_OFFS_IRAM_CTX]
94 beq 1f @ ssp_de_iram_ctx
96 bl ssp_get_iram_context
98 str r1, [r7, #SSP_OFFS_IRAM_DIRTY]
100 str r1, [r7, #SSP_OFFS_IRAM_CTX]
101 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
103 1: @ ssp_de_iram_ctx:
104 ldr r2, [r7, #SSP_OFFS_BLTAB_IRAM]
105 add r2, r2, r1, lsl #12 @ block_tab_iram + iram_context * 0x800/2*4
106 add r1, r2, r0, lsl #2
114 str r1, [r7, #SSP_OFFS_TMP1]
115 bl ssp_translate_block
117 ldr r0, [r7, #SSP_OFFS_TMP0] @ entry PC
118 ldr r1, [r7, #SSP_OFFS_TMP1] @ &block_table_iram[iram_context][rPC]
125 .endm @ ssp_drc_do_next
129 stmfd sp!, {r4-r11, lr}
136 ldmia r2, {r3,r4,r5,r6,r8}
139 orr r4, r3, r4, lsr #16 @ XXYY
141 and r8, r8, #0x0f0000
142 mov r8, r8, lsl #13 @ sss0 *
143 and r9, r6, #0x670000
147 orrne r8, r8, #0x4 @ sss0 * NZ..
148 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
150 ldr r8, [r7, #0x440] @ r0-r2
151 ldr r9, [r7, #0x444] @ r4-r6
152 ldr r10,[r7, #(0x400+SSP_P*4)] @ P
154 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
166 ldr r1, [r7, #SSP_OFFS_TMP2] @ jump instr. (actually call) address + 4
168 moveq r3, #0xe1000000
169 orreq r3, r3, #0x00a00000 @ nop
176 streq r3, [r1, #-4] @ move the other cond up
177 moveq r3, #0xe1000000
178 orreq r3, r3, #0x00a00000
179 streq r3, [r1] @ fill it's place with nop
185 bic r3, r3, #1 @ L bit
186 orr r3, r3, r12,lsl #6
187 mov r3, r3, ror #8 @ patched branch instruction
188 str r3, [r1, #-4] @ patch the bl/b to jump directly to another handler
191 str r2, [r7, #SSP_OFFS_TMP1]
194 bl cache_flush_d_inval_i
195 ldr r2, [r7, #SSP_OFFS_TMP1]
196 ldr r0, [r7, #SSP_OFFS_TMP0]
202 str r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
205 str r10,[r7, #(0x400+SSP_P*4)] @ P
206 str r8, [r7, #0x440] @ r0-r2
207 str r9, [r7, #0x444] @ r4-r6
210 and r9, r9, #(7<<16) @ STACK
212 msr cpsr_flg, r3 @ to to ARM PSR
215 orrmi r6, r6, #0x80000000 @ N
216 orreq r6, r6, #0x20000000 @ Z
218 mov r3, r4, lsl #16 @ Y
220 mov r2, r2, lsl #16 @ X
223 stmia r8, {r2,r3,r5,r6,r9}
226 ldmfd sp!, {r4-r11, lr}
235 ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
236 ldr r1, [r7, #SSP_OFFS_EMUSTAT]
238 orreq r1, r1, #SSP_WAIT_PM0
240 streq r1, [r7, #SSP_OFFS_EMUSTAT]
247 .macro hle_flushflags
250 orr r6, r6, r1, lsr #28
254 sub r6, r6, #0x20000000
256 add r1, r1, #0x048 @ stack
257 add r1, r1, r6, lsr #28
267 ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
268 add r2, r3, r0, lsl #1 @ (r7|00)
273 add r3, r3, r0, lsl #1 @ IRAM dest
274 ldrh r12,[r2], #2 @ length
275 bic r3, r3, #3 @ always seen aligned
276 @ orr r5, r5, #0x08000000
277 @ orr r5, r5, #0x00880000
278 @ sub r5, r5, r12, lsl #16
282 str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
283 sub r11,r11,r12,lsl #1
284 sub r11,r11,r12 @ -= length*3
290 orr r0, r0, r1, lsl #16
298 ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
302 strh r2, [r1] @ (r7|00)
306 orr r0, r0, #0x08000000
307 orr r0, r0, #0x001c8000
308 str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
309 str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
312 subs r11,r11,#16 @ timeslice is likely to end
317 @ this one is car rendering related
318 .macro hle_11_12c_mla offs_in
319 ldrsh r5, [r7, #(\offs_in+0)]
320 ldrsh r0, [r7, #(\offs_in+2)]
321 ldrsh r1, [r7, #(\offs_in+4)]
323 ldrsh r12,[r7, #(\offs_in+6)]
326 add r5, r5, r12,lsl #11
329 add r1, r7, r8, lsr #23
350 mov r2, r2, asr #15 @ (r7|00) << 1
352 mov r3, r3, asr #15 @ (r7|01) << 1
354 mov r4, r4, asr #15 @ (r7|10) << 1
382 mov r2, #0 @ EFh, EEh
384 add r0, r7, #0x1c0 @ r0 (based)
390 eor r5, r5, r5, asr #31
391 add r5, r5, r5, lsr #31 @ abs(r5)
393 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
398 orrpl r2, r2, r1,lsl #16 @ EFh |= r4
408 bpl ssp_hle_11_38x_loop
413 orr r8, r8, r0, lsr #1
419 sub r11,r11,#(9+30*4)
428 and r0, r8, #0xff @ assuming alignment
429 add r0, r7, r0, lsl #1
431 mov r1, r1, lsl #16 @ 106h << 16
432 mov r2, r2, lsl #16 @ 107h << 16
437 bmi ssp_hle_07_6d6_end
443 bmi ssp_hle_07_6d6_loop
445 b ssp_hle_07_6d6_loop
452 orr r1, r2, r1, lsr #16
462 orr r0, r0, r0, lsr #16
467 ldr r1, [r7, #0x1e0] @ F1h F0h
468 rsb r5, r1, r1, lsr #16
469 mov r5, r5, lsl #16 @ AL not needed
472 bmi hle_07_036_ending2
473 ldr r1, [r7, #0x1dc] @ EEh
480 strh r0, [r1, #0xea] @ F5h
481 ldr r0, [r7, #0x1e0] @ F0h
483 strh r0, [r1, #0xf0] @ F8h
484 add r2, r0, #0xc0 @ r2
485 add r2, r7, r2, lsl #1
491 @ will handle PMC later
492 ldr r0, [r7, #0x1e8] @ F5h << 16
493 ldr r1, [r7, #0x1f0] @ F8h
494 ldr r2, [r7, #0x1d4] @ EAh
496 add r0, r0, r1, lsl #16
497 sub r0, r2, r0, asr #18
499 rsbs r0, r0, #0x78 @ length
500 ble hle_07_036_ending1
505 ldr r1, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
506 ldr r2, [r7, #SSP_OFFS_DRAM]
508 add r1, r2, r1, lsr #15 @ addr (based)
509 ldrh r2, [r7, #0] @ pattern
510 ldrh r3, [r7, #6] @ mode
515 subnes r12,r12,#0x0400
518 orr r2, r2, r2, lsl #16
524 strneh r2, [r1], #0x3e @ align
537 strne r2, [r1], #0x40
540 b hle_07_036_end_copy
544 orreq r12,r12,#0x000f
546 orreq r12,r12,#0x00f0
548 orreq r12,r12,#0x0f00
550 orreq r12,r12,#0xf000
551 orrs r12,r12,r12,lsl #16
552 beq hle_07_036_no_ovrwr
559 strh r3, [r1], #0x3e @ align
582 ldr r2, [r7, #SSP_OFFS_DRAM]
584 sub r0, r1, r2 @ new addr
586 strh r0, [r3, #(0x6c+4*4)] @ SSP_OFFS_PM_WRITE+4*4 (low)
589 ldr r0, [r7, #0x1e0] @ F1h << 16
592 add r0, r0, #(0xc4<<16)
593 bic r8, r8, #0xff0000
595 add r0, r7, r0, lsr #15
601 ldr r1, [r7, #4] @ new mode
603 strh r1, [r2, #(0x6c+4*4+2)] @ SSP_OFFS_PM_WRITE+4*4 (high)
617 b ssp_drc_next @ let the dispatcher finish this
619 @ vim:filetype=armasm