2 * rarely used EEPROM code
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4 * (see Genesis Plus for Wii/GC code and docs for info,
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5 * full game list and better code).
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8 #include "pico_int.h"
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10 static unsigned int last_write = 0xffff0000;
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12 // eeprom_status: LA.. s.la (L=pending SCL, A=pending SDA,
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13 // s=started, l=old SCL, a=old SDA)
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14 static void EEPROM_write_do(unsigned int d) // ???? ??la (l=SCL, a=SDA)
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16 unsigned int sreg = Pico.m.eeprom_status, saddr = Pico.m.eeprom_addr;
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17 unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;
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19 elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,
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20 (d&2)>>1, d&1, SekCyclesDoneT() - last_write);
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24 // SCL was and is still high..
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25 if((sreg & 1) && !(d&1)) {
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26 // ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter
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27 elprintf(EL_EEPROM, "eeprom: -start-");
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31 } else if(!(sreg & 1) && (d&1)) {
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32 // SDA went high == stop command
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33 elprintf(EL_EEPROM, "eeprom: -stop-");
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37 else if((sreg & 8) && !(sreg & 2) && (d&2))
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39 // we are started and SCL went high - next cycle
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40 scyc++; // pre-increment
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41 if(SRam.eeprom_type) {
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43 if((ssa&1) && scyc == 18) {
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45 saddr++; // next address in read mode
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46 /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask
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48 else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;
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49 else if(scyc == 36) scyc = 27;
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54 if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode
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57 elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);
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59 else if((sreg & 8) && (sreg & 2) && !(d&2))
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61 // we are started and SCL went low (falling edge)
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62 if(SRam.eeprom_type) {
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64 if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles
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65 else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {
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68 unsigned char *pm=SRam.data+saddr;
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69 *pm <<= 1; *pm |= d&1;
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70 if(scyc == 26 || scyc == 35) {
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71 saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented
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72 elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);
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76 } else if(scyc > 9) {
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78 // we latch another addr bit
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80 if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask
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82 if(scyc==17||scyc==26) {
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83 elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);
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84 if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too
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90 if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);
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94 if(scyc == 9); // ACK cycle, do nothing
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98 unsigned char *pm=SRam.data+(saddr>>1);
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99 *pm <<= 1; *pm |= d&1;
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101 saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented
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102 elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);
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107 // we latch another addr bit
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108 saddr<<=1; saddr|=d&1; saddr&=0xff;
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109 if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);
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114 sreg &= ~3; sreg |= d&3; // remember SCL and SDA
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115 Pico.m.eeprom_status = (unsigned char) sreg;
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116 Pico.m.eeprom_cycle = (unsigned char) scyc;
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117 Pico.m.eeprom_slave = (unsigned char) ssa;
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118 Pico.m.eeprom_addr = (unsigned short)saddr;
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121 static void EEPROM_upd_pending(unsigned int d)
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123 unsigned int d1, sreg = Pico.m.eeprom_status;
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128 d1 = (d >> SRam.eeprom_bit_cl) & 1;
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132 d1 = (d >> SRam.eeprom_bit_in) & 1;
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135 Pico.m.eeprom_status = (unsigned char) sreg;
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138 void EEPROM_write16(unsigned int d)
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140 // this diff must be at most 16 for NBA Jam to work
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141 if (SekCyclesDoneT() - last_write < 16) {
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142 // just update pending state
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143 elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",
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144 SekCyclesDoneT() - last_write);
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145 EEPROM_upd_pending(d);
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147 int srs = Pico.m.eeprom_status;
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148 EEPROM_write_do(srs >> 6); // execute pending
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149 EEPROM_upd_pending(d);
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150 if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed
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151 last_write = SekCyclesDoneT();
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155 void EEPROM_write8(unsigned int a, unsigned int d)
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157 unsigned char *wb = Pico.m.eeprom_wb;
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159 EEPROM_write16((wb[0] << 8) | wb[1]);
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162 unsigned int EEPROM_read(void)
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164 unsigned int shift, d;
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165 unsigned int sreg, saddr, scyc, ssa, interval;
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167 // flush last pending write
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168 EEPROM_write_do(Pico.m.eeprom_status>>6);
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170 sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;
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171 interval = SekCyclesDoneT() - last_write;
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172 d = (sreg>>6)&1; // use SDA as "open bus"
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174 // NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.
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175 // this is probably valid because data changes occur while SCL is low and data can be read
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176 // before it's actual cycle begins.
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177 if (!(sreg&0x80) && interval >= 24) {
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178 elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);
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182 if (!(sreg & 8)); // not started, use open bus
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183 else if (scyc == 9 || scyc == 18 || scyc == 27) {
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184 elprintf(EL_EEPROM, "eeprom: r ack");
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186 } else if (scyc > 9 && scyc < 18) {
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187 // started and first command word received
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189 if (SRam.eeprom_type) {
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192 elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
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193 if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);
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194 d = (SRam.data[saddr]>>shift)&1;
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199 elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);
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200 if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);
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201 d = (SRam.data[saddr>>1]>>shift)&1;
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206 return (d << SRam.eeprom_bit_out);
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