3 * (c) Copyright Dave, 2004
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4 * (C) notaz, 2006-2010
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6 * This work is licensed under the terms of MAME license.
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7 * See COPYING file in the top-level directory.
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10 #include "pico_int.h"
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13 #include "sound/ym2612.h"
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14 #include "sound/sn76496.h"
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16 extern unsigned int lastSSRamWrite; // used by serial eeprom code
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18 uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];
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19 uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];
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20 uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];
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21 uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
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23 static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
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24 const void *func_or_mh, int is_func)
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27 // workaround bug (segfault) in
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28 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
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31 uptr addr = (uptr)func_or_mh;
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32 int mask = (1 << shift) - 1;
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35 if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {
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36 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",
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37 start_addr, end_addr);
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42 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);
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49 for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
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52 map[i] |= (uptr)1 << (sizeof(addr) * 8 - 1);
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56 void z80_map_set(uptr *map, int start_addr, int end_addr,
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57 const void *func_or_mh, int is_func)
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59 xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
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62 void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
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63 const void *func_or_mh, int is_func)
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65 xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
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68 // more specialized/optimized function (does same as above)
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69 void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)
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71 uptr *r8map, *r16map, *w8map, *w16map;
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72 uptr addr = (uptr)ptr;
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73 int shift = M68K_MEM_SHIFT;
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77 r8map = m68k_read8_map;
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78 r16map = m68k_read16_map;
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79 w8map = m68k_write8_map;
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80 w16map = m68k_write16_map;
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82 r8map = s68k_read8_map;
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83 r16map = s68k_read16_map;
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84 w8map = s68k_write8_map;
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85 w16map = s68k_write16_map;
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90 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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91 r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;
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94 static u32 m68k_unmapped_read8(u32 a)
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96 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
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97 return 0; // assume pulldown, as if MegaCD2 was attached
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100 static u32 m68k_unmapped_read16(u32 a)
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102 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
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106 static void m68k_unmapped_write8(u32 a, u32 d)
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108 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
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111 static void m68k_unmapped_write16(u32 a, u32 d)
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113 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
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116 void m68k_map_unmap(int start_addr, int end_addr)
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119 // workaround bug (segfault) in
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120 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
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124 int shift = M68K_MEM_SHIFT;
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127 addr = (uptr)m68k_unmapped_read8;
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128 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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129 m68k_read8_map[i] = (addr >> 1) | (1 << 31);
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131 addr = (uptr)m68k_unmapped_read16;
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132 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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133 m68k_read16_map[i] = (addr >> 1) | (1 << 31);
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135 addr = (uptr)m68k_unmapped_write8;
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136 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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137 m68k_write8_map[i] = (addr >> 1) | (1 << 31);
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139 addr = (uptr)m68k_unmapped_write16;
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140 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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141 m68k_write16_map[i] = (addr >> 1) | (1 << 31);
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144 MAKE_68K_READ8(m68k_read8, m68k_read8_map)
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145 MAKE_68K_READ16(m68k_read16, m68k_read16_map)
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146 MAKE_68K_READ32(m68k_read32, m68k_read16_map)
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147 MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)
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148 MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)
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149 MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)
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151 // -----------------------------------------------------------------
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153 static u32 ym2612_read_local_68k(void);
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154 static int ym2612_write_local(u32 a, u32 d, int is_from_z80);
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155 static void z80_mem_setup(void);
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157 #ifdef _ASM_MEMORY_C
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158 u32 PicoRead8_sram(u32 a);
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159 u32 PicoRead16_sram(u32 a);
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162 #ifdef EMU_CORE_DEBUG
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163 u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};
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164 int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
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165 extern unsigned int ppop;
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169 void log_io(unsigned int addr, int bits, int rw);
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170 #elif defined(_MSC_VER)
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173 #define log_io(...)
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176 #if defined(EMU_C68K)
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177 void cyclone_crashed(u32 pc, struct Cyclone *context)
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179 elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",
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180 context == &PicoCpuCM68k ? 'm' : 's', pc);
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181 context->membase = (u32)Pico.rom;
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182 context->pc = (u32)Pico.rom + Pico.romsize;
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186 // -----------------------------------------------------------------
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189 #ifndef _ASM_MEMORY_C
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194 int pad,value,data_reg;
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195 pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU
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196 data_reg=Pico.ioports[i+1];
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198 // orr the bits, which are set as output
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199 value = data_reg&(Pico.ioports[i+4]|0x80);
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201 if (PicoOpt & POPT_6BTN_PAD)
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203 int phase = Pico.m.padTHPhase[i];
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205 if(phase == 2 && !(data_reg&0x40)) { // TH
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206 value|=(pad&0xc0)>>2; // ?0SA 0000
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208 } else if(phase == 3) {
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210 value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
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212 value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
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217 if(data_reg&0x40) // TH
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218 value|=(pad&0x3f); // ?1CB RLDU
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219 else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
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221 return value; // will mirror later
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224 #ifndef _ASM_MEMORY_C
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226 static u32 io_ports_read(u32 a)
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231 case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
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232 case 1: d = PadRead(0); break;
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233 case 2: d = PadRead(1); break;
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234 default: d = Pico.ioports[a]; break; // IO ports can be used as RAM
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239 static void NOINLINE io_ports_write(u32 a, u32 d)
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243 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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244 if (1 <= a && a <= 2 && (PicoOpt & POPT_6BTN_PAD))
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246 Pico.m.padDelay[a - 1] = 0;
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247 if (!(Pico.ioports[a] & 0x40) && (d & 0x40))
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248 Pico.m.padTHPhase[a - 1]++;
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251 // certain IO ports can be used as RAM
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252 Pico.ioports[a] = d;
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255 #endif // _ASM_MEMORY_C
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257 void NOINLINE ctl_write_z80busreq(u32 d)
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260 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
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261 if (d ^ Pico.m.z80Run)
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265 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
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269 z80stopCycle = SekCyclesDone();
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270 if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {
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272 PicoSyncZ80(z80stopCycle);
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273 pprof_end_sub(m68k);
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280 void NOINLINE ctl_write_z80reset(u32 d)
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283 elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);
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284 if (d ^ Pico.m.z80_reset)
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288 if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run) {
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290 PicoSyncZ80(SekCyclesDone());
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291 pprof_end_sub(m68k);
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298 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
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301 Pico.m.z80_reset = d;
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305 // -----------------------------------------------------------------
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307 #ifndef _ASM_MEMORY_C
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309 // cart (save) RAM area (usually 0x200000 - ...)
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310 static u32 PicoRead8_sram(u32 a)
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313 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))
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315 if (SRam.flags & SRF_EEPROM) {
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320 d = *(u8 *)(SRam.data - SRam.start + a);
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321 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
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325 // XXX: this is banking unfriendly
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326 if (a < Pico.romsize)
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327 return Pico.rom[a ^ 1];
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329 return m68k_unmapped_read8(a);
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332 static u32 PicoRead16_sram(u32 a)
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335 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))
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337 if (SRam.flags & SRF_EEPROM)
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340 u8 *pm = (u8 *)(SRam.data - SRam.start + a);
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344 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
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348 if (a < Pico.romsize)
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349 return *(u16 *)(Pico.rom + a);
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351 return m68k_unmapped_read16(a);
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354 #endif // _ASM_MEMORY_C
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356 static void PicoWrite8_sram(u32 a, u32 d)
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358 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
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359 m68k_unmapped_write8(a, d);
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363 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);
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364 if (SRam.flags & SRF_EEPROM)
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366 EEPROM_write8(a, d);
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369 u8 *pm = (u8 *)(SRam.data - SRam.start + a);
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370 if (*pm != (u8)d) {
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377 static void PicoWrite16_sram(u32 a, u32 d)
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379 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
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380 m68k_unmapped_write16(a, d);
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384 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);
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385 if (SRam.flags & SRF_EEPROM)
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390 // XXX: hardware could easily use MSB too..
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391 u8 *pm = (u8 *)(SRam.data - SRam.start + a);
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392 if (*pm != (u8)d) {
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399 // z80 area (0xa00000 - 0xa0ffff)
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400 // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)
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401 static u32 PicoRead8_z80(u32 a)
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404 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
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405 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
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406 // open bus. Pulled down if MegaCD2 is attached.
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410 if ((a & 0x4000) == 0x0000)
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411 d = Pico.zram[a & 0x1fff];
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412 else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff
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413 d = ym2612_read_local_68k();
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415 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
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419 static u32 PicoRead16_z80(u32 a)
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421 u32 d = PicoRead8_z80(a);
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422 return d | (d << 8);
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425 static void PicoWrite8_z80(u32 a, u32 d)
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427 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
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428 // verified on real hw
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429 elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
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433 if ((a & 0x4000) == 0x0000) { // z80 RAM
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434 SekCyclesBurn(2); // hack
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435 Pico.zram[a & 0x1fff] = (u8)d;
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438 if ((a & 0x6000) == 0x4000) { // FM Sound
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439 if (PicoOpt & POPT_EN_FM)
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440 emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;
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443 // TODO: probably other VDP access too? Maybe more mirrors?
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444 if ((a & 0x7ff9) == 0x7f11) { // PSG Sound
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445 if (PicoOpt & POPT_EN_PSG)
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449 if ((a & 0x7f00) == 0x6000) // Z80 BANK register
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451 Pico.m.z80_bank68k >>= 1;
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452 Pico.m.z80_bank68k |= d << 8;
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453 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
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454 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);
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457 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);
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460 static void PicoWrite16_z80(u32 a, u32 d)
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462 // for RAM, only most significant byte is sent
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463 // TODO: verify remaining accesses
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464 PicoWrite8_z80(a, d >> 8);
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467 #ifndef _ASM_MEMORY_C
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469 // IO/control area (0xa10000 - 0xa1ffff)
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470 u32 PicoRead8_io(u32 a)
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474 if ((a & 0xffe0) == 0x0000) { // I/O ports
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475 d = io_ports_read(a);
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479 // faking open bus (MegaCD pulldowns don't work here curiously)
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480 d = Pico.m.rotate++;
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483 if ((a & 0xfc00) == 0x1000) {
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484 // bit8 seems to be readable in this range
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488 if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)
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489 d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;
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490 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);
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495 if (PicoOpt & POPT_EN_32X) {
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496 d = PicoRead8_32x(a);
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500 d = m68k_unmapped_read8(a);
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505 u32 PicoRead16_io(u32 a)
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509 if ((a & 0xffe0) == 0x0000) { // I/O ports
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510 d = io_ports_read(a);
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516 d = (Pico.m.rotate += 0x41);
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517 d ^= (d << 5) ^ (d << 8);
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519 // bit8 seems to be readable in this range
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520 if ((a & 0xfc00) == 0x1000) {
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523 if ((a & 0xff00) == 0x1100) { // z80 busreq
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524 d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;
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525 elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);
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530 if (PicoOpt & POPT_EN_32X) {
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531 d = PicoRead16_32x(a);
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535 d = m68k_unmapped_read16(a);
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540 void PicoWrite8_io(u32 a, u32 d)
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542 if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)
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543 io_ports_write(a, d);
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546 if ((a & 0xff01) == 0x1100) { // z80 busreq
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547 ctl_write_z80busreq(d);
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550 if ((a & 0xff01) == 0x1200) { // z80 reset
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551 ctl_write_z80reset(d);
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554 if (a == 0xa130f1) { // sram access register
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555 elprintf(EL_SRAMIO, "sram reg=%02x", d);
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556 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
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557 Pico.m.sram_reg |= (u8)(d & 3);
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560 if (PicoOpt & POPT_EN_32X) {
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561 PicoWrite8_32x(a, d);
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565 m68k_unmapped_write8(a, d);
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568 void PicoWrite16_io(u32 a, u32 d)
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570 if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)
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571 io_ports_write(a, d);
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574 if ((a & 0xff00) == 0x1100) { // z80 busreq
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575 ctl_write_z80busreq(d >> 8);
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578 if ((a & 0xff00) == 0x1200) { // z80 reset
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579 ctl_write_z80reset(d >> 8);
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582 if (a == 0xa130f0) { // sram access register
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583 elprintf(EL_SRAMIO, "sram reg=%02x", d);
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584 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
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585 Pico.m.sram_reg |= (u8)(d & 3);
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588 if (PicoOpt & POPT_EN_32X) {
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589 PicoWrite16_32x(a, d);
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592 m68k_unmapped_write16(a, d);
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595 #endif // _ASM_MEMORY_C
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597 // VDP area (0xc00000 - 0xdfffff)
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598 // TODO: verify if lower byte goes to PSG on word writes
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599 static u32 PicoRead8_vdp(u32 a)
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601 if ((a & 0x00e0) == 0x0000)
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602 return PicoVideoRead8(a);
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604 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
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608 static u32 PicoRead16_vdp(u32 a)
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610 if ((a & 0x00e0) == 0x0000)
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611 return PicoVideoRead(a);
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613 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
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617 static void PicoWrite8_vdp(u32 a, u32 d)
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619 if ((a & 0x00f9) == 0x0011) { // PSG Sound
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620 if (PicoOpt & POPT_EN_PSG)
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624 if ((a & 0x00e0) == 0x0000) {
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626 PicoVideoWrite(a, d | (d << 8));
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630 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);
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633 static void PicoWrite16_vdp(u32 a, u32 d)
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635 if ((a & 0x00f9) == 0x0010) { // PSG Sound
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636 if (PicoOpt & POPT_EN_PSG)
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640 if ((a & 0x00e0) == 0x0000) {
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641 PicoVideoWrite(a, d);
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645 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);
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648 // -----------------------------------------------------------------
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651 static void m68k_mem_setup(void);
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654 PICO_INTERNAL void PicoMemSetup(void)
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658 // setup the memory map
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659 cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);
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660 cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);
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661 cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);
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662 cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);
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665 // align to bank size. We know ROM loader allocated enough for this
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666 mask = (1 << M68K_MEM_SHIFT) - 1;
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667 rs = (Pico.romsize + mask) & ~mask;
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668 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);
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669 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);
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671 // Common case of on-cart (save) RAM, usually at 0x200000-...
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672 if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {
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673 rs = SRam.end - SRam.start;
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674 rs = (rs + mask) & ~mask;
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675 if (SRam.start + rs >= 0x1000000)
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676 rs = 0x1000000 - SRam.start;
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677 cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);
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678 cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);
\r
679 cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);
\r
680 cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);
\r
684 cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);
\r
685 cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);
\r
686 cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);
\r
687 cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);
\r
689 // IO/control region
\r
690 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);
\r
691 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);
\r
692 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);
\r
693 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);
\r
696 for (a = 0xc00000; a < 0xe00000; a += 0x010000) {
\r
697 if ((a & 0xe700e0) != 0xc00000)
\r
699 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);
\r
700 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);
\r
701 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);
\r
702 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);
\r
705 // RAM and it's mirrors
\r
706 for (a = 0xe00000; a < 0x1000000; a += 0x010000) {
\r
707 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);
\r
708 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);
\r
709 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);
\r
710 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);
\r
713 // Setup memory callbacks:
\r
715 PicoCpuCM68k.read8 = (void *)m68k_read8_map;
\r
716 PicoCpuCM68k.read16 = (void *)m68k_read16_map;
\r
717 PicoCpuCM68k.read32 = (void *)m68k_read16_map;
\r
718 PicoCpuCM68k.write8 = (void *)m68k_write8_map;
\r
719 PicoCpuCM68k.write16 = (void *)m68k_write16_map;
\r
720 PicoCpuCM68k.write32 = (void *)m68k_write16_map;
\r
721 PicoCpuCM68k.checkpc = NULL; /* unused */
\r
722 PicoCpuCM68k.fetch8 = NULL;
\r
723 PicoCpuCM68k.fetch16 = NULL;
\r
724 PicoCpuCM68k.fetch32 = NULL;
\r
727 PicoCpuFM68k.read_byte = m68k_read8;
\r
728 PicoCpuFM68k.read_word = m68k_read16;
\r
729 PicoCpuFM68k.read_long = m68k_read32;
\r
730 PicoCpuFM68k.write_byte = m68k_write8;
\r
731 PicoCpuFM68k.write_word = m68k_write16;
\r
732 PicoCpuFM68k.write_long = m68k_write32;
\r
734 // setup FAME fetchmap
\r
737 // by default, point everything to first 64k of ROM
\r
738 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
739 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
\r
741 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
\r
742 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;
\r
744 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)
\r
745 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.ram - (i<<(24-FAMEC_FETCHBITS));
\r
756 unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;
\r
757 unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;
\r
758 unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;
\r
759 void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;
\r
760 void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;
\r
761 void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;
\r
763 /* it appears that Musashi doesn't always mask the unused bits */
\r
764 unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }
\r
765 unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }
\r
766 unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }
\r
767 void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }
\r
768 void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }
\r
769 void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }
\r
771 static void m68k_mem_setup(void)
\r
773 pm68k_read_memory_8 = m68k_read8;
\r
774 pm68k_read_memory_16 = m68k_read16;
\r
775 pm68k_read_memory_32 = m68k_read32;
\r
776 pm68k_write_memory_8 = m68k_write8;
\r
777 pm68k_write_memory_16 = m68k_write16;
\r
778 pm68k_write_memory_32 = m68k_write32;
\r
783 // -----------------------------------------------------------------
\r
785 static int get_scanline(int is_from_z80)
\r
788 int cycles = z80_cyclesDone();
\r
789 while (cycles - z80_scanline_cycles >= 228)
\r
790 z80_scanline++, z80_scanline_cycles += 228;
\r
791 return z80_scanline;
\r
794 return Pico.m.scanline;
\r
797 /* probably should not be in this file, but it's near related code here */
\r
798 void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)
\r
800 int xcycles = z80_cycles << 8;
\r
802 /* check for overflows */
\r
803 if ((mode_old & 4) && xcycles > timer_a_next_oflow)
\r
804 ym2612.OPN.ST.status |= 1;
\r
806 if ((mode_old & 8) && xcycles > timer_b_next_oflow)
\r
807 ym2612.OPN.ST.status |= 2;
\r
809 /* update timer a */
\r
811 while (xcycles > timer_a_next_oflow)
\r
812 timer_a_next_oflow += timer_a_step;
\r
814 if ((mode_old ^ mode_new) & 1) // turning on/off
\r
817 timer_a_next_oflow = TIMER_NO_OFLOW;
\r
819 timer_a_next_oflow = xcycles + timer_a_step;
\r
822 elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);
\r
824 /* update timer b */
\r
826 while (xcycles > timer_b_next_oflow)
\r
827 timer_b_next_oflow += timer_b_step;
\r
829 if ((mode_old ^ mode_new) & 2)
\r
832 timer_b_next_oflow = TIMER_NO_OFLOW;
\r
834 timer_b_next_oflow = xcycles + timer_b_step;
\r
837 elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);
\r
840 // ym2612 DAC and timer I/O handlers for z80
\r
841 static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
\r
846 if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */
\r
848 int scanline = get_scanline(is_from_z80);
\r
849 //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);
\r
850 ym2612.dacout = ((int)d - 0x80) << 6;
\r
851 if (PsndOut && ym2612.dacen && scanline >= PsndDacLine)
\r
852 PsndDoDAC(scanline);
\r
858 case 0: /* address port 0 */
\r
859 ym2612.OPN.ST.address = d;
\r
860 ym2612.addr_A1 = 0;
\r
862 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
\r
866 case 1: /* data port 0 */
\r
867 if (ym2612.addr_A1 != 0)
\r
870 addr = ym2612.OPN.ST.address;
\r
871 ym2612.REGS[addr] = d;
\r
875 case 0x24: // timer A High 8
\r
876 case 0x25: { // timer A Low 2
\r
877 int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))
\r
878 : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));
\r
879 if (ym2612.OPN.ST.TA != TAnew)
\r
881 //elprintf(EL_STATUS, "timer a set %i", TAnew);
\r
882 ym2612.OPN.ST.TA = TAnew;
\r
883 //ym2612.OPN.ST.TAC = (1024-TAnew)*18;
\r
884 //ym2612.OPN.ST.TAT = 0;
\r
885 timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
\r
886 if (ym2612.OPN.ST.mode & 1) {
\r
887 // this is not right, should really be done on overflow only
\r
888 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
\r
889 timer_a_next_oflow = (cycles << 8) + timer_a_step;
\r
891 elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);
\r
895 case 0x26: // timer B
\r
896 if (ym2612.OPN.ST.TB != d) {
\r
897 //elprintf(EL_STATUS, "timer b set %i", d);
\r
898 ym2612.OPN.ST.TB = d;
\r
899 //ym2612.OPN.ST.TBC = (256-d) * 288;
\r
900 //ym2612.OPN.ST.TBT = 0;
\r
901 timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
\r
902 if (ym2612.OPN.ST.mode & 2) {
\r
903 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
\r
904 timer_b_next_oflow = (cycles << 8) + timer_b_step;
\r
906 elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);
\r
909 case 0x27: { /* mode, timer control */
\r
910 int old_mode = ym2612.OPN.ST.mode;
\r
911 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
\r
912 ym2612.OPN.ST.mode = d;
\r
914 elprintf(EL_YMTIMER, "st mode %02x", d);
\r
915 ym2612_sync_timers(cycles, old_mode, d);
\r
917 /* reset Timer a flag */
\r
919 ym2612.OPN.ST.status &= ~1;
\r
921 /* reset Timer b flag */
\r
923 ym2612.OPN.ST.status &= ~2;
\r
925 if ((d ^ old_mode) & 0xc0) {
\r
927 if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));
\r
933 case 0x2b: { /* DAC Sel (YM2612) */
\r
934 int scanline = get_scanline(is_from_z80);
\r
935 ym2612.dacen = d & 0x80;
\r
936 if (d & 0x80) PsndDacLine = scanline;
\r
938 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);
\r
945 case 2: /* address port 1 */
\r
946 ym2612.OPN.ST.address = d;
\r
947 ym2612.addr_A1 = 1;
\r
949 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
\r
953 case 3: /* data port 1 */
\r
954 if (ym2612.addr_A1 != 1)
\r
957 addr = ym2612.OPN.ST.address | 0x100;
\r
958 ym2612.REGS[addr] = d;
\r
963 if (PicoOpt & POPT_EXT_FM)
\r
964 return YM2612Write_940(a, d, get_scanline(is_from_z80));
\r
966 return YM2612Write_(a, d);
\r
970 #define ym2612_read_local() \
\r
971 if (xcycles >= timer_a_next_oflow) \
\r
972 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \
\r
973 if (xcycles >= timer_b_next_oflow) \
\r
974 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2
\r
976 static u32 ym2612_read_local_z80(void)
\r
978 int xcycles = z80_cyclesDone() << 8;
\r
980 ym2612_read_local();
\r
982 elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,
\r
983 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);
\r
984 return ym2612.OPN.ST.status;
\r
987 static u32 ym2612_read_local_68k(void)
\r
989 int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;
\r
991 ym2612_read_local();
\r
993 elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,
\r
994 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);
\r
995 return ym2612.OPN.ST.status;
\r
998 void ym2612_pack_state(void)
\r
1000 // timers are saved as tick counts, in 16.16 int format
\r
1001 int tac, tat = 0, tbc, tbt = 0;
\r
1002 tac = 1024 - ym2612.OPN.ST.TA;
\r
1003 tbc = 256 - ym2612.OPN.ST.TB;
\r
1004 if (timer_a_next_oflow != TIMER_NO_OFLOW)
\r
1005 tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);
\r
1006 if (timer_b_next_oflow != TIMER_NO_OFLOW)
\r
1007 tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);
\r
1008 elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);
\r
1009 elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);
\r
1012 if (PicoOpt & POPT_EXT_FM)
\r
1013 YM2612PicoStateSave2_940(tat, tbt);
\r
1016 YM2612PicoStateSave2(tat, tbt);
\r
1019 void ym2612_unpack_state(void)
\r
1021 int i, ret, tac, tat, tbc, tbt;
\r
1022 YM2612PicoStateLoad();
\r
1024 // feed all the registers and update internal state
\r
1025 for (i = 0x20; i < 0xA0; i++) {
\r
1026 ym2612_write_local(0, i, 0);
\r
1027 ym2612_write_local(1, ym2612.REGS[i], 0);
\r
1029 for (i = 0x30; i < 0xA0; i++) {
\r
1030 ym2612_write_local(2, i, 0);
\r
1031 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
\r
1033 for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards
\r
1034 ym2612_write_local(2, i, 0);
\r
1035 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
\r
1036 ym2612_write_local(0, i, 0);
\r
1037 ym2612_write_local(1, ym2612.REGS[i], 0);
\r
1039 for (i = 0xB0; i < 0xB8; i++) {
\r
1040 ym2612_write_local(0, i, 0);
\r
1041 ym2612_write_local(1, ym2612.REGS[i], 0);
\r
1042 ym2612_write_local(2, i, 0);
\r
1043 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
\r
1047 if (PicoOpt & POPT_EXT_FM)
\r
1048 ret = YM2612PicoStateLoad2_940(&tat, &tbt);
\r
1051 ret = YM2612PicoStateLoad2(&tat, &tbt);
\r
1053 elprintf(EL_STATUS, "old ym2612 state");
\r
1054 return; // no saved timers
\r
1057 tac = (1024 - ym2612.OPN.ST.TA) << 16;
\r
1058 tbc = (256 - ym2612.OPN.ST.TB) << 16;
\r
1059 if (ym2612.OPN.ST.mode & 1)
\r
1060 timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);
\r
1062 timer_a_next_oflow = TIMER_NO_OFLOW;
\r
1063 if (ym2612.OPN.ST.mode & 2)
\r
1064 timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);
\r
1066 timer_b_next_oflow = TIMER_NO_OFLOW;
\r
1067 elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);
\r
1068 elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);
\r
1071 #if defined(NO_32X) && defined(_ASM_MEMORY_C)
\r
1072 // referenced by asm code
\r
1073 u32 PicoRead8_32x(u32 a) { return 0; }
\r
1074 u32 PicoRead16_32x(u32 a) { return 0; }
\r
1075 void PicoWrite8_32x(u32 a, u32 d) {}
\r
1076 void PicoWrite16_32x(u32 a, u32 d) {}
\r
1079 // -----------------------------------------------------------------
\r
1080 // z80 memhandlers
\r
1082 static unsigned char z80_md_vdp_read(unsigned short a)
\r
1085 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);
\r
1089 static unsigned char z80_md_bank_read(unsigned short a)
\r
1091 unsigned int addr68k;
\r
1092 unsigned char ret;
\r
1094 addr68k = Pico.m.z80_bank68k<<15;
\r
1095 addr68k += a & 0x7fff;
\r
1097 ret = m68k_read8(addr68k);
\r
1099 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
\r
1103 static void z80_md_ym2612_write(unsigned int a, unsigned char data)
\r
1105 if (PicoOpt & POPT_EN_FM)
\r
1106 emustatus |= ym2612_write_local(a, data, 1) & 1;
\r
1109 static void z80_md_vdp_br_write(unsigned int a, unsigned char data)
\r
1111 // TODO: allow full VDP access
\r
1112 if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17
\r
1114 if (PicoOpt & POPT_EN_PSG)
\r
1115 SN76496Write(data);
\r
1119 if ((a>>8) == 0x60)
\r
1121 Pico.m.z80_bank68k >>= 1;
\r
1122 Pico.m.z80_bank68k |= data << 8;
\r
1123 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
\r
1127 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
\r
1130 static void z80_md_bank_write(unsigned int a, unsigned char data)
\r
1132 unsigned int addr68k;
\r
1134 addr68k = Pico.m.z80_bank68k << 15;
\r
1135 addr68k += a & 0x7fff;
\r
1137 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
\r
1138 m68k_write8(addr68k, data);
\r
1141 // -----------------------------------------------------------------
\r
1143 static unsigned char z80_md_in(unsigned short p)
\r
1145 elprintf(EL_ANOMALY, "Z80 port %04x read", p);
\r
1149 static void z80_md_out(unsigned short p, unsigned char d)
\r
1151 elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);
\r
1154 static void z80_mem_setup(void)
\r
1156 z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);
\r
1157 z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);
\r
1158 z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);
\r
1159 z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);
\r
1160 z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);
\r
1162 z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);
\r
1163 z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);
\r
1164 z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);
\r
1165 z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);
\r
1166 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);
\r
1169 drZ80.z80_in = z80_md_in;
\r
1170 drZ80.z80_out = z80_md_out;
\r
1173 Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM
\r
1174 Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror
\r
1175 Cz80_Set_INPort(&CZ80, z80_md_in);
\r
1176 Cz80_Set_OUTPort(&CZ80, z80_md_out);
\r