3 * (c) Copyright Dave, 2004
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4 * (C) notaz, 2006-2010
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6 * This work is licensed under the terms of MAME license.
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7 * See COPYING file in the top-level directory.
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10 #include "pico_int.h"
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13 #include "sound/ym2612.h"
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14 #include "sound/sn76496.h"
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16 extern unsigned int lastSSRamWrite; // used by serial eeprom code
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18 uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];
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19 uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];
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20 uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];
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21 uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
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23 static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
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24 const void *func_or_mh, int is_func)
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27 // workaround bug (segfault) in
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28 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
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31 uptr addr = (uptr)func_or_mh;
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32 int mask = (1 << shift) - 1;
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35 if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {
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36 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",
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37 start_addr, end_addr);
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42 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);
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49 for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
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52 map[i] |= (uptr)1 << (sizeof(addr) * 8 - 1);
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56 void z80_map_set(uptr *map, int start_addr, int end_addr,
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57 const void *func_or_mh, int is_func)
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59 xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
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62 void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
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63 const void *func_or_mh, int is_func)
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65 xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
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68 // more specialized/optimized function (does same as above)
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69 void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)
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71 uptr *r8map, *r16map, *w8map, *w16map;
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72 uptr addr = (uptr)ptr;
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73 int shift = M68K_MEM_SHIFT;
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77 r8map = m68k_read8_map;
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78 r16map = m68k_read16_map;
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79 w8map = m68k_write8_map;
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80 w16map = m68k_write16_map;
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82 r8map = s68k_read8_map;
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83 r16map = s68k_read16_map;
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84 w8map = s68k_write8_map;
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85 w16map = s68k_write16_map;
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90 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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91 r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;
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94 static u32 m68k_unmapped_read8(u32 a)
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96 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
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97 return 0; // assume pulldown, as if MegaCD2 was attached
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100 static u32 m68k_unmapped_read16(u32 a)
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102 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
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106 static void m68k_unmapped_write8(u32 a, u32 d)
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108 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
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111 static void m68k_unmapped_write16(u32 a, u32 d)
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113 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
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116 void m68k_map_unmap(int start_addr, int end_addr)
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119 // workaround bug (segfault) in
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120 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
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124 int shift = M68K_MEM_SHIFT;
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127 addr = (uptr)m68k_unmapped_read8;
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128 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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129 m68k_read8_map[i] = (addr >> 1) | (1 << 31);
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131 addr = (uptr)m68k_unmapped_read16;
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132 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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133 m68k_read16_map[i] = (addr >> 1) | (1 << 31);
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135 addr = (uptr)m68k_unmapped_write8;
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136 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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137 m68k_write8_map[i] = (addr >> 1) | (1 << 31);
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139 addr = (uptr)m68k_unmapped_write16;
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140 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
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141 m68k_write16_map[i] = (addr >> 1) | (1 << 31);
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144 MAKE_68K_READ8(m68k_read8, m68k_read8_map)
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145 MAKE_68K_READ16(m68k_read16, m68k_read16_map)
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146 MAKE_68K_READ32(m68k_read32, m68k_read16_map)
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147 MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)
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148 MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)
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149 MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)
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151 // -----------------------------------------------------------------
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153 static u32 ym2612_read_local_68k(void);
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154 static int ym2612_write_local(u32 a, u32 d, int is_from_z80);
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155 static void z80_mem_setup(void);
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157 #ifdef _ASM_MEMORY_C
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158 u32 PicoRead8_sram(u32 a);
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159 u32 PicoRead16_sram(u32 a);
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162 #ifdef EMU_CORE_DEBUG
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163 u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};
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164 int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
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165 extern unsigned int ppop;
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169 void log_io(unsigned int addr, int bits, int rw);
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170 #elif defined(_MSC_VER)
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173 #define log_io(...)
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176 #if defined(EMU_C68K)
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177 void cyclone_crashed(u32 pc, struct Cyclone *context)
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179 elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",
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180 context == &PicoCpuCM68k ? 'm' : 's', pc);
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181 context->membase = (u32)Pico.rom;
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182 context->pc = (u32)Pico.rom + Pico.romsize;
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186 // -----------------------------------------------------------------
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189 static u32 read_pad_3btn(int i, u32 out_bits)
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191 u32 pad = ~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU
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194 if (out_bits & 0x40) // TH
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195 value = pad & 0x3f; // ?1CB RLDU
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197 value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
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199 value |= out_bits & 0x40;
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203 static u32 read_pad_6btn(int i, u32 out_bits)
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205 u32 pad = ~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU
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206 int phase = Pico.m.padTHPhase[i];
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209 if (phase == 2 && !(out_bits & 0x40)) {
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210 value = (pad & 0xc0) >> 2; // ?0SA 0000
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213 else if(phase == 3) {
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214 if (out_bits & 0x40)
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215 return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ
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217 return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111
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221 if (out_bits & 0x40) // TH
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222 value = pad & 0x3f; // ?1CB RLDU
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224 value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
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227 value |= out_bits & 0x40;
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231 static u32 read_nothing(int i, u32 out_bits)
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236 typedef u32 (port_read_func)(int index, u32 out_bits);
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238 static port_read_func *port_readers[3] = {
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244 static NOINLINE u32 port_read(int i)
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246 u32 data_reg = Pico.ioports[i + 1];
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247 u32 ctrl_reg = Pico.ioports[i + 4] | 0x80;
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250 out = data_reg & ctrl_reg;
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251 out |= 0x7f & ~ctrl_reg; // pull-ups
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253 in = port_readers[i](i, out);
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255 return (in & ~ctrl_reg) | (data_reg & ctrl_reg);
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258 void PicoSetInputDevice(int port, enum input_device device)
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260 port_read_func *func;
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262 if (port < 0 || port > 2)
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266 case PICO_INPUT_PAD_3BTN:
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267 func = read_pad_3btn;
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270 case PICO_INPUT_PAD_6BTN:
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271 func = read_pad_6btn;
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275 func = read_nothing;
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279 port_readers[port] = func;
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282 NOINLINE u32 io_ports_read(u32 a)
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287 case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
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288 case 1: d = port_read(0); break;
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289 case 2: d = port_read(1); break;
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290 case 3: d = port_read(2); break;
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291 default: d = Pico.ioports[a]; break; // IO ports can be used as RAM
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296 NOINLINE void io_ports_write(u32 a, u32 d)
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300 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
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301 if (1 <= a && a <= 2)
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303 Pico.m.padDelay[a - 1] = 0;
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304 if (!(Pico.ioports[a] & 0x40) && (d & 0x40))
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305 Pico.m.padTHPhase[a - 1]++;
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308 // certain IO ports can be used as RAM
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309 Pico.ioports[a] = d;
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312 void NOINLINE ctl_write_z80busreq(u32 d)
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315 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
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316 if (d ^ Pico.m.z80Run)
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320 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
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324 z80stopCycle = SekCyclesDone();
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325 if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {
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327 PicoSyncZ80(z80stopCycle);
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328 pprof_end_sub(m68k);
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335 void NOINLINE ctl_write_z80reset(u32 d)
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338 elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);
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339 if (d ^ Pico.m.z80_reset)
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343 if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run) {
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345 PicoSyncZ80(SekCyclesDone());
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346 pprof_end_sub(m68k);
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353 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
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356 Pico.m.z80_reset = d;
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360 // -----------------------------------------------------------------
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362 #ifndef _ASM_MEMORY_C
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364 // cart (save) RAM area (usually 0x200000 - ...)
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365 static u32 PicoRead8_sram(u32 a)
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368 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))
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370 if (SRam.flags & SRF_EEPROM) {
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375 d = *(u8 *)(SRam.data - SRam.start + a);
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376 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
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380 // XXX: this is banking unfriendly
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381 if (a < Pico.romsize)
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382 return Pico.rom[a ^ 1];
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384 return m68k_unmapped_read8(a);
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387 static u32 PicoRead16_sram(u32 a)
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390 if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))
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392 if (SRam.flags & SRF_EEPROM)
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395 u8 *pm = (u8 *)(SRam.data - SRam.start + a);
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399 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
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403 if (a < Pico.romsize)
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404 return *(u16 *)(Pico.rom + a);
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406 return m68k_unmapped_read16(a);
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409 #endif // _ASM_MEMORY_C
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411 static void PicoWrite8_sram(u32 a, u32 d)
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413 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
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414 m68k_unmapped_write8(a, d);
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418 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);
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419 if (SRam.flags & SRF_EEPROM)
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421 EEPROM_write8(a, d);
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424 u8 *pm = (u8 *)(SRam.data - SRam.start + a);
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425 if (*pm != (u8)d) {
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432 static void PicoWrite16_sram(u32 a, u32 d)
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434 if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
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435 m68k_unmapped_write16(a, d);
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439 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);
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440 if (SRam.flags & SRF_EEPROM)
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445 // XXX: hardware could easily use MSB too..
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446 u8 *pm = (u8 *)(SRam.data - SRam.start + a);
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447 if (*pm != (u8)d) {
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454 // z80 area (0xa00000 - 0xa0ffff)
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455 // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)
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456 static u32 PicoRead8_z80(u32 a)
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459 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
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460 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
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461 // open bus. Pulled down if MegaCD2 is attached.
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465 if ((a & 0x4000) == 0x0000)
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466 d = Pico.zram[a & 0x1fff];
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467 else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff
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468 d = ym2612_read_local_68k();
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470 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
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474 static u32 PicoRead16_z80(u32 a)
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476 u32 d = PicoRead8_z80(a);
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477 return d | (d << 8);
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480 static void PicoWrite8_z80(u32 a, u32 d)
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482 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
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483 // verified on real hw
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484 elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
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488 if ((a & 0x4000) == 0x0000) { // z80 RAM
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489 SekCyclesBurn(2); // hack
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490 Pico.zram[a & 0x1fff] = (u8)d;
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493 if ((a & 0x6000) == 0x4000) { // FM Sound
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494 if (PicoOpt & POPT_EN_FM)
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495 emustatus |= ym2612_write_local(a&3, d&0xff, 0)&1;
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498 // TODO: probably other VDP access too? Maybe more mirrors?
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499 if ((a & 0x7ff9) == 0x7f11) { // PSG Sound
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500 if (PicoOpt & POPT_EN_PSG)
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504 if ((a & 0x7f00) == 0x6000) // Z80 BANK register
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506 Pico.m.z80_bank68k >>= 1;
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507 Pico.m.z80_bank68k |= d << 8;
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508 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
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509 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);
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512 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);
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515 static void PicoWrite16_z80(u32 a, u32 d)
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517 // for RAM, only most significant byte is sent
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518 // TODO: verify remaining accesses
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519 PicoWrite8_z80(a, d >> 8);
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522 #ifndef _ASM_MEMORY_C
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524 // IO/control area (0xa10000 - 0xa1ffff)
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525 u32 PicoRead8_io(u32 a)
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529 if ((a & 0xffe0) == 0x0000) { // I/O ports
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530 d = io_ports_read(a);
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534 // faking open bus (MegaCD pulldowns don't work here curiously)
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535 d = Pico.m.rotate++;
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538 if ((a & 0xfc00) == 0x1000) {
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539 // bit8 seems to be readable in this range
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543 if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)
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544 d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;
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545 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d, SekCyclesDone(), SekPc);
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550 if (PicoOpt & POPT_EN_32X) {
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551 d = PicoRead8_32x(a);
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555 d = m68k_unmapped_read8(a);
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560 u32 PicoRead16_io(u32 a)
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564 if ((a & 0xffe0) == 0x0000) { // I/O ports
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565 d = io_ports_read(a);
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571 d = (Pico.m.rotate += 0x41);
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572 d ^= (d << 5) ^ (d << 8);
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574 // bit8 seems to be readable in this range
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575 if ((a & 0xfc00) == 0x1000) {
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578 if ((a & 0xff00) == 0x1100) { // z80 busreq
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579 d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;
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580 elprintf(EL_BUSREQ, "get_zrun: %04x [%i] @%06x", d, SekCyclesDone(), SekPc);
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585 if (PicoOpt & POPT_EN_32X) {
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586 d = PicoRead16_32x(a);
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590 d = m68k_unmapped_read16(a);
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595 void PicoWrite8_io(u32 a, u32 d)
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597 if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)
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598 io_ports_write(a, d);
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601 if ((a & 0xff01) == 0x1100) { // z80 busreq
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602 ctl_write_z80busreq(d);
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605 if ((a & 0xff01) == 0x1200) { // z80 reset
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606 ctl_write_z80reset(d);
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609 if (a == 0xa130f1) { // sram access register
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610 elprintf(EL_SRAMIO, "sram reg=%02x", d);
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611 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
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612 Pico.m.sram_reg |= (u8)(d & 3);
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615 if (PicoOpt & POPT_EN_32X) {
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616 PicoWrite8_32x(a, d);
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620 m68k_unmapped_write8(a, d);
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623 void PicoWrite16_io(u32 a, u32 d)
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625 if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)
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626 io_ports_write(a, d);
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629 if ((a & 0xff00) == 0x1100) { // z80 busreq
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630 ctl_write_z80busreq(d >> 8);
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633 if ((a & 0xff00) == 0x1200) { // z80 reset
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634 ctl_write_z80reset(d >> 8);
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637 if (a == 0xa130f0) { // sram access register
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638 elprintf(EL_SRAMIO, "sram reg=%02x", d);
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639 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
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640 Pico.m.sram_reg |= (u8)(d & 3);
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643 if (PicoOpt & POPT_EN_32X) {
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644 PicoWrite16_32x(a, d);
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647 m68k_unmapped_write16(a, d);
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650 #endif // _ASM_MEMORY_C
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652 // VDP area (0xc00000 - 0xdfffff)
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653 // TODO: verify if lower byte goes to PSG on word writes
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654 static u32 PicoRead8_vdp(u32 a)
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656 if ((a & 0x00e0) == 0x0000)
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657 return PicoVideoRead8(a);
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659 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
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663 static u32 PicoRead16_vdp(u32 a)
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665 if ((a & 0x00e0) == 0x0000)
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666 return PicoVideoRead(a);
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668 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
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672 static void PicoWrite8_vdp(u32 a, u32 d)
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674 if ((a & 0x00f9) == 0x0011) { // PSG Sound
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675 if (PicoOpt & POPT_EN_PSG)
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679 if ((a & 0x00e0) == 0x0000) {
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681 PicoVideoWrite(a, d | (d << 8));
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685 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);
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688 static void PicoWrite16_vdp(u32 a, u32 d)
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690 if ((a & 0x00f9) == 0x0010) { // PSG Sound
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691 if (PicoOpt & POPT_EN_PSG)
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695 if ((a & 0x00e0) == 0x0000) {
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696 PicoVideoWrite(a, d);
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700 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);
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703 // -----------------------------------------------------------------
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706 static void m68k_mem_setup(void);
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709 PICO_INTERNAL void PicoMemSetup(void)
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713 // setup the memory map
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714 cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);
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715 cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);
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716 cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);
\r
717 cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);
\r
720 // align to bank size. We know ROM loader allocated enough for this
\r
721 mask = (1 << M68K_MEM_SHIFT) - 1;
\r
722 rs = (Pico.romsize + mask) & ~mask;
\r
723 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);
\r
724 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);
\r
726 // Common case of on-cart (save) RAM, usually at 0x200000-...
\r
727 if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {
\r
728 rs = SRam.end - SRam.start;
\r
729 rs = (rs + mask) & ~mask;
\r
730 if (SRam.start + rs >= 0x1000000)
\r
731 rs = 0x1000000 - SRam.start;
\r
732 cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);
\r
733 cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);
\r
734 cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);
\r
735 cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);
\r
739 cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);
\r
740 cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);
\r
741 cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);
\r
742 cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);
\r
744 // IO/control region
\r
745 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);
\r
746 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);
\r
747 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);
\r
748 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);
\r
751 for (a = 0xc00000; a < 0xe00000; a += 0x010000) {
\r
752 if ((a & 0xe700e0) != 0xc00000)
\r
754 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);
\r
755 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);
\r
756 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);
\r
757 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);
\r
760 // RAM and it's mirrors
\r
761 for (a = 0xe00000; a < 0x1000000; a += 0x010000) {
\r
762 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);
\r
763 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);
\r
764 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);
\r
765 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);
\r
768 // Setup memory callbacks:
\r
770 PicoCpuCM68k.read8 = (void *)m68k_read8_map;
\r
771 PicoCpuCM68k.read16 = (void *)m68k_read16_map;
\r
772 PicoCpuCM68k.read32 = (void *)m68k_read16_map;
\r
773 PicoCpuCM68k.write8 = (void *)m68k_write8_map;
\r
774 PicoCpuCM68k.write16 = (void *)m68k_write16_map;
\r
775 PicoCpuCM68k.write32 = (void *)m68k_write16_map;
\r
776 PicoCpuCM68k.checkpc = NULL; /* unused */
\r
777 PicoCpuCM68k.fetch8 = NULL;
\r
778 PicoCpuCM68k.fetch16 = NULL;
\r
779 PicoCpuCM68k.fetch32 = NULL;
\r
782 PicoCpuFM68k.read_byte = m68k_read8;
\r
783 PicoCpuFM68k.read_word = m68k_read16;
\r
784 PicoCpuFM68k.read_long = m68k_read32;
\r
785 PicoCpuFM68k.write_byte = m68k_write8;
\r
786 PicoCpuFM68k.write_word = m68k_write16;
\r
787 PicoCpuFM68k.write_long = m68k_write32;
\r
789 // setup FAME fetchmap
\r
792 // by default, point everything to first 64k of ROM
\r
793 for (i = 0; i < M68K_FETCHBANK1; i++)
\r
794 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
\r
796 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
\r
797 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;
\r
799 for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)
\r
800 PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.ram - (i<<(24-FAMEC_FETCHBITS));
\r
811 unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;
\r
812 unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;
\r
813 unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;
\r
814 void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;
\r
815 void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;
\r
816 void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;
\r
818 /* it appears that Musashi doesn't always mask the unused bits */
\r
819 unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }
\r
820 unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }
\r
821 unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }
\r
822 void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }
\r
823 void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }
\r
824 void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }
\r
826 static void m68k_mem_setup(void)
\r
828 pm68k_read_memory_8 = m68k_read8;
\r
829 pm68k_read_memory_16 = m68k_read16;
\r
830 pm68k_read_memory_32 = m68k_read32;
\r
831 pm68k_write_memory_8 = m68k_write8;
\r
832 pm68k_write_memory_16 = m68k_write16;
\r
833 pm68k_write_memory_32 = m68k_write32;
\r
838 // -----------------------------------------------------------------
\r
840 static int get_scanline(int is_from_z80)
\r
843 int cycles = z80_cyclesDone();
\r
844 while (cycles - z80_scanline_cycles >= 228)
\r
845 z80_scanline++, z80_scanline_cycles += 228;
\r
846 return z80_scanline;
\r
849 return Pico.m.scanline;
\r
852 /* probably should not be in this file, but it's near related code here */
\r
853 void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)
\r
855 int xcycles = z80_cycles << 8;
\r
857 /* check for overflows */
\r
858 if ((mode_old & 4) && xcycles > timer_a_next_oflow)
\r
859 ym2612.OPN.ST.status |= 1;
\r
861 if ((mode_old & 8) && xcycles > timer_b_next_oflow)
\r
862 ym2612.OPN.ST.status |= 2;
\r
864 /* update timer a */
\r
866 while (xcycles > timer_a_next_oflow)
\r
867 timer_a_next_oflow += timer_a_step;
\r
869 if ((mode_old ^ mode_new) & 1) // turning on/off
\r
872 timer_a_next_oflow = TIMER_NO_OFLOW;
\r
874 timer_a_next_oflow = xcycles + timer_a_step;
\r
877 elprintf(EL_YMTIMER, "timer a upd to %i @ %i", timer_a_next_oflow>>8, z80_cycles);
\r
879 /* update timer b */
\r
881 while (xcycles > timer_b_next_oflow)
\r
882 timer_b_next_oflow += timer_b_step;
\r
884 if ((mode_old ^ mode_new) & 2)
\r
887 timer_b_next_oflow = TIMER_NO_OFLOW;
\r
889 timer_b_next_oflow = xcycles + timer_b_step;
\r
892 elprintf(EL_YMTIMER, "timer b upd to %i @ %i", timer_b_next_oflow>>8, z80_cycles);
\r
895 // ym2612 DAC and timer I/O handlers for z80
\r
896 static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
\r
901 if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */
\r
903 int scanline = get_scanline(is_from_z80);
\r
904 //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", PsndDacLine, scanline, d, is_from_z80);
\r
905 ym2612.dacout = ((int)d - 0x80) << 6;
\r
906 if (PsndOut && ym2612.dacen && scanline >= PsndDacLine)
\r
907 PsndDoDAC(scanline);
\r
913 case 0: /* address port 0 */
\r
914 ym2612.OPN.ST.address = d;
\r
915 ym2612.addr_A1 = 0;
\r
917 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
\r
921 case 1: /* data port 0 */
\r
922 if (ym2612.addr_A1 != 0)
\r
925 addr = ym2612.OPN.ST.address;
\r
926 ym2612.REGS[addr] = d;
\r
930 case 0x24: // timer A High 8
\r
931 case 0x25: { // timer A Low 2
\r
932 int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))
\r
933 : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));
\r
934 if (ym2612.OPN.ST.TA != TAnew)
\r
936 //elprintf(EL_STATUS, "timer a set %i", TAnew);
\r
937 ym2612.OPN.ST.TA = TAnew;
\r
938 //ym2612.OPN.ST.TAC = (1024-TAnew)*18;
\r
939 //ym2612.OPN.ST.TAT = 0;
\r
940 timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
\r
941 if (ym2612.OPN.ST.mode & 1) {
\r
942 // this is not right, should really be done on overflow only
\r
943 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
\r
944 timer_a_next_oflow = (cycles << 8) + timer_a_step;
\r
946 elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);
\r
950 case 0x26: // timer B
\r
951 if (ym2612.OPN.ST.TB != d) {
\r
952 //elprintf(EL_STATUS, "timer b set %i", d);
\r
953 ym2612.OPN.ST.TB = d;
\r
954 //ym2612.OPN.ST.TBC = (256-d) * 288;
\r
955 //ym2612.OPN.ST.TBT = 0;
\r
956 timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
\r
957 if (ym2612.OPN.ST.mode & 2) {
\r
958 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
\r
959 timer_b_next_oflow = (cycles << 8) + timer_b_step;
\r
961 elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);
\r
964 case 0x27: { /* mode, timer control */
\r
965 int old_mode = ym2612.OPN.ST.mode;
\r
966 int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
\r
967 ym2612.OPN.ST.mode = d;
\r
969 elprintf(EL_YMTIMER, "st mode %02x", d);
\r
970 ym2612_sync_timers(cycles, old_mode, d);
\r
972 /* reset Timer a flag */
\r
974 ym2612.OPN.ST.status &= ~1;
\r
976 /* reset Timer b flag */
\r
978 ym2612.OPN.ST.status &= ~2;
\r
980 if ((d ^ old_mode) & 0xc0) {
\r
982 if (PicoOpt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));
\r
988 case 0x2b: { /* DAC Sel (YM2612) */
\r
989 int scanline = get_scanline(is_from_z80);
\r
990 ym2612.dacen = d & 0x80;
\r
991 if (d & 0x80) PsndDacLine = scanline;
\r
993 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);
\r
1000 case 2: /* address port 1 */
\r
1001 ym2612.OPN.ST.address = d;
\r
1002 ym2612.addr_A1 = 1;
\r
1004 if (PicoOpt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
\r
1008 case 3: /* data port 1 */
\r
1009 if (ym2612.addr_A1 != 1)
\r
1012 addr = ym2612.OPN.ST.address | 0x100;
\r
1013 ym2612.REGS[addr] = d;
\r
1018 if (PicoOpt & POPT_EXT_FM)
\r
1019 return YM2612Write_940(a, d, get_scanline(is_from_z80));
\r
1021 return YM2612Write_(a, d);
\r
1025 #define ym2612_read_local() \
\r
1026 if (xcycles >= timer_a_next_oflow) \
\r
1027 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \
\r
1028 if (xcycles >= timer_b_next_oflow) \
\r
1029 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2
\r
1031 static u32 ym2612_read_local_z80(void)
\r
1033 int xcycles = z80_cyclesDone() << 8;
\r
1035 ym2612_read_local();
\r
1037 elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,
\r
1038 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);
\r
1039 return ym2612.OPN.ST.status;
\r
1042 static u32 ym2612_read_local_68k(void)
\r
1044 int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;
\r
1046 ym2612_read_local();
\r
1048 elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i", ym2612.OPN.ST.status,
\r
1049 timer_a_next_oflow>>8, timer_b_next_oflow>>8, xcycles >> 8, (xcycles >> 8) / 228);
\r
1050 return ym2612.OPN.ST.status;
\r
1053 void ym2612_pack_state(void)
\r
1055 // timers are saved as tick counts, in 16.16 int format
\r
1056 int tac, tat = 0, tbc, tbt = 0;
\r
1057 tac = 1024 - ym2612.OPN.ST.TA;
\r
1058 tbc = 256 - ym2612.OPN.ST.TB;
\r
1059 if (timer_a_next_oflow != TIMER_NO_OFLOW)
\r
1060 tat = (int)((double)(timer_a_step - timer_a_next_oflow) / (double)timer_a_step * tac * 65536);
\r
1061 if (timer_b_next_oflow != TIMER_NO_OFLOW)
\r
1062 tbt = (int)((double)(timer_b_step - timer_b_next_oflow) / (double)timer_b_step * tbc * 65536);
\r
1063 elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);
\r
1064 elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);
\r
1067 if (PicoOpt & POPT_EXT_FM)
\r
1068 YM2612PicoStateSave2_940(tat, tbt);
\r
1071 YM2612PicoStateSave2(tat, tbt);
\r
1074 void ym2612_unpack_state(void)
\r
1076 int i, ret, tac, tat, tbc, tbt;
\r
1077 YM2612PicoStateLoad();
\r
1079 // feed all the registers and update internal state
\r
1080 for (i = 0x20; i < 0xA0; i++) {
\r
1081 ym2612_write_local(0, i, 0);
\r
1082 ym2612_write_local(1, ym2612.REGS[i], 0);
\r
1084 for (i = 0x30; i < 0xA0; i++) {
\r
1085 ym2612_write_local(2, i, 0);
\r
1086 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
\r
1088 for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards
\r
1089 ym2612_write_local(2, i, 0);
\r
1090 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
\r
1091 ym2612_write_local(0, i, 0);
\r
1092 ym2612_write_local(1, ym2612.REGS[i], 0);
\r
1094 for (i = 0xB0; i < 0xB8; i++) {
\r
1095 ym2612_write_local(0, i, 0);
\r
1096 ym2612_write_local(1, ym2612.REGS[i], 0);
\r
1097 ym2612_write_local(2, i, 0);
\r
1098 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
\r
1102 if (PicoOpt & POPT_EXT_FM)
\r
1103 ret = YM2612PicoStateLoad2_940(&tat, &tbt);
\r
1106 ret = YM2612PicoStateLoad2(&tat, &tbt);
\r
1108 elprintf(EL_STATUS, "old ym2612 state");
\r
1109 return; // no saved timers
\r
1112 tac = (1024 - ym2612.OPN.ST.TA) << 16;
\r
1113 tbc = (256 - ym2612.OPN.ST.TB) << 16;
\r
1114 if (ym2612.OPN.ST.mode & 1)
\r
1115 timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * timer_a_step);
\r
1117 timer_a_next_oflow = TIMER_NO_OFLOW;
\r
1118 if (ym2612.OPN.ST.mode & 2)
\r
1119 timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * timer_b_step);
\r
1121 timer_b_next_oflow = TIMER_NO_OFLOW;
\r
1122 elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, timer_a_next_oflow >> 8);
\r
1123 elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, timer_b_next_oflow >> 8);
\r
1126 #if defined(NO_32X) && defined(_ASM_MEMORY_C)
\r
1127 // referenced by asm code
\r
1128 u32 PicoRead8_32x(u32 a) { return 0; }
\r
1129 u32 PicoRead16_32x(u32 a) { return 0; }
\r
1130 void PicoWrite8_32x(u32 a, u32 d) {}
\r
1131 void PicoWrite16_32x(u32 a, u32 d) {}
\r
1134 // -----------------------------------------------------------------
\r
1135 // z80 memhandlers
\r
1137 static unsigned char z80_md_vdp_read(unsigned short a)
\r
1140 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);
\r
1144 static unsigned char z80_md_bank_read(unsigned short a)
\r
1146 unsigned int addr68k;
\r
1147 unsigned char ret;
\r
1149 addr68k = Pico.m.z80_bank68k<<15;
\r
1150 addr68k += a & 0x7fff;
\r
1152 ret = m68k_read8(addr68k);
\r
1154 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
\r
1158 static void z80_md_ym2612_write(unsigned int a, unsigned char data)
\r
1160 if (PicoOpt & POPT_EN_FM)
\r
1161 emustatus |= ym2612_write_local(a, data, 1) & 1;
\r
1164 static void z80_md_vdp_br_write(unsigned int a, unsigned char data)
\r
1166 // TODO: allow full VDP access
\r
1167 if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17
\r
1169 if (PicoOpt & POPT_EN_PSG)
\r
1170 SN76496Write(data);
\r
1174 if ((a>>8) == 0x60)
\r
1176 Pico.m.z80_bank68k >>= 1;
\r
1177 Pico.m.z80_bank68k |= data << 8;
\r
1178 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
\r
1182 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
\r
1185 static void z80_md_bank_write(unsigned int a, unsigned char data)
\r
1187 unsigned int addr68k;
\r
1189 addr68k = Pico.m.z80_bank68k << 15;
\r
1190 addr68k += a & 0x7fff;
\r
1192 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
\r
1193 m68k_write8(addr68k, data);
\r
1196 // -----------------------------------------------------------------
\r
1198 static unsigned char z80_md_in(unsigned short p)
\r
1200 elprintf(EL_ANOMALY, "Z80 port %04x read", p);
\r
1204 static void z80_md_out(unsigned short p, unsigned char d)
\r
1206 elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);
\r
1209 static void z80_mem_setup(void)
\r
1211 z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);
\r
1212 z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);
\r
1213 z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);
\r
1214 z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);
\r
1215 z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);
\r
1217 z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);
\r
1218 z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);
\r
1219 z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);
\r
1220 z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);
\r
1221 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);
\r
1224 drZ80.z80_in = z80_md_in;
\r
1225 drZ80.z80_out = z80_md_out;
\r
1228 Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM
\r
1229 Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror
\r
1230 Cz80_Set_INPort(&CZ80, z80_md_in);
\r
1231 Cz80_Set_OUTPort(&CZ80, z80_md_out);
\r
1235 // vim:shiftwidth=2:ts=2:expandtab
\r