2 * PicoDrive - Internal Header File
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3 * (c) Copyright Dave, 2004
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4 * (C) notaz, 2006-2010
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6 * This work is licensed under the terms of MAME license.
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7 * See COPYING file in the top-level directory.
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10 #ifndef PICO_INTERNAL_INCLUDED
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11 #define PICO_INTERNAL_INCLUDED
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17 #include "carthw/carthw.h"
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20 #define USE_POLL_DETECT
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22 #ifndef PICO_INTERNAL
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23 #define PICO_INTERNAL
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25 #ifndef PICO_INTERNAL_ASM
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26 #define PICO_INTERNAL_ASM
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29 // to select core, define EMU_C68K, EMU_M68K or EMU_F68K in your makefile or project
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36 #define snprintf _snprintf
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37 #define strcasecmp _stricmp
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38 #define strncasecmp _strnicmp
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41 // ----------------------- 68000 CPU -----------------------
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43 #include "../cpu/cyclone/Cyclone.h"
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44 extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
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45 #define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run
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46 #define SekCyclesLeftS68k PicoCpuCS68k.cycles
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47 #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)
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48 #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)
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49 #define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])
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50 #define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])
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51 #define SekSr CycloneGetSr(&PicoCpuCM68k)
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52 #define SekSrS68k CycloneGetSr(&PicoCpuCS68k)
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53 #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }
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54 #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }
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55 #define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)
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56 #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)
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57 #define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
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59 #define SekNotPolling PicoCpuCM68k.not_pol
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60 #define SekNotPollingS68k PicoCpuCS68k.not_pol
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62 #define SekInterrupt(i) PicoCpuCM68k.irq=i
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63 #define SekIrqLevel PicoCpuCM68k.irq
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68 #include "../cpu/fame/fame.h"
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69 extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
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70 #define SekCyclesLeft PicoCpuFM68k.io_cycle_counter
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71 #define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter
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72 #define SekPc fm68k_get_pc(&PicoCpuFM68k)
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73 #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)
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74 #define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)
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75 #define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)
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76 #define SekSr PicoCpuFM68k.sr
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77 #define SekSrS68k PicoCpuFS68k.sr
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78 #define SekSetStop(x) { \
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79 PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \
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80 if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \
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82 #define SekSetStopS68k(x) { \
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83 PicoCpuFS68k.execinfo &= ~FM68K_HALTED; \
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84 if (x) { PicoCpuFS68k.execinfo |= FM68K_HALTED; PicoCpuFS68k.io_cycle_counter = 0; } \
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86 #define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)
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87 #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)
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88 #define SekShouldInterrupt() fm68k_would_interrupt()
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90 #define SekNotPolling PicoCpuFM68k.not_polling
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91 #define SekNotPollingS68k PicoCpuFS68k.not_polling
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93 #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq
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94 #define SekIrqLevel PicoCpuFM68k.interrupts[0]
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99 #include "../cpu/musashi/m68kcpu.h"
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100 extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
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101 #ifndef SekCyclesLeft
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102 #define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles
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103 #define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles
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104 #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)
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105 #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)
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106 #define SekDar(x) PicoCpuMM68k.dar[x]
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107 #define SekDarS68k(x) PicoCpuMS68k.dar[x]
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108 #define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
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109 #define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)
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110 #define SekSetStop(x) { \
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111 if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \
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112 else PicoCpuMM68k.stopped=0; \
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114 #define SekSetStopS68k(x) { \
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115 if(x) { SET_CYCLES(0); PicoCpuMS68k.stopped=STOP_LEVEL_STOP; } \
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116 else PicoCpuMS68k.stopped=0; \
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118 #define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)
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119 #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)
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120 #define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)
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122 #define SekNotPolling PicoCpuMM68k.not_polling
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123 #define SekNotPollingS68k PicoCpuMS68k.not_polling
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125 #define SekInterrupt(irq) { \
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126 void *oldcontext = m68ki_cpu_p; \
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127 m68k_set_context(&PicoCpuMM68k); \
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128 m68k_set_irq(irq); \
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129 m68k_set_context(oldcontext); \
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131 #define SekIrqLevel (PicoCpuMM68k.int_level >> 8)
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136 // while running, cnt represents target of current timeslice
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137 // while not in SekRun(), it's actual cycles done
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138 // (but always use SekCyclesDone() if you need current position)
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139 // cnt may change if timeslice is ended prematurely or extended,
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140 // so we use SekCycleAim for the actual target
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141 extern unsigned int SekCycleCnt;
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142 extern unsigned int SekCycleAim;
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144 // number of cycles done (can be checked anywhere)
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145 #define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)
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147 // burn cycles while not in SekRun() and while in
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148 #define SekCyclesBurn(c) SekCycleCnt += c
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149 #define SekCyclesBurnRun(c) { \
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150 SekCyclesLeft -= c; \
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153 // note: sometimes may extend timeslice to delay an irq
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154 #define SekEndRun(after) { \
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155 SekCycleCnt -= SekCyclesLeft - (after); \
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156 SekCyclesLeft = after; \
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159 extern unsigned int SekCycleCntS68k;
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160 extern unsigned int SekCycleAimS68k;
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162 #define SekEndRunS68k(after) { \
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163 if (SekCyclesLeftS68k > (after)) { \
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164 SekCycleCntS68k -= SekCyclesLeftS68k - (after); \
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165 SekCyclesLeftS68k = after; \
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169 #define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)
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171 // compare cycles, handling overflows
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173 #define CYCLES_GT(a, b) \
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174 ((int)((a) - (b)) > 0)
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176 #define CYCLES_GE(a, b) \
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177 ((int)((a) - (b)) >= 0)
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179 // ----------------------- Z80 CPU -----------------------
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181 #if defined(_USE_DRZ80)
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182 #include "../cpu/DrZ80/drz80.h"
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184 extern struct DrZ80 drZ80;
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186 #define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))
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187 #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)
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188 #define z80_int() drZ80.Z80_IRQ = 1
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189 #define z80_int() drZ80.Z80_IRQ = 1
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190 #define z80_nmi() drZ80.Z80IF |= 8
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192 #define z80_cyclesLeft drZ80.cycles
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193 #define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)
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195 #elif defined(_USE_CZ80)
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196 #include "../cpu/cz80/cz80.h"
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198 #define z80_run(cycles) Cz80_Exec(&CZ80, cycles)
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199 #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)
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200 #define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)
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201 #define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)
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203 #define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)
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204 #define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)
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208 #define z80_run(cycles) (cycles)
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209 #define z80_run_nr(cycles)
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215 #define Z80_STATE_SIZE 0x60
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217 extern unsigned int last_z80_sync;
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218 extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */
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219 extern int z80_cycle_aim;
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220 extern int z80_scanline;
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221 extern int z80_scanline_cycles; /* cycles done until z80_scanline */
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223 #define z80_resetCycles() \
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224 last_z80_sync = SekCyclesDone(); \
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225 z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;
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227 #define z80_cyclesDone() \
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228 (z80_cycle_aim - z80_cyclesLeft)
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230 #define cycles_68k_to_z80(x) ((x)*957 >> 11)
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232 // ----------------------- SH2 CPU -----------------------
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234 #include "cpu/sh2/sh2.h"
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236 extern SH2 sh2s[2];
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237 #define msh2 sh2s[0]
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238 #define ssh2 sh2s[1]
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241 # define sh2_end_run(sh2, after_) do { \
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242 if ((sh2)->icount > (after_)) { \
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243 (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \
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244 (sh2)->icount = after_; \
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247 # define sh2_cycles_left(sh2) (sh2)->icount
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248 # define sh2_burn_cycles(sh2, n) (sh2)->icount -= n
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249 # define sh2_pc(sh2) (sh2)->ppc
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251 # define sh2_end_run(sh2, after_) do { \
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252 int left_ = (signed int)(sh2)->sr >> 12; \
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253 if (left_ > (after_)) { \
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254 (sh2)->cycles_timeslice -= left_ - (after_); \
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255 (sh2)->sr &= 0xfff; \
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256 (sh2)->sr |= (after_) << 12; \
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259 # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)
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260 # define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)
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261 # define sh2_pc(sh2) (sh2)->pc
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264 #define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))
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265 #define sh2_cycles_done_t(sh2) \
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266 ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))
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267 #define sh2_cycles_done_m68k(sh2) \
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268 ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))
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270 #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]
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271 #define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr
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272 #define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr
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273 #define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)
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275 #define sh2_set_gbr(c, v) \
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276 { if (c) ssh2.gbr = v; else msh2.gbr = v; }
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277 #define sh2_set_vbr(c, v) \
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278 { if (c) ssh2.vbr = v; else msh2.vbr = v; }
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280 #define elprintf_sh2(sh2, w, f, ...) \
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281 elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)
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283 // ---------------------------------------------------------
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285 // main oscillator clock which controls timing
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286 #define OSC_NTSC 53693100
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287 #define OSC_PAL 53203424
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291 unsigned char reg[0x20];
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292 unsigned int command; // 32-bit Command
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293 unsigned char pending; // 1 if waiting for second half of 32-bit command
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294 unsigned char type; // Command type (v/c/vsram read/write)
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295 unsigned short addr; // Read/Write address
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296 int status; // Status bits
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297 unsigned char pending_ints; // pending interrupts: ??VH????
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298 signed char lwrite_cnt; // VDP write count during active display line
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299 unsigned short v_counter; // V-counter
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300 unsigned char pad[0x10];
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305 unsigned char rotate;
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306 unsigned char z80Run;
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307 unsigned char padTHPhase[2]; // 02 phase of gamepad TH switches
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308 unsigned short scanline; // 04 0 to 261||311
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309 char dirtyPal; // 06 Is the palette dirty (1 - change @ this frame, 2 - some time before)
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310 unsigned char hardware; // 07 Hardware value for country
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311 unsigned char pal; // 08 1=PAL 0=NTSC
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312 unsigned char sram_reg; // 09 SRAM reg. See SRR_* below
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313 unsigned short z80_bank68k; // 0a
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314 unsigned short pad0;
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315 unsigned char ncart_in; // 0e !cart_in
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316 unsigned char z80_reset; // 0f z80 reset held
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317 unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay
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318 unsigned short eeprom_addr; // EEPROM address register
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319 unsigned char eeprom_cycle; // EEPROM cycle number
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320 unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs
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321 unsigned char eeprom_status;
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322 unsigned char pad2;
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323 unsigned short dma_xfers; // 18
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324 unsigned char eeprom_wb[2]; // EEPROM latch/write buffer
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325 unsigned int frame_count; // 1c for movies and idle det
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330 unsigned char carthw[0x10];
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331 unsigned char io_ctl;
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332 unsigned char nmi_state;
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333 unsigned char pad[0x4e];
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336 // some assembly stuff depend on these, do not touch!
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339 unsigned char ram[0x10000]; // 0x00000 scratch ram
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340 union { // vram is byteswapped for easier reads when drawing
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341 unsigned short vram[0x8000]; // 0x10000
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342 unsigned char vramb[0x4000]; // VRAM in SMS mode
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344 unsigned char zram[0x2000]; // 0x20000 Z80 ram
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345 unsigned char ioports[0x10]; // XXX: fix asm and mv
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346 unsigned char pad[0xf0]; // unused
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347 unsigned short cram[0x40]; // 0x22100
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348 unsigned short vsram[0x40]; // 0x22180
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350 unsigned char *rom; // 0x22200
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351 unsigned int romsize; // 0x22204 (on 32bits)
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354 struct PicoVideo video;
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359 #define SRR_MAPPED (1 << 0)
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360 #define SRR_READONLY (1 << 1)
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362 #define SRF_ENABLED (1 << 0)
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363 #define SRF_EEPROM (1 << 1)
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367 unsigned char *data; // actual data
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368 unsigned int start; // start address in 68k address space
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370 unsigned char flags; // 0c: SRF_*
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371 unsigned char unused2;
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372 unsigned char changed;
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373 unsigned char eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words
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374 unsigned char unused3;
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375 unsigned char eeprom_bit_cl; // bit number for cl
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376 unsigned char eeprom_bit_in; // bit number for in
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377 unsigned char eeprom_bit_out; // bit number for out
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382 #define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)
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386 unsigned char control; // reg7
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387 unsigned char enabled; // reg8
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388 unsigned char cur_ch;
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389 unsigned char bank;
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390 unsigned int update_cycles;
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392 struct pcm_chan // 08, size 0x10
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394 unsigned char regs[8];
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395 unsigned int addr; // .08: played sample address
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400 #define PCD_ST_S68K_RST 1
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404 unsigned short hint_vector;
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405 unsigned char busreq; // not s68k_regs[1]
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406 unsigned char s68k_pend_ints;
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407 unsigned int state_flags; // 04
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408 unsigned int stopwatch_base_c;
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409 unsigned short m68k_poll_a;
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410 unsigned short m68k_poll_cnt;
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411 unsigned short s68k_poll_a;
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412 unsigned short s68k_poll_cnt;
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413 unsigned int s68k_poll_clk;
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414 unsigned char bcram_reg; // 18: battery-backed RAM cart register
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415 unsigned char dmna_ret_2m;
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416 unsigned char need_sync;
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417 unsigned char pad3;
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423 unsigned char bios[0x20000]; // 000000: 128K
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424 union { // 020000: 512K
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425 unsigned char prg_ram[0x80000];
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426 unsigned char prg_ram_b[4][0x20000];
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428 union { // 0a0000: 256K
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430 unsigned char word_ram2M[0x40000];
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431 unsigned char unused0[0x20000];
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434 unsigned char unused1[0x20000];
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435 unsigned char word_ram1M[2][0x20000];
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438 union { // 100000: 64K
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439 unsigned char pcm_ram[0x10000];
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440 unsigned char pcm_ram_b[0x10][0x1000];
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442 unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs
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443 unsigned char bram[0x2000]; // 110200: 8K
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444 struct mcd_misc m; // 112200: misc
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445 struct mcd_pcm pcm; // 112240:
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448 int pcm_mixbuf[PCM_MIXBUF_LEN * 2];
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450 char pcm_mixbuf_dirty;
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451 char pcm_regs_dirty;
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454 // XXX: this will need to be reworked for cart+cd support.
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455 #define Pico_mcd ((mcd_state *)Pico.rom)
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458 #define P32XS_FM (1<<15)
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459 #define P32XS_nCART (1<< 8)
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460 #define P32XS_REN (1<< 7)
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461 #define P32XS_nRES (1<< 1)
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462 #define P32XS_ADEN (1<< 0)
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463 #define P32XS2_ADEN (1<< 9)
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464 #define P32XS_FULL (1<< 7) // DREQ FIFO full
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465 #define P32XS_68S (1<< 2)
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466 #define P32XS_DMA (1<< 1)
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467 #define P32XS_RV (1<< 0)
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469 #define P32XV_nPAL (1<<15) // VDP
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470 #define P32XV_PRI (1<< 7)
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471 #define P32XV_Mx (3<< 0) // display mode mask
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473 #define P32XV_SFT (1<< 0)
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475 #define P32XV_VBLK (1<<15)
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476 #define P32XV_HBLK (1<<14)
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477 #define P32XV_PEN (1<<13)
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478 #define P32XV_nFEN (1<< 1)
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479 #define P32XV_FS (1<< 0)
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481 #define P32XP_RTP (1<<7) // PWM control
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482 #define P32XP_FULL (1<<15) // PWM pulse
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483 #define P32XP_EMPTY (1<<14)
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485 #define P32XF_68KCPOLL (1 << 0)
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486 #define P32XF_68KVPOLL (1 << 1)
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487 #define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io
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489 #define P32XI_VRES (1 << 14/2) // IRL/2
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490 #define P32XI_VINT (1 << 12/2)
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491 #define P32XI_HINT (1 << 10/2)
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492 #define P32XI_CMD (1 << 8/2)
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493 #define P32XI_PWM (1 << 6/2)
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495 // peripheral reg access
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496 #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
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498 #define DMAC_FIFO_LEN (4*2)
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499 #define PWM_BUFF_LEN 1024 // in one channel samples
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501 #define SH2_DRCBLK_RAM_SHIFT 1
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502 #define SH2_DRCBLK_DA_SHIFT 1
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504 #define SH2_READ_SHIFT 25
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505 #define SH2_WRITE_SHIFT 25
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509 unsigned short regs[0x20];
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510 unsigned short vdp_regs[0x10]; // 0x40
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511 unsigned short sh2_regs[3]; // 0x60
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512 unsigned char pending_fb;
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513 unsigned char dirty_pal;
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514 unsigned int emu_flags;
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515 unsigned char sh2irq_mask[2];
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516 unsigned char sh2irqi[2]; // individual
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517 unsigned int sh2irqs; // common irqs
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518 unsigned short dmac_fifo[DMAC_FIFO_LEN];
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519 unsigned int pad[4];
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520 unsigned int dmac0_fifo_ptr;
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521 unsigned short vdp_fbcr_fake;
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522 unsigned short pad2;
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523 unsigned char comm_dirty_68k;
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524 unsigned char comm_dirty_sh2;
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525 unsigned char pwm_irq_cnt;
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526 unsigned char pad1;
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527 unsigned short pwm_p[2]; // pwm pos in fifo
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528 unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)
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529 unsigned int reserved[6];
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534 unsigned char sdram[0x40000];
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536 unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];
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538 unsigned short dram[2][0x20000/2]; // AKA fb
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540 unsigned char m68k_rom[0x100];
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541 unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE
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544 unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
\r
547 unsigned char b[0x800];
\r
548 unsigned short w[0x800/2];
\r
551 unsigned char b[0x400];
\r
552 unsigned short w[0x400/2];
\r
554 unsigned short pal[0x100];
\r
555 unsigned short pal_native[0x100]; // converted to native (for renderer)
\r
556 signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame
\r
557 signed short pwm_current[2]; // current converted samples
\r
558 unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries
\r
562 extern void (*PicoLoadStateHook)(void);
\r
568 } carthw_state_chunk;
\r
569 extern carthw_state_chunk *carthw_chunks;
\r
570 #define CHUNK_CARTHW 64
\r
573 extern int PicoCartResize(int newsize);
\r
574 extern void Byteswap(void *dst, const void *src, int len);
\r
575 extern void (*PicoCartMemSetup)(void);
\r
576 extern void (*PicoCartUnloadHook)(void);
\r
579 int CM_compareRun(int cyc, int is_sub);
\r
582 PICO_INTERNAL void PicoFrameStart(void);
\r
583 void PicoDrawSync(int to, int blank_last_line);
\r
584 void BackFill(int reg7, int sh);
\r
585 void FinalizeLine555(int sh, int line);
\r
586 extern int (*PicoScanBegin)(unsigned int num);
\r
587 extern int (*PicoScanEnd)(unsigned int num);
\r
588 extern int DrawScanline;
\r
589 #define MAX_LINE_SPRITES 29
\r
590 extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];
\r
591 extern void *DrawLineDestBase;
\r
592 extern int DrawLineDestIncrement;
\r
595 PICO_INTERNAL void PicoFrameFull();
\r
598 void PicoFrameStartMode4(void);
\r
599 void PicoLineMode4(int line);
\r
600 void PicoDoHighPal555M4(void);
\r
601 void PicoDrawSetOutputMode4(pdso_t which);
\r
604 PICO_INTERNAL void PicoMemSetup(void);
\r
605 unsigned int PicoRead8_io(unsigned int a);
\r
606 unsigned int PicoRead16_io(unsigned int a);
\r
607 void PicoWrite8_io(unsigned int a, unsigned int d);
\r
608 void PicoWrite16_io(unsigned int a, unsigned int d);
\r
611 PICO_INTERNAL void PicoMemSetupPico(void);
\r
614 void cdc_init(void);
\r
615 void cdc_reset(void);
\r
616 int cdc_context_save(unsigned char *state);
\r
617 int cdc_context_load(unsigned char *state);
\r
618 int cdc_context_load_old(unsigned char *state);
\r
619 void cdc_dma_update(void);
\r
620 int cdc_decoder_update(unsigned char header[4]);
\r
621 void cdc_reg_w(unsigned char data);
\r
622 unsigned char cdc_reg_r(void);
\r
623 unsigned short cdc_host_r(void);
\r
626 void cdd_reset(void);
\r
627 int cdd_context_save(unsigned char *state);
\r
628 int cdd_context_load(unsigned char *state);
\r
629 int cdd_context_load_old(unsigned char *state);
\r
630 void cdd_read_data(unsigned char *dst);
\r
631 void cdd_read_audio(unsigned int samples);
\r
632 void cdd_update(void);
\r
633 void cdd_process(void);
\r
636 int load_cd_image(const char *cd_img_name, int *type);
\r
639 void gfx_init(void);
\r
640 void gfx_start(unsigned int base);
\r
641 void gfx_update(unsigned int cycles);
\r
642 int gfx_context_save(unsigned char *state);
\r
643 int gfx_context_load(const unsigned char *state);
\r
646 void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc);
\r
649 PICO_INTERNAL void PicoMemSetupCD(void);
\r
650 unsigned int PicoRead8_mcd_io(unsigned int a);
\r
651 unsigned int PicoRead16_mcd_io(unsigned int a);
\r
652 void PicoWrite8_mcd_io(unsigned int a, unsigned int d);
\r
653 void PicoWrite16_mcd_io(unsigned int a, unsigned int d);
\r
654 void pcd_state_loaded_mem(void);
\r
657 extern struct Pico Pico;
\r
658 extern struct PicoSRAM SRam;
\r
659 extern int PicoPadInt[2];
\r
660 extern int emustatus;
\r
661 extern int scanlines_total;
\r
662 extern void (*PicoResetHook)(void);
\r
663 extern void (*PicoLineHook)(void);
\r
664 PICO_INTERNAL int CheckDMA(void);
\r
665 PICO_INTERNAL void PicoDetectRegion(void);
\r
666 PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);
\r
669 #define PCDS_IEN1 (1<<1)
\r
670 #define PCDS_IEN2 (1<<2)
\r
671 #define PCDS_IEN3 (1<<3)
\r
672 #define PCDS_IEN4 (1<<4)
\r
673 #define PCDS_IEN5 (1<<5)
\r
674 #define PCDS_IEN6 (1<<6)
\r
676 PICO_INTERNAL void PicoInitMCD(void);
\r
677 PICO_INTERNAL void PicoExitMCD(void);
\r
678 PICO_INTERNAL void PicoPowerMCD(void);
\r
679 PICO_INTERNAL int PicoResetMCD(void);
\r
680 PICO_INTERNAL void PicoFrameMCD(void);
\r
689 extern unsigned int pcd_event_times[PCD_EVENT_COUNT];
\r
690 void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);
\r
691 void pcd_event_schedule_s68k(enum pcd_event event, int after);
\r
692 void pcd_prepare_frame(void);
\r
693 unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);
\r
694 int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);
\r
695 void pcd_run_cpus(int m68k_cycles);
\r
696 void pcd_soft_reset(void);
\r
697 void pcd_state_loaded(void);
\r
700 void pcd_pcm_sync(unsigned int to);
\r
701 void pcd_pcm_update(int *buffer, int length, int stereo);
\r
702 void pcd_pcm_write(unsigned int a, unsigned int d);
\r
703 unsigned int pcd_pcm_read(unsigned int a);
\r
706 PICO_INTERNAL void PicoInitPico(void);
\r
707 PICO_INTERNAL void PicoReratePico(void);
\r
710 PICO_INTERNAL void PicoPicoPCMUpdate(short *buffer, int length, int stereo);
\r
711 PICO_INTERNAL void PicoPicoPCMReset(void);
\r
712 PICO_INTERNAL void PicoPicoPCMRerate(int xpcm_rate);
\r
715 PICO_INTERNAL void SekInit(void);
\r
716 PICO_INTERNAL int SekReset(void);
\r
717 PICO_INTERNAL void SekState(int *data);
\r
718 PICO_INTERNAL void SekSetRealTAS(int use_real);
\r
719 PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub);
\r
720 PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);
\r
721 void SekStepM68k(void);
\r
722 void SekInitIdleDet(void);
\r
723 void SekFinishIdleDet(void);
\r
724 #if defined(CPU_CMP_R) || defined(CPU_CMP_W)
\r
725 void SekTrace(int is_s68k);
\r
727 #define SekTrace(x)
\r
731 PICO_INTERNAL void SekInitS68k(void);
\r
732 PICO_INTERNAL int SekResetS68k(void);
\r
733 PICO_INTERNAL int SekInterruptS68k(int irq);
\r
734 void SekInterruptClearS68k(int irq);
\r
737 extern short cdda_out_buffer[2*1152];
\r
738 extern int PsndLen_exc_cnt;
\r
739 extern int PsndLen_exc_add;
\r
740 extern int timer_a_next_oflow, timer_a_step; // in z80 cycles
\r
741 extern int timer_b_next_oflow, timer_b_step;
\r
743 void cdda_start_play(int lba_base, int lba_offset, int lb_len);
\r
745 void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new);
\r
746 void ym2612_pack_state(void);
\r
747 void ym2612_unpack_state(void);
\r
749 #define TIMER_NO_OFLOW 0x70000000
\r
750 // tA = 72 * (1024 - NA) / M
\r
751 #define TIMER_A_TICK_ZCYCLES 17203
\r
752 // tB = 1152 * (256 - NA) / M
\r
753 #define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura
\r
755 #define timers_cycle() \
\r
756 if (timer_a_next_oflow > 0 && timer_a_next_oflow < TIMER_NO_OFLOW) \
\r
757 timer_a_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
\r
758 if (timer_b_next_oflow > 0 && timer_b_next_oflow < TIMER_NO_OFLOW) \
\r
759 timer_b_next_oflow -= Pico.m.pal ? 70938*256 : 59659*256; \
\r
760 ym2612_sync_timers(0, ym2612.OPN.ST.mode, ym2612.OPN.ST.mode);
\r
762 #define timers_reset() \
\r
763 timer_a_next_oflow = timer_b_next_oflow = TIMER_NO_OFLOW; \
\r
764 timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \
\r
765 timer_b_step = TIMER_B_TICK_ZCYCLES * 256;
\r
769 extern int line_base_cycles;
\r
770 PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);
\r
771 PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);
\r
772 PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);
\r
773 extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **srcp, unsigned short **limitp);
\r
776 PICO_INTERNAL_ASM void pmemcpy16(unsigned short *dest, unsigned short *src, int count);
\r
777 PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count);
\r
778 PICO_INTERNAL_ASM void memcpy32(int *dest, int *src, int count); // 32bit word count
\r
779 PICO_INTERNAL_ASM void memset32(int *dest, int c, int count);
\r
782 void EEPROM_write8(unsigned int a, unsigned int d);
\r
783 void EEPROM_write16(unsigned int d);
\r
784 unsigned int EEPROM_read(void);
\r
786 // z80 functionality wrappers
\r
787 PICO_INTERNAL void z80_init(void);
\r
788 PICO_INTERNAL void z80_pack(void *data);
\r
789 PICO_INTERNAL int z80_unpack(const void *data);
\r
790 PICO_INTERNAL void z80_reset(void);
\r
791 PICO_INTERNAL void z80_exit(void);
\r
794 PICO_INTERNAL_ASM void wram_2M_to_1M(unsigned char *m);
\r
795 PICO_INTERNAL_ASM void wram_1M_to_2M(unsigned char *m);
\r
798 PICO_INTERNAL void PsndReset(void);
\r
799 PICO_INTERNAL void PsndDoDAC(int line_to);
\r
800 PICO_INTERNAL void PsndClear(void);
\r
801 PICO_INTERNAL void PsndGetSamples(int y);
\r
802 PICO_INTERNAL void PsndGetSamplesMS(void);
\r
803 extern int PsndDacLine;
\r
807 void PicoPowerMS(void);
\r
808 void PicoResetMS(void);
\r
809 void PicoMemSetupMS(void);
\r
810 void PicoStateLoadedMS(void);
\r
811 void PicoFrameMS(void);
\r
812 void PicoFrameDrawOnlyMS(void);
\r
814 #define PicoPowerMS()
\r
815 #define PicoResetMS()
\r
816 #define PicoMemSetupMS()
\r
817 #define PicoStateLoadedMS()
\r
818 #define PicoFrameMS()
\r
819 #define PicoFrameDrawOnlyMS()
\r
824 extern struct Pico32x Pico32x;
\r
827 P32X_EVENT_FILLEND,
\r
831 extern unsigned int p32x_event_times[P32X_EVENT_COUNT];
\r
833 void Pico32xInit(void);
\r
834 void PicoPower32x(void);
\r
835 void PicoReset32x(void);
\r
836 void Pico32xStartup(void);
\r
837 void PicoUnload32x(void);
\r
838 void PicoFrame32x(void);
\r
839 void Pico32xStateLoaded(int is_early);
\r
840 void p32x_sync_sh2s(unsigned int m68k_target);
\r
841 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);
\r
842 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);
\r
843 void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);
\r
844 void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);
\r
845 void p32x_reset_sh2s(void);
\r
846 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);
\r
847 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);
\r
848 void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);
\r
851 struct Pico32xMem *Pico32xMem;
\r
852 unsigned int PicoRead8_32x(unsigned int a);
\r
853 unsigned int PicoRead16_32x(unsigned int a);
\r
854 void PicoWrite8_32x(unsigned int a, unsigned int d);
\r
855 void PicoWrite16_32x(unsigned int a, unsigned int d);
\r
856 void PicoMemSetup32x(void);
\r
857 void Pico32xSwapDRAM(int b);
\r
858 void Pico32xMemStateLoaded(void);
\r
859 void p32x_m68k_poll_event(unsigned int flags);
\r
860 void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);
\r
863 void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);
\r
864 void FinalizeLine32xRGB555(int sh, int line);
\r
865 void PicoDraw32xLayer(int offs, int lines, int mdbg);
\r
866 void PicoDraw32xLayerMdOnly(int offs, int lines);
\r
867 extern int (*PicoScan32xBegin)(unsigned int num);
\r
868 extern int (*PicoScan32xEnd)(unsigned int num);
\r
874 extern int Pico32xDrawMode;
\r
877 unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,
\r
878 unsigned int m68k_cycles);
\r
879 void p32x_pwm_write16(unsigned int a, unsigned int d,
\r
880 SH2 *sh2, unsigned int m68k_cycles);
\r
881 void p32x_pwm_update(int *buf32, int length, int stereo);
\r
882 void p32x_pwm_ctl_changed(void);
\r
883 void p32x_pwm_schedule(unsigned int m68k_now);
\r
884 void p32x_pwm_schedule_sh2(SH2 *sh2);
\r
885 void p32x_pwm_sync_to_sh2(SH2 *sh2);
\r
886 void p32x_pwm_irq_event(unsigned int m68k_now);
\r
887 void p32x_pwm_state_loaded(void);
\r
890 void p32x_dreq0_trigger(void);
\r
891 void p32x_dreq1_trigger(void);
\r
892 void p32x_timers_recalc(void);
\r
893 void p32x_timers_do(unsigned int m68k_slice);
\r
894 void sh2_peripheral_reset(SH2 *sh2);
\r
895 unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
\r
896 unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
\r
897 unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
\r
898 void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);
\r
899 void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);
\r
900 void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);
\r
903 #define Pico32xInit()
\r
904 #define PicoPower32x()
\r
905 #define PicoReset32x()
\r
906 #define PicoFrame32x()
\r
907 #define PicoUnload32x()
\r
908 #define Pico32xStateLoaded()
\r
909 #define FinalizeLine32xRGB555 NULL
\r
910 #define p32x_pwm_update(...)
\r
911 #define p32x_timers_recalc()
\r
914 /* avoid dependency on newer glibc */
\r
915 static INLINE int isspace_(int c)
\r
917 return (0x09 <= c && c <= 0x0d) || c == ' ';
\r
921 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
\r
924 // emulation event logging
\r
926 # ifdef __x86_64__ // HACK
\r
927 # define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)
\r
929 # define EL_LOGMASK (EL_STATUS)
\r
933 #define EL_HVCNT 0x00000001 /* hv counter reads */
\r
934 #define EL_SR 0x00000002 /* SR reads */
\r
935 #define EL_INTS 0x00000004 /* ints and acks */
\r
936 #define EL_YMTIMER 0x00000008 /* ym2612 timer stuff */
\r
937 #define EL_INTSW 0x00000010 /* log irq switching on/off */
\r
938 #define EL_ASVDP 0x00000020 /* VDP accesses during active scan */
\r
939 #define EL_VDPDMA 0x00000040 /* VDP DMA transfers and their timing */
\r
940 #define EL_BUSREQ 0x00000080 /* z80 busreq r/w or reset w */
\r
941 #define EL_Z80BNK 0x00000100 /* z80 i/o through bank area */
\r
942 #define EL_SRAMIO 0x00000200 /* sram i/o */
\r
943 #define EL_EEPROM 0x00000400 /* eeprom debug */
\r
944 #define EL_UIO 0x00000800 /* unmapped i/o */
\r
945 #define EL_IO 0x00001000 /* all i/o */
\r
946 #define EL_CDPOLL 0x00002000 /* MCD: log poll detection */
\r
947 #define EL_SVP 0x00004000 /* SVP stuff */
\r
948 #define EL_PICOHW 0x00008000 /* Pico stuff */
\r
949 #define EL_IDLE 0x00010000 /* idle loop det. */
\r
950 #define EL_CDREGS 0x00020000 /* MCD: register access */
\r
951 #define EL_CDREG3 0x00040000 /* MCD: register 3 only */
\r
952 #define EL_32X 0x00080000
\r
953 #define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */
\r
954 #define EL_32XP 0x00200000 /* 32X peripherals */
\r
955 #define EL_CD 0x00400000 /* MCD */
\r
957 #define EL_STATUS 0x40000000 /* status messages */
\r
958 #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
\r
961 #define elprintf(w,f,...) \
\r
963 if ((w) & EL_LOGMASK) \
\r
964 lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \
\r
966 #elif defined(_MSC_VER)
\r
969 #define elprintf(w,f,...)
\r
974 #include <platform/linux/pprof.h>
\r
976 #define pprof_init()
\r
977 #define pprof_finish()
\r
978 #define pprof_start(x)
\r
979 #define pprof_end(...)
\r
980 #define pprof_end_sub(...)
\r
1002 void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);
\r
1003 void pevt_dump(void);
\r
1005 #define pevt_log_m68k(e) \
\r
1006 pevt_log(SekCyclesDone(), EVT_M68K, e)
\r
1007 #define pevt_log_m68k_o(e) \
\r
1008 pevt_log(SekCyclesDone(), EVT_M68K, e)
\r
1009 #define pevt_log_sh2(sh2, e) \
\r
1010 pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)
\r
1011 #define pevt_log_sh2_o(sh2, e) \
\r
1012 pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)
\r
1014 #define pevt_log(c, e)
\r
1015 #define pevt_log_m68k(e)
\r
1016 #define pevt_log_m68k_o(e)
\r
1017 #define pevt_log_sh2(sh2, e)
\r
1018 #define pevt_log_sh2_o(sh2, e)
\r
1019 #define pevt_dump()
\r
1026 #define cdprintf(x...)
\r
1029 #if defined(__GNUC__) && defined(__i386__)
\r
1030 #define REGPARM(x) __attribute__((regparm(x)))
\r
1032 #define REGPARM(x)
\r
1036 #define NOINLINE __attribute__((noinline))
\r
1041 #ifdef __cplusplus
\r
1042 } // End of extern "C"
\r
1045 #endif // PICO_INTERNAL_INCLUDED
\r