5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
13 uptr z80_read_map [0x10000 >> Z80_MEM_SHIFT];
14 uptr z80_write_map[0x10000 >> Z80_MEM_SHIFT];
17 // this causes trouble in some cases, like doukutsu putting sp in bank area
18 // no perf difference for most, upto 1-2% for some others
23 static void drz80_load_pcsp(u32 pc, u32 sp)
25 drZ80.Z80PC_BASE = z80_read_map[pc >> Z80_MEM_SHIFT];
26 if (drZ80.Z80PC_BASE & (1<<31)) {
27 elprintf(EL_STATUS|EL_ANOMALY, "load_pcsp: bad PC: %04x", pc);
28 drZ80.Z80PC_BASE = drZ80.Z80PC = z80_read_map[0];
30 drZ80.Z80PC_BASE <<= 1;
31 drZ80.Z80PC = drZ80.Z80PC_BASE + pc;
35 drZ80.Z80SP_BASE = z80_read_map[sp >> Z80_MEM_SHIFT];
36 if (drZ80.Z80SP_BASE & (1<<31)) {
37 elprintf(EL_STATUS|EL_ANOMALY, "load_pcsp: bad SP: %04x", sp);
38 drZ80.Z80SP_BASE = z80_read_map[0];
39 drZ80.Z80SP = drZ80.Z80SP_BASE + (1 << Z80_MEM_SHIFT);
41 drZ80.Z80SP_BASE <<= 1;
42 drZ80.Z80SP = drZ80.Z80SP_BASE + sp;
47 // called only if internal xmap rebase fails
48 static unsigned int dz80_rebase_pc(unsigned short pc)
50 elprintf(EL_STATUS|EL_ANOMALY, "dz80_rebase_pc: fail on %04x", pc);
51 drZ80.Z80PC_BASE = z80_read_map[0] << 1;
52 return drZ80.Z80PC_BASE;
56 static u32 drz80_sp_base;
58 static unsigned int dz80_rebase_sp(unsigned short sp)
60 elprintf(EL_STATUS|EL_ANOMALY, "dz80_rebase_sp: fail on %04x", sp);
61 drZ80.Z80SP_BASE = z80_read_map[drz80_sp_base >> Z80_MEM_SHIFT] << 1;
62 return drZ80.Z80SP_BASE + (1 << Z80_MEM_SHIFT) - 0x100;
65 #define dz80_rebase_sp NULL
73 memset(&drZ80, 0, sizeof(drZ80));
74 drZ80.z80_rebasePC = dz80_rebase_pc;
75 drZ80.z80_rebaseSP = dz80_rebase_sp;
76 drZ80.z80_read8 = (void *)z80_read_map;
77 drZ80.z80_read16 = NULL;
78 drZ80.z80_write8 = (void *)z80_write_map;
79 drZ80.z80_write16 = NULL;
80 drZ80.z80_irq_callback = NULL;
83 memset(&CZ80, 0, sizeof(CZ80));
85 Cz80_Set_ReadB(&CZ80, NULL); // unused (hacked in)
86 Cz80_Set_WriteB(&CZ80, NULL);
96 drZ80.z80irqvector = 0xff0000; // RST 38h
97 drZ80.Z80PC_BASE = drZ80.Z80PC = z80_read_map[0] << 1;
98 // others not changed, undefined on cold boot
100 drZ80.Z80F = (1<<2); // set ZFlag
101 drZ80.Z80F2 = (1<<2); // set ZFlag
102 drZ80.Z80IX = 0xFFFF << 16;
103 drZ80.Z80IY = 0xFFFF << 16;
106 // drZ80 is locked in single bank
107 drz80_sp_base = (PicoAHW & PAHW_SMS) ? 0xc000 : 0x0000;
108 drZ80.Z80SP_BASE = z80_read_map[drz80_sp_base >> Z80_MEM_SHIFT] << 1;
110 if (PicoAHW & PAHW_SMS)
111 drZ80.Z80SP = drZ80.Z80SP_BASE + 0xdff0; // simulate BIOS
112 // XXX: since we use direct SP pointer, it might make sense to force it to RAM,
113 // but we'll rely on built-in stack protection for now
117 if (PicoAHW & PAHW_SMS)
118 Cz80_Set_Reg(&CZ80, CZ80_SP, 0xdff0);
132 struct z80sr_main m; // main regs
133 struct z80sr_main a; // alt (') regs
142 u8 irq_pending; // irq line level, 1 if active
143 u8 irq_vector[3]; // up to 3 byte vector for irq mode0 handling
147 void z80_pack(void *data)
149 struct z80_state *s = data;
150 memset(data, 0, Z80_STATE_SIZE);
151 strcpy(s->magic, "Z80");
152 #if defined(_USE_DRZ80)
153 #define DRR8(n) (drZ80.Z80##n >> 24)
154 #define DRR16(n) (drZ80.Z80##n >> 16)
155 #define DRR16H(n) (drZ80.Z80##n >> 24)
156 #define DRR16L(n) ((drZ80.Z80##n >> 16) & 0xff)
157 s->m.a = DRR8(A); s->m.f = drZ80.Z80F;
158 s->m.b = DRR16H(BC); s->m.c = DRR16L(BC);
159 s->m.d = DRR16H(DE); s->m.e = DRR16L(DE);
160 s->m.h = DRR16H(HL); s->m.l = DRR16L(HL);
161 s->a.a = DRR8(A2); s->a.f = drZ80.Z80F2;
162 s->a.b = DRR16H(BC2); s->a.c = DRR16L(BC2);
163 s->a.d = DRR16H(DE2); s->a.e = DRR16L(DE2);
164 s->a.h = DRR16H(HL2); s->a.l = DRR16L(HL2);
165 s->i = DRR8(I); s->r = drZ80.spare;
166 s->ix = DRR16(IX); s->iy = DRR16(IY);
167 s->sp = drZ80.Z80SP - drZ80.Z80SP_BASE;
168 s->pc = drZ80.Z80PC - drZ80.Z80PC_BASE;
169 s->halted = !!(drZ80.Z80IF & 4);
170 s->iff1 = !!(drZ80.Z80IF & 1);
171 s->iff2 = !!(drZ80.Z80IF & 2);
173 s->irq_pending = !!drZ80.Z80_IRQ;
174 s->irq_vector[0] = drZ80.z80irqvector >> 16;
175 s->irq_vector[1] = drZ80.z80irqvector >> 8;
176 s->irq_vector[2] = drZ80.z80irqvector;
177 #elif defined(_USE_CZ80)
179 const cz80_struc *CPU = &CZ80;
180 s->m.a = zA; s->m.f = zF;
181 s->m.b = zB; s->m.c = zC;
182 s->m.d = zD; s->m.e = zE;
183 s->m.h = zH; s->m.l = zL;
184 s->a.a = zA2; s->a.f = zF2;
185 s->a.b = CZ80.BC2.B.H; s->a.c = CZ80.BC2.B.L;
186 s->a.d = CZ80.DE2.B.H; s->a.e = CZ80.DE2.B.L;
187 s->a.h = CZ80.HL2.B.H; s->a.l = CZ80.HL2.B.L;
188 s->i = zI; s->r = zR;
189 s->ix = zIX; s->iy = zIY;
190 s->sp = Cz80_Get_Reg(&CZ80, CZ80_SP);
191 s->pc = Cz80_Get_Reg(&CZ80, CZ80_PC);
192 s->halted = !!Cz80_Get_Reg(&CZ80, CZ80_HALT);
196 s->irq_pending = (Cz80_Get_Reg(&CZ80, CZ80_IRQ) == HOLD_LINE);
197 s->irq_vector[0] = 0xff;
202 int z80_unpack(const void *data)
204 const struct z80_state *s = data;
205 if (strcmp(s->magic, "Z80") != 0) {
206 elprintf(EL_STATUS, "legacy z80 state - ignored");
210 #if defined(_USE_DRZ80)
211 #define DRW8(n, v) drZ80.Z80##n = (u32)(v) << 24
212 #define DRW16(n, v) drZ80.Z80##n = (u32)(v) << 16
213 #define DRW16HL(n, h, l) drZ80.Z80##n = ((u32)(h) << 24) | ((u32)(l) << 16)
214 DRW8(A, s->m.a); drZ80.Z80F = s->m.f;
215 DRW16HL(BC, s->m.b, s->m.c);
216 DRW16HL(DE, s->m.d, s->m.e);
217 DRW16HL(HL, s->m.h, s->m.l);
218 DRW8(A2, s->a.a); drZ80.Z80F2 = s->a.f;
219 DRW16HL(BC2, s->a.b, s->a.c);
220 DRW16HL(DE2, s->a.d, s->a.e);
221 DRW16HL(HL2, s->a.h, s->a.l);
222 DRW8(I, s->i); drZ80.spare = s->r;
223 DRW16(IX, s->ix); DRW16(IY, s->iy);
224 drz80_load_pcsp(s->pc, s->sp);
226 if (s->halted) drZ80.Z80IF |= 4;
227 if (s->iff1) drZ80.Z80IF |= 1;
228 if (s->iff2) drZ80.Z80IF |= 2;
230 drZ80.Z80_IRQ = s->irq_pending;
231 drZ80.z80irqvector = ((u32)s->irq_vector[0] << 16) |
232 ((u32)s->irq_vector[1] << 8) | s->irq_vector[2];
234 #elif defined(_USE_CZ80)
236 cz80_struc *CPU = &CZ80;
237 zA = s->m.a; zF = s->m.f;
238 zB = s->m.b; zC = s->m.c;
239 zD = s->m.d; zE = s->m.e;
240 zH = s->m.h; zL = s->m.l;
241 zA2 = s->a.a; zF2 = s->a.f;
242 CZ80.BC2.B.H = s->a.b; CZ80.BC2.B.L = s->a.c;
243 CZ80.DE2.B.H = s->a.d; CZ80.DE2.B.L = s->a.e;
244 CZ80.HL2.B.H = s->a.h; CZ80.HL2.B.L = s->a.l;
245 zI = s->i; zR = s->r;
246 zIX = s->ix; zIY = s->iy;
247 Cz80_Set_Reg(&CZ80, CZ80_SP, s->sp);
248 Cz80_Set_Reg(&CZ80, CZ80_PC, s->pc);
249 Cz80_Set_Reg(&CZ80, CZ80_HALT, s->halted);
250 Cz80_Set_Reg(&CZ80, CZ80_IFF1, s->iff1);
251 Cz80_Set_Reg(&CZ80, CZ80_IFF2, s->iff2);
253 Cz80_Set_Reg(&CZ80, CZ80_IRQ, s->irq_pending ? HOLD_LINE : CLEAR_LINE);
265 void z80_debug(char *dstr)
267 #if defined(_USE_DRZ80)
268 sprintf(dstr, "Z80 state: PC: %04x SP: %04x\n", drZ80.Z80PC-drZ80.Z80PC_BASE, drZ80.Z80SP-drZ80.Z80SP_BASE);
269 #elif defined(_USE_CZ80)
270 sprintf(dstr, "Z80 state: PC: %04x SP: %04x\n", (unsigned int)(CZ80.PC - CZ80.BasePC), CZ80.SP.W);
274 // vim:ts=2:sw=2:expandtab