4 .global vidCpy8to16 @ void *dest, void *src, short *pal, int lines|(flags<<16),
5 @ flags=is32col[0], no_even_lines[1], no_odd_lines[2]
14 orr r3, r3, r3, lsl #8
15 orreq r3, r3, #(320/8-1)<<24 @ 40 col mode
16 orrne r3, r3, #(256/8-1)<<24 @ 32 col mode
34 and r4, lr, r12,lsl #1
36 and r5, lr, r12,lsr #7
38 and r6, lr, r12,lsr #15
40 orr r4, r4, r5, lsl #16
42 and r5, lr, r12,lsr #23
44 and r8, lr, r7, lsl #1
46 orr r5, r6, r5, lsl #16
48 and r6, lr, r7, lsr #7
50 and r12,lr, r7, lsr #15
52 and r7, lr, r7, lsr #23
54 orr r8, r8, r6, lsl #16
57 orr r12,r12, r7, lsl #16
59 stmia r0!, {r4,r5,r8,r12}
63 add r1, r1, #336 @ skip a line and 1 col
64 addne r1, r1, #64 @ skip more for 32col mode
65 add r0, r0, #(320+2)*2
67 addeq r3, r3, #(320/8)<<24
68 addne r3, r3, #(256/8)<<24
75 ldmnefd sp!, {r4-r8,pc}
78 orr r3, r3, r4, lsr #8
97 and r6, lr, r12, lsl #1
99 and r5, lr, r12, lsr #7
101 orr r4, r8, r6, lsl #16
103 and r6, lr, r12, lsr #15
105 and r8, lr, r12, lsr #23
107 orr r5, r5, r6, lsl #16
109 and r6, lr, r7, lsl #1
111 and r12,lr, r7, lsr #7
113 orr r6, r8, r6, lsl #16
115 and r8, lr, r7, lsr #15
119 and r7, lr, r7, lsr #23
120 orr r12,r12,r8, lsl #16
124 stmia r0!, {r4,r5,r6,r12}
131 add r1, r1, #336 @ skip a line and 1 col
132 addne r1, r1, #64 @ skip more for 32col mode
133 add r0, r0, #(320+2)*2
135 addeq r3, r3, #(320/8)<<24
136 addne r3, r3, #(256/8)<<24
141 ldmfd sp!, {r4-r8,lr}