4 .global vidCpy8to16_40 @ void *dest, void *src, short *pal, int lines
10 orr r3, r3, r3, lsl #8
12 orr r3, r3, #(320/8-1)<<24
19 and r4, lr, r12, lsl #1
21 and r5, lr, r12, lsr #7
23 and r6, lr, r12, lsr #15
25 orr r4, r4, r5, lsl #16
27 and r5, lr, r12, lsr #23
29 and r8, lr, r7, lsl #1
31 orr r5, r6, r5, lsl #16
33 and r6, lr, r7, lsr #7
35 and r12,lr, r7, lsr #15
37 and r9, lr, r7, lsr #23
39 orr r8, r8, r6, lsl #16
42 orr r12,r12, r9, lsl #16
44 stmia r0!, {r4,r5,r8,r12}
47 add r1, r1, #336 @ skip a line and 1 col
48 add r0, r0, #320*2+2*2
49 add r3, r3, #(320/8)<<24
55 orr r3, r3, r4, lsr #8
74 and r4, lr, r12, lsl #1
76 and r5, lr, r12, lsr #7
79 and r6, lr, r12, lsr #15
82 and r4, lr, r12, lsr #23
84 orr r5, r5, r6, lsl #16
86 and r8, lr, r7, lsl #1
89 and r6, lr, r7, lsr #7
91 orr r8, r4, r8, lsl #16
93 and r12,lr, r7, lsr #15
96 and r4, lr, r7, lsr #23
98 orr r12,r6, r12,lsl #16
101 stmia r0!, {r5,r8,r12}
103 bpl vcloop_40_unaligned
105 add r1, r1, #336 @ skip a line and 1 col
106 add r0, r0, #320*2+2*2
107 add r3, r3, #(320/8)<<24
110 bne vcloop_40_unaligned
112 ldmfd sp!, {r4-r9,lr}