platform ps2, handle audio similar to psp
[picodrive.git] / sh2 / mame / sh2pico.c
1 #include "../sh2.h"
2
3 #ifdef DRC_CMP
4 #include "../compiler.c"
5 #define BUSY_LOOP_HACKS 0
6 #else
7 #define BUSY_LOOP_HACKS 1
8 #endif
9
10 // MAME types
11 #ifndef INT8
12 typedef signed char  INT8;
13 typedef signed short INT16;
14 typedef signed int   INT32;
15 typedef unsigned int   UINT32;
16 typedef unsigned short UINT16;
17 typedef unsigned char  UINT8;
18 #endif
19
20 #ifdef DRC_SH2
21
22 // this nasty conversion is needed for drc-expecting memhandlers
23 #define MAKE_READFUNC(name, cname) \
24 static __inline unsigned int name(SH2 *sh2, unsigned int a) \
25 { \
26         unsigned int ret; \
27         sh2->sr |= sh2->icount << 12; \
28         ret = cname(a, sh2); \
29         sh2->icount = (signed int)sh2->sr >> 12; \
30         sh2->sr &= 0x3f3; \
31         return ret; \
32 }
33
34 #define MAKE_WRITEFUNC(name, cname) \
35 static __inline void name(SH2 *sh2, unsigned int a, unsigned int d) \
36 { \
37         sh2->sr |= sh2->icount << 12; \
38         cname(a, d, sh2); \
39         sh2->icount = (signed int)sh2->sr >> 12; \
40         sh2->sr &= 0x3f3; \
41 }
42
43 MAKE_READFUNC(RB, p32x_sh2_read8)
44 MAKE_READFUNC(RW, p32x_sh2_read16)
45 MAKE_READFUNC(RL, p32x_sh2_read32)
46 MAKE_WRITEFUNC(WB, p32x_sh2_write8)
47 MAKE_WRITEFUNC(WW, p32x_sh2_write16)
48 MAKE_WRITEFUNC(WL, p32x_sh2_write32)
49
50 #else
51
52 #define RB(sh2, a) p32x_sh2_read8(a, sh2)
53 #define RW(sh2, a) p32x_sh2_read16(a, sh2)
54 #define RL(sh2, a) p32x_sh2_read32(a, sh2)
55 #define WB(sh2, a, d) p32x_sh2_write8(a, d, sh2)
56 #define WW(sh2, a, d) p32x_sh2_write16(a, d, sh2)
57 #define WL(sh2, a, d) p32x_sh2_write32(a, d, sh2)
58
59 #endif
60
61 // some stuff from sh2comn.h
62 #define T       0x00000001
63 #define S       0x00000002
64 #define I       0x000000f0
65 #define Q       0x00000100
66 #define M       0x00000200
67
68 #define AM      0xc7ffffff
69
70 #define FLAGS   (M|Q|I|S|T)
71
72 #define Rn      ((opcode>>8)&15)
73 #define Rm      ((opcode>>4)&15)
74
75 #define sh2_state SH2
76
77 extern void lprintf(const char *fmt, ...);
78 #define logerror lprintf
79
80 #ifdef SH2_STATS
81 static SH2 sh2_stats;
82 static unsigned int op_refs[0x10000];
83 # define LRN  1
84 # define LRM  2
85 # define LRNM (LRN|LRM)
86 # define rlog(rnm) {   \
87   int op = opcode;     \
88   if ((rnm) & LRN) {   \
89     op &= ~0x0f00;     \
90     sh2_stats.r[Rn]++; \
91   }                    \
92   if ((rnm) & LRM) {   \
93     op &= ~0x00f0;     \
94     sh2_stats.r[Rm]++; \
95   }                    \
96   op_refs[op]++;       \
97 }
98 # define rlog1(x) sh2_stats.r[x]++
99 # define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
100 #else
101 # define rlog(x)
102 # define rlog1(...)
103 # define rlog2(...)
104 #endif
105
106 #include "sh2.c"
107
108 #ifndef DRC_CMP
109
110 int sh2_execute_interpreter(SH2 *sh2, int cycles)
111 {
112         UINT32 opcode;
113
114         sh2->icount = cycles;
115
116         if (sh2->icount <= 0)
117                 goto out;
118
119         do
120         {
121                 if (sh2->delay)
122                 {
123                         sh2->ppc = sh2->delay;
124                         opcode = RW(sh2, sh2->delay);
125
126                         // TODO: more branch types
127                         if ((opcode >> 13) == 5) { // BRA/BSR
128                                 sh2->r[15] -= 4;
129                                 WL(sh2, sh2->r[15], sh2->sr);
130                                 sh2->r[15] -= 4;
131                                 WL(sh2, sh2->r[15], sh2->pc);
132                                 sh2->pc = RL(sh2, sh2->vbr + 6 * 4);
133                                 sh2->icount -= 5;
134                                 opcode = 9; // NOP
135                         }
136
137                         sh2->pc -= 2;
138                 }
139                 else
140                 {
141                         sh2->ppc = sh2->pc;
142                         opcode = RW(sh2, sh2->pc);
143                 }
144
145                 sh2->delay = 0;
146                 sh2->pc += 2;
147
148                 switch (opcode & ( 15 << 12))
149                 {
150                 case  0<<12: op0000(sh2, opcode); break;
151                 case  1<<12: op0001(sh2, opcode); break;
152                 case  2<<12: op0010(sh2, opcode); break;
153                 case  3<<12: op0011(sh2, opcode); break;
154                 case  4<<12: op0100(sh2, opcode); break;
155                 case  5<<12: op0101(sh2, opcode); break;
156                 case  6<<12: op0110(sh2, opcode); break;
157                 case  7<<12: op0111(sh2, opcode); break;
158                 case  8<<12: op1000(sh2, opcode); break;
159                 case  9<<12: op1001(sh2, opcode); break;
160                 case 10<<12: op1010(sh2, opcode); break;
161                 case 11<<12: op1011(sh2, opcode); break;
162                 case 12<<12: op1100(sh2, opcode); break;
163                 case 13<<12: op1101(sh2, opcode); break;
164                 case 14<<12: op1110(sh2, opcode); break;
165                 default: op1111(sh2, opcode); break;
166                 }
167
168                 sh2->icount--;
169
170                 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
171                 {
172                         int level = sh2->pending_level;
173                         int vector = sh2->irq_callback(sh2, level);
174                         sh2_do_irq(sh2, level, vector);
175                         sh2->test_irq = 0;
176                 }
177
178         }
179         while (sh2->icount > 0 || sh2->delay);  /* can't interrupt before delay */
180
181 out:
182         return sh2->icount;
183 }
184
185 #else // if DRC_CMP
186
187 int sh2_execute_interpreter(SH2 *sh2, int cycles)
188 {
189         static unsigned int base_pc_[2] = { 0, 0 };
190         static unsigned int end_pc_[2] = { 0, 0 };
191         static unsigned char op_flags_[2][BLOCK_INSN_LIMIT];
192         unsigned int *base_pc = &base_pc_[sh2->is_slave];
193         unsigned int *end_pc = &end_pc_[sh2->is_slave];
194         unsigned char *op_flags = op_flags_[sh2->is_slave];
195         unsigned int pc_expect;
196         UINT32 opcode;
197
198         sh2->icount = sh2->cycles_timeslice = cycles;
199
200         if (sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
201         {
202                 int level = sh2->pending_level;
203                 int vector = sh2->irq_callback(sh2, level);
204                 sh2_do_irq(sh2, level, vector);
205         }
206         pc_expect = sh2->pc;
207
208         if (sh2->icount <= 0)
209                 goto out;
210
211         do
212         {
213                 if (!sh2->delay) {
214                         if (sh2->pc < *base_pc || sh2->pc >= *end_pc) {
215                                 *base_pc = sh2->pc;
216                                 scan_block(*base_pc, sh2->is_slave,
217                                         op_flags, end_pc, NULL);
218                         }
219                         if ((op_flags[(sh2->pc - *base_pc) / 2]
220                                 & OF_BTARGET) || sh2->pc == *base_pc
221                                 || pc_expect != sh2->pc) // branched
222                         {
223                                 pc_expect = sh2->pc;
224                                 if (sh2->icount < 0)
225                                         break;
226                         }
227
228                         do_sh2_trace(sh2, sh2->icount);
229                 }
230                 pc_expect += 2;
231
232                 if (sh2->delay)
233                 {
234                         sh2->ppc = sh2->delay;
235                         opcode = RW(sh2, sh2->delay);
236                         sh2->pc -= 2;
237                 }
238                 else
239                 {
240                         sh2->ppc = sh2->pc;
241                         opcode = RW(sh2, sh2->pc);
242                 }
243
244                 sh2->delay = 0;
245                 sh2->pc += 2;
246
247                 switch (opcode & ( 15 << 12))
248                 {
249                 case  0<<12: op0000(sh2, opcode); break;
250                 case  1<<12: op0001(sh2, opcode); break;
251                 case  2<<12: op0010(sh2, opcode); break;
252                 case  3<<12: op0011(sh2, opcode); break;
253                 case  4<<12: op0100(sh2, opcode); break;
254                 case  5<<12: op0101(sh2, opcode); break;
255                 case  6<<12: op0110(sh2, opcode); break;
256                 case  7<<12: op0111(sh2, opcode); break;
257                 case  8<<12: op1000(sh2, opcode); break;
258                 case  9<<12: op1001(sh2, opcode); break;
259                 case 10<<12: op1010(sh2, opcode); break;
260                 case 11<<12: op1011(sh2, opcode); break;
261                 case 12<<12: op1100(sh2, opcode); break;
262                 case 13<<12: op1101(sh2, opcode); break;
263                 case 14<<12: op1110(sh2, opcode); break;
264                 default: op1111(sh2, opcode); break;
265                 }
266
267                 sh2->icount--;
268
269                 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
270                 {
271                         int level = sh2->pending_level;
272                         int vector = sh2->irq_callback(sh2, level);
273                         sh2_do_irq(sh2, level, vector);
274                         sh2->test_irq = 0;
275                 }
276
277         }
278         while (1);
279
280 out:
281         return sh2->icount;
282 }
283
284 #endif // DRC_CMP
285
286 #ifdef SH2_STATS
287 #include <stdio.h>
288 #include <string.h>
289 #include "sh2dasm.h"
290
291 void sh2_dump_stats(void)
292 {
293         static const char *rnames[] = {
294                 "R0", "R1", "R2",  "R3",  "R4",  "R5",  "R6",  "R7",
295                 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
296                 "PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
297         };
298         long long total;
299         char buff[64];
300         int u, i;
301
302         // dump reg usage
303         total = 0;
304         for (i = 0; i < 24; i++)
305                 total += sh2_stats.r[i];
306
307         for (i = 0; i < 24; i++) {
308                 if (i == 16 || i == 17 || i == 19)
309                         continue;
310                 printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
311                         rnames[i], sh2_stats.r[i]);
312         }
313
314         memset(&sh2_stats, 0, sizeof(sh2_stats));
315
316         // dump ops
317         printf("\n");
318         total = 0;
319         for (i = 0; i < 0x10000; i++)
320                 total += op_refs[i];
321
322         for (u = 0; u < 16; u++) {
323                 int max = 0, op = 0;
324                 for (i = 0; i < 0x10000; i++) {
325                         if (op_refs[i] > max) {
326                                 max = op_refs[i];
327                                 op = i;
328                         }
329                 }
330                 DasmSH2(buff, 0, op);
331                 printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
332                         op_refs[op], buff);
333                 op_refs[op] = 0;
334         }
335         memset(op_refs, 0, sizeof(op_refs));
336 }
337 #endif
338