1 /***************************************************************************\
3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
38 \***************************************************************************/
42 #define RIVA_SW_VERSION 0x00010003
45 * Typedefs to force certain sized values.
54 #define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
55 #define NV_RD08(p,i) (((U008 *)(p))[i])
56 #define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
57 #define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
58 #define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
59 #define NV_RD32(p,i) (((U032 *)(p))[(i)/4])
60 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
61 #define VGA_RD08(p,i) NV_RD08(p,i)
64 * Define supported architectures.
66 #define NV_ARCH_03 0x03
67 #define NV_ARCH_04 0x04
68 #define NV_ARCH_10 0x10
69 /***************************************************************************\
73 \***************************************************************************/
76 * Raster OPeration. Windows style ROP3.
78 typedef volatile struct
83 U032 reserved01[0x0BB];
87 * 8X8 Monochrome pattern.
89 typedef volatile struct
94 U032 reserved01[0x0BD];
96 U032 reserved03[0x001];
102 * Scissor clip rectangle.
104 typedef volatile struct
109 U032 reserved01[0x0BB];
114 * 2D filled rectangle.
116 typedef volatile struct
121 U032 reserved01[0x0BC];
123 U032 reserved03[0x03E];
128 * 2D screen-screen BLT.
130 typedef volatile struct
135 U032 reserved01[0x0BB];
143 typedef volatile struct
148 U032 reserved01[0x0BC];
152 U032 reserved02[0x03C];
156 * Filled rectangle combined with monochrome expand. Useful for glyphs.
158 typedef volatile struct
163 U032 reserved01[0x0BB];
164 U032 reserved03[(0x040)-1];
170 } UnclippedRectangle[64];
171 U032 reserved04[(0x080)-3];
182 } ClippedRectangle[64];
183 U032 reserved05[(0x080)-5];
192 U032 MonochromeData1C;
193 U032 reserved06[(0x080)+121];
201 U032 WidthHeightOutD;
203 U032 MonochromeData1D;
204 U032 reserved07[(0x080)+120];
213 U032 WidthHeightOutE;
215 U032 MonochromeData01E;
218 * 3D textured, Z buffered triangle.
220 typedef volatile struct
225 U032 reserved01[0x0BC];
230 /* This is a problem on LynxOS */
236 U032 reserved02[0x339];
245 } RivaTexturedTriangle03;
246 typedef volatile struct
251 U032 reserved01[0x0BB];
257 /* This is a problem on LynxOS */
263 U032 reserved02[0x39];
276 } RivaTexturedTriangle05;
280 typedef volatile struct
285 U032 reserved01[0x0BC];
286 U032 Color; /* source color 0304-0307*/
287 U032 Reserved02[0x03e];
288 struct { /* start aliased methods in array 0400- */
289 U032 point0; /* y_x S16_S16 in pixels 0- 3*/
290 U032 point1; /* y_x S16_S16 in pixels 4- 7*/
291 } Lin[16]; /* end of aliased methods in array -047f*/
292 struct { /* start aliased methods in array 0480- */
293 U032 point0X; /* in pixels, 0 at left 0- 3*/
294 U032 point0Y; /* in pixels, 0 at top 4- 7*/
295 U032 point1X; /* in pixels, 0 at left 8- b*/
296 U032 point1Y; /* in pixels, 0 at top c- f*/
297 } Lin32[8]; /* end of aliased methods in array -04ff*/
298 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
299 struct { /* start aliased methods in array 0580- */
300 U032 x; /* in pixels, 0 at left 0- 3*/
301 U032 y; /* in pixels, 0 at top 4- 7*/
302 } PolyLin32[16]; /* end of aliased methods in array -05ff*/
303 struct { /* start aliased methods in array 0600- */
304 U032 color; /* source color 0- 3*/
305 U032 point; /* y_x S16_S16 in pixels 4- 7*/
306 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/
311 typedef volatile struct
316 U032 reserved01[0x0BE];
319 typedef volatile struct
324 U032 reserved01[0x0BD];
326 U032 RenderBufferOffset;
330 /***************************************************************************\
332 * Virtualized RIVA H/W interface. *
334 \***************************************************************************/
336 struct _riva_hw_inst;
337 struct _riva_hw_state;
339 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
341 typedef struct _riva_hw_inst
344 * Chip specific settings.
349 U032 RamAmountKBytes;
350 U032 MaxVClockFreqKHz;
351 U032 RamBandwidthKBytesPerSec;
358 * Non-FIFO registers.
360 volatile U032 *PCRTC;
361 volatile U032 *PRAMDAC;
363 volatile U032 *PFIFO;
364 volatile U032 *PGRAPH;
365 volatile U032 *PEXTDEV;
366 volatile U032 *PTIMER;
368 volatile U032 *PRAMIN;
370 volatile U032 *CURSOR;
371 volatile U032 *CURSORPOS;
372 volatile U032 *VBLANKENABLE;
373 volatile U032 *VBLANK;
378 * Common chip functions.
380 int (*Busy)(struct _riva_hw_inst *);
381 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int);
382 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
383 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
384 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
385 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
386 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
387 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
388 void (*LockUnlock)(struct _riva_hw_inst *, int);
390 * Current extended mode settings.
392 struct _riva_hw_state *CurrentState;
403 RivaTexturedTriangle03 *Tri03;
404 RivaTexturedTriangle05 *Tri05;
407 * Extended mode state information.
409 typedef struct _riva_hw_state
439 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
442 #define RIVA_FIFO_FREE(hwptr,cnt) \
444 while (FifoFreeCount < (cnt)) \
445 FifoFreeCount = hwptr->FifoFree >> 2; \
446 FifoFreeCount -= (cnt); \
448 #endif /* __RIVA_HW_H__ */