9 .global flush_inval_caches
13 @ translation cache buffer
16 .size tcache, TCACHE_SIZE
26 mov r2, #0x0 @ must be 0
31 @ SSP_GR0, SSP_X, SSP_Y, SSP_A,
32 @ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
33 @ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
34 @ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
39 @ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
53 ldmia r2, {r3,r4,r5,r6,r8}
56 orr r4, r3, r4, lsr #16 @ XXYY
59 mov r8, r8, lsl #13 @ sss0 *
64 orrne r8, r8, #0x4 @ sss0 * NZ..
65 orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
67 ldr r8, [r7, #0x440] @ r0-r2
68 ldr r9, [r7, #0x444] @ r4-r6
69 ldr r10,[r7, #(0x400+7*4)] @ P
74 str r10,[r7, #(0x400+7*4)] @ P
75 str r8, [r7, #0x440] @ r0-r2
76 str r9, [r7, #0x444] @ r4-r6
79 and r9, r9, #(7<<16) @ STACK
81 msr cpsr_flg, r3 @ to to ARM PSR
84 orrmi r6, r6, #0x80000000 @ N
85 orreq r6, r6, #0x20000000 @ Z
87 mov r3, r4, lsl #16 @ Y
89 mov r2, r2, lsl #16 @ X
92 stmia r8, {r2,r3,r5,r6,r9}