use&=~0x0e00; // Use same handler for all registers\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,tea);\r
\r
if(type==1||type==3) {\r
Cycles=8;\r
use=OpBase(op);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op);\r
+ OpStart(op,sea|tea);\r
\r
ot(" mov r10,#1\n");\r
ot("\n");\r
use=OpBase(op);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=size<2?4:6;\r
+ OpStart(op,ea); Cycles=size<2?4:6;\r
if(ea >= 0x10) {\r
Cycles*=2;\r
-#ifdef CYCLONE_FOR_GENESIS\r
+#if CYCLONE_FOR_GENESIS\r
// This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.\r
// May be this is similar case as with TAS opcode, but this time the dummy\r
// read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.\r
ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");\r
OpGetFlags(1,1,0);\r
if(size!=2) {\r
- ot(" movs r1,r1,asr #%i\n",size?16:24);\r
+ ot(" movs r1,r1,asr #%i\n",size?16:24);\r
ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");\r
- }\r
- ot(" andeq r9,r9,r3 ;@ fix Z\n");\r
+ }\r
+ ot(" andeq r9,r9,r3 ;@ fix Z\n");\r
ot("\n");\r
}\r
\r
use=OpBase(op);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ OpStart(op,sea); Cycles=4;\r
\r
EaCalc ( 0,0x003f,sea,size,1);\r
EaRead ( 0, 0,sea,size,0x003f,1);\r
use=OpBase(op);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=8;\r
+ OpStart(op,ea); Cycles=8;\r
if (ea<8) Cycles=4;\r
\r
ot(" mov r1,#0\n");\r
if(count == 1) {\r
if(dir==0) {\r
if(size!=2) {\r
- ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
- ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
- }\r
+ ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
+ ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
+ }\r
GetXBit(0);\r
ot(" movs r0,r0,rrx\n");\r
OpGetFlags(0,1);\r
use=OpBase(op);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=6; // EmitAsr() will add 2\r
+ OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
\r
EaCalc (10,0x003f,ea,size,1);\r
EaRead (10, 0,ea,size,0x003f,1);\r
return 0;\r
}\r
\r
-int OpTas(int op)\r
+int OpTas(int op, int gen_special)\r
{\r
int ea=0;\r
int use=0;\r
use=OpBase(op);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
- OpStart(op); Cycles=4;\r
+ if (!gen_special) OpStart(op,ea);\r
+ else\r
+ ot("Op%.4x_%s\n", op, ms?"":":");\r
+\r
+ Cycles=4;\r
if(ea>=8) Cycles+=10;\r
\r
EaCalc (10,0x003f,ea,0,1);\r
\r
#if CYCLONE_FOR_GENESIS\r
// the original Sega hardware ignores write-back phase (to memory only)\r
- if (ea < 0x10) {\r
+ if (ea < 0x10 || gen_special) {\r
#endif\r
ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
\r
#endif\r
\r
OpEnd();\r
+\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ if (!gen_special && ea >= 0x10) {\r
+ OpTas(op, 1);\r
+ }\r
+#endif\r
+\r
return 0;\r
}\r
\r