* Mega Drive system. As VDP chip in these systems had control of the bus,\r
* several instructions were acting differently, for example TAS did'n have\r
* the write-back phase. That will be emulated, if this option is enabled.\r
- * This option also alters timing slightly.\r
*/\r
#define CYCLONE_FOR_GENESIS 2\r
\r
* MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
* count and this will screw timing (if not cause a deadlock).\r
*/\r
-#define MEMHANDLERS_NEED_PC 1\r
+#define MEMHANDLERS_NEED_PC 0\r
#define MEMHANDLERS_NEED_PREV_PC 0\r
#define MEMHANDLERS_NEED_FLAGS 0\r
#define MEMHANDLERS_NEED_CYCLES 1\r