u32 newPC = (u32)(PC) - BasePC;
SET_PC(newPC-2);
execute_exception(M68K_PRIVILEGE_VIOLATION_EX);
- RET(4)
+ RET(0)
}
RET(20)
}
READ_BYTE_F(adr + 2, src)
DREGu16((Opcode >> 9) & 7) = (res << 8) | src;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(24)
+#endif
}
// MOVEPLaD
READ_BYTE_F(adr, src)
DREG((Opcode >> 9) & 7) = res | src;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(24)
+#else
RET(32)
+#endif
}
// MOVEPWDa
WRITE_BYTE_F(adr + 0, res >> 8)
WRITE_BYTE_F(adr + 2, res >> 0)
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(24)
+#endif
}
// MOVEPLDa
adr += 2;
WRITE_BYTE_F(adr, res >> 0)
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(24)
+#else
RET(32)
+#endif
}
// MOVEB
RET(8)
}
+#if 0
// MOVEB
OPCODE(0x1008)
{
*/
RET(8)
}
+#endif
// MOVEB
OPCODE(0x1010)
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(12)
}
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(12)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(22)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(24)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(26)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(24)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(28)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(24)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(26)
}
adr = AREG(7) - 4;
AREG(7) = adr;
PRE_IO
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(20)
}
flag_N = res >> 24;
adr = AREG(7) - 4;
AREG(7) = adr;
- WRITE_LONG_F(adr, res)
+ WRITE_LONG_DEC_F(adr, res)
POST_IO
RET(22)
}
u32 oldPC=GET_PC;
SET_PC(oldPC-2)
execute_exception(M68K_ILLEGAL_INSTRUCTION_EX);
-RET(4)
+RET(0)
}
// ILLEGAL A000-AFFF
u32 oldPC=GET_PC;
SET_PC(oldPC-2)
execute_exception(M68K_1010_EX);
-RET(4)
+RET(0)
}
// ILLEGAL F000-FFFF
u32 oldPC=GET_PC;
SET_PC(oldPC-2)
execute_exception(M68K_1111_EX);
-RET(4)
+RET(0) // 4 already taken by exc. handler
}
// MOVEMaR
AREG(7) = ASP;
ASP = res;
}
- m68kcontext.execinfo |= M68K_HALTED;
+ m68kcontext.execinfo |= FM68K_HALTED;
m68kcontext.io_cycle_counter = 0;
RET(4)
}
ASP = res;
}
POST_IO
- m68kcontext.execinfo &= ~(M68K_EMULATE_GROUP_0|M68K_EMULATE_TRACE|M68K_DO_TRACE);
+ m68kcontext.execinfo &= ~(FM68K_EMULATE_GROUP_0|FM68K_EMULATE_TRACE|FM68K_DO_TRACE);
CHECK_INT_TO_JUMP(20)
RET(20)
}
dst = AREGu32((Opcode >> 0) & 7);
res = dst + src;
AREG((Opcode >> 0) & 7) = res;
-#ifdef USE_CYCLONE_TIMING_ // breaks Project-X
+#ifdef USE_CYCLONE_TIMING
RET(4)
#else
RET(8)
}
// SUBaD
+#if 0
OPCODE(0x9008)
{
u32 adr, res;
*/
RET(4)
}
+#endif
// SUBaD
OPCODE(0x9010)
}
// CMP
+#if 0
OPCODE(0xB008)
{
u32 adr, res;
*/
RET(4)
}
+#endif
// CMP
OPCODE(0xB010)
}
// ADDaD
+#if 0
OPCODE(0xD008)
{
u32 adr, res;
*/
RET(4)
}
+#endif
// ADDaD
OPCODE(0xD010)
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(14)
+#else
RET(12)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(16)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(20)
+#else
RET(18)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(16)
+#else
RET(14)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(18)
+#else
RET(16)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(12)
+#else
RET(10)
+#endif
}
// ADDA
res = dst + src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
+#ifdef USE_CYCLONE_TIMING
+RET(14)
+#else
RET(12)
+#endif
}
// ADDA