output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
}
+void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
+{
+ assert(rs<16);
+ assert(rt<16);
+ assert(imm<32);
+ assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
+ output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
+}
+
void emit_xor(u_int rs1,u_int rs2,u_int rt)
{
assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
{
u_int offset = addr-(u_int)&dynarec_local;
assert(offset<4096);
- assem_debug("str %s,fp+%d\n",regname[rt],offset);
+ assem_debug("strb %s,fp+%d\n",regname[rt],offset);
output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
}
void emit_writeword_imm(int imm, int addr)
rth=get_reg(i_regmap,rt1[i]|64);
rt=get_reg(i_regmap,rt1[i]);
}
-#ifdef PCSX
- if(rt<0)
- // assume forced dummy read
- rt=get_reg(i_regmap,-1);
-#endif
assert(rs>=0);
- assert(rt>=0);
if(addr<0) addr=rt;
+ if(addr<0)
+ // assume dummy read, no alloced reg
+ addr=get_reg(i_regmap,-1);
assert(addr>=0);
int ftable=0;
if(type==LOADB_STUB||type==LOADBU_STUB)
//if((cc=get_reg(regmap,CCREG))>=0) {
// emit_loadreg(CCREG,cc);
//}
- if(type==LOADB_STUB)
- emit_movsbl((int)&readmem_dword,rt);
- if(type==LOADBU_STUB)
- emit_movzbl((int)&readmem_dword,rt);
- if(type==LOADH_STUB)
- emit_movswl((int)&readmem_dword,rt);
- if(type==LOADHU_STUB)
- emit_movzwl((int)&readmem_dword,rt);
- if(type==LOADW_STUB)
- emit_readword((int)&readmem_dword,rt);
- if(type==LOADD_STUB) {
- emit_readword((int)&readmem_dword,rt);
- if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
+ if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
+ assert(rt>=0);
+ if(type==LOADB_STUB)
+ emit_movsbl((int)&readmem_dword,rt);
+ if(type==LOADBU_STUB)
+ emit_movzbl((int)&readmem_dword,rt);
+ if(type==LOADH_STUB)
+ emit_movswl((int)&readmem_dword,rt);
+ if(type==LOADHU_STUB)
+ emit_movzwl((int)&readmem_dword,rt);
+ if(type==LOADW_STUB)
+ emit_readword((int)&readmem_dword,rt);
+ if(type==LOADD_STUB) {
+ emit_readword((int)&readmem_dword,rt);
+ if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
+ }
}
emit_jmp(stubs[n][2]); // return address
}
#endif
emit_xorimm(temp,24,temp);
emit_movimm(-1,HOST_TEMPREG);
- if (opcode[i]==0x2e) { // SWR
+ if (opcode[i]==0x2a) { // SWL
emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
emit_orrshr(rt,temp,temp2);
}else{
int do_dirty_stub(int i)
{
assem_debug("do_dirty_stub %x\n",start+i*4);
+ u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
+ #ifdef PCSX
+ addr=(u_int)source;
+ #endif
// Careful about the code output here, verify_dirty needs to parse it.
#ifdef ARMv5_ONLY
- emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
+ emit_loadlp(addr,1);
emit_loadlp((int)copy,2);
emit_loadlp(slen*4,3);
#else
- emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
+ emit_movw(addr&0x0000FFFF,1);
emit_movw(((u_int)copy)&0x0000FFFF,2);
- emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
+ emit_movt(addr&0xFFFF0000,1);
emit_movt(((u_int)copy)&0xFFFF0000,2);
emit_movw(slen*4,3);
#endif
else addr=s;
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
}
if(tl>=0) {
}else{
emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
}
- emit_cmpimm(addr,0x800000);
+ emit_cmpimm(addr,RAM_SIZE);
jaddr=(int)out;
emit_jno(0);
}
if((source[i]&0x3f)==0x08) // TLBP
emit_call((int)TLBP);
#endif
+#ifdef PCSX
+ if((source[i]&0x3f)==0x10) // RFE
+ {
+ emit_readword((int)&Status,0);
+ emit_andimm(0,0x3c,1);
+ emit_andimm(0,~0xf,0);
+ emit_orrshr_imm(1,2,0);
+ emit_writeword(0,(int)&Status);
+ }
+#else
if((source[i]&0x3f)==0x18) // ERET
{
int count=ccadj[i];
emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
emit_jmp((int)jump_eret);
}
+#endif
}
}