}
}
- if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
+ if ((psxHu32(0x1070) & psxHu32(0x1074)) && (psxRegs.CP0.n.Status & 0x401) == 0x401) {
psxException(0x400, 0);
pending_exception = 1;
}
evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
MTC0(&psxRegs, reg, val);
gen_interupt();
- if (Cause & Status & 0x0300) // possible sw irq
+ if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x0300) // possible sw irq
pending_exception = 1;
}