#define NO_CYCLE_PENALTY_THR 12
-int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
-int cycle_multiplier_override;
int cycle_multiplier_old;
static int cycle_multiplier_active;
set_jump_target(stubs[n].addr, out);
save_regs(reglist);
- emit_readword(&inv_code_start, 2);
- emit_readword(&inv_code_end, 3);
if (addrr != 0 || ofs_start != 0)
emit_addimm(addrr, ofs_start, 0);
+ emit_readword(&inv_code_start, 2);
+ emit_readword(&inv_code_end, 3);
if (len != 0)
emit_addimm(0, len + 4, (rightr = 1));
emit_cmp(0, 2);
static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
{
- void *hlefunc = psxNULL;
+ void *hlefunc = gteNULL;
uint32_t hleCode = source[i] & 0x03ffffff;
if (hleCode < ARRAY_SIZE(psxHLEt))
hlefunc = psxHLEt[hleCode];
stat_clear(stat_blocks);
stat_clear(stat_links);
- cycle_multiplier_old = cycle_multiplier;
+ cycle_multiplier_old = Config.cycle_multiplier;
new_dynarec_hacks_old = new_dynarec_hacks;
}
#endif
#endif
out = ndrc->translation_cache;
- cycle_multiplier=200;
new_dynarec_clear_full();
#ifdef HOST_IMM8
// Copy this into local area so we don't have to put it in every literal pool
(0xbfc00000 <= addr && addr < 0xbfc80000)))
{
// BIOS. The multiplier should be much higher as it's uncached 8bit mem,
- // but timings in PCSX are too tied to the interpreter's BIAS
+ // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
cycle_multiplier_active = 200;
return 0;
}
- cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
- ? cycle_multiplier_override : cycle_multiplier;
+ cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
+ ? Config.cycle_multiplier_override : Config.cycle_multiplier;
source = get_source_start(start, &pagelimit);
if (source == NULL) {