#define COP2 27 // Coprocessor 2 move
#define C2LS 28 // Coprocessor 2 load/store
#define C2OP 29 // Coprocessor 2 operation
+#define INTCALL 30// Call interpreter to handle rare corner cases
/* stubs */
#define CC_STUB 1
void jump_syscall_hle();
void jump_eret();
void jump_hlecall();
+void jump_intcall();
void new_dyna_leave();
// TLB
j++;
break;
}
- if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
+ if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
{
break;
}
if(((ptr>>shift)==(addr>>shift)) ||
(((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
{
- printf("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
+ inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
u_int host_addr=(u_int)kill_pointer(head->addr);
if((host_addr>>12)!=(old_host_addr>>12)) {
emit_jmp((int)jump_hlecall);
}
+void intcall_assemble(int i,struct regstat *i_regs)
+{
+ signed char ccreg=get_reg(i_regs->regmap,CCREG);
+ assert(ccreg==HOST_CCREG);
+ assert(!is_delayslot);
+ emit_movimm(start+i*4,0); // Get PC
+ emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
+ emit_jmp((int)jump_intcall);
+}
+
void ds_assemble(int i,struct regstat *i_regs)
{
is_delayslot=1;
mov_assemble(i,i_regs);break;
case SYSCALL:
case HLECALL:
+ case INTCALL:
case SPAN:
case UJUMP:
case RJUMP:
mov_assemble(t,®s[t]);break;
case SYSCALL:
case HLECALL:
+ case INTCALL:
case SPAN:
case UJUMP:
case RJUMP:
mov_assemble(0,®s[0]);break;
case SYSCALL:
case HLECALL:
+ case INTCALL:
case SPAN:
case UJUMP:
case RJUMP:
}
}
}
- else if(itype[i]==SYSCALL||itype[i]==HLECALL)
+ else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
{
// SYSCALL instruction (software interrupt)
u=1;
if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
}
}
- else if(itype[i]==SYSCALL||itype[i]==HLECALL)
+ else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
{
// SYSCALL instruction (software interrupt)
r32=0;
}
}
}
- else if(itype[i]==SYSCALL||itype[i]==HLECALL)
+ else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
{
// SYSCALL instruction (software interrupt)
will_dirty_i=0;
case C2LS:
printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
break;
+ case INTCALL:
+ printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
+ break;
default:
//printf (" %s %8x\n",insn[i],source[i]);
printf (" %x: %s\n",start+i*4,insn[i]);
break;
}
break;
+#ifndef FORCE32
case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
-#ifndef FORCE32
case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
#endif
#ifdef PCSX
case 0x12: strcpy(insn[i],"COP2"); type=NI;
+ // note: COP MIPS-1 encoding differs from MIPS32
op2=(source[i]>>21)&0x1f;
- switch(op2)
+ if (source[i]&0x3f) {
+ if (gte_handlers[source[i]&0x3f]!=NULL) {
+ snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
+ type=C2OP;
+ }
+ }
+ else switch(op2)
{
case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
- default:
- if (gte_handlers[source[i]&0x3f]!=NULL) {
- snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
- type=C2OP;
- }
- break;
}
break;
case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
break;
}
+#ifdef PCSX
+ /* detect branch in delay slot early */
+ if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
+ opcode[i+1]=source[i+1]>>26;
+ opcode2[i+1]=source[i+1]&0x3f;
+ if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
+ printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
+ // don't handle first branch and call interpreter if it's hit
+ type=INTCALL;
+ }
+ }
+#endif
itype[i]=type;
opcode2[i]=op2;
/* Get registers/immediates */
break;
case SYSCALL:
case HLECALL:
+ case INTCALL:
rs1[i]=CCREG;
rs2[i]=0;
rt1[i]=0;
/* Is this the end of the block? */
if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
- done=1;
- // Does the block continue due to a branch?
- for(j=i-1;j>=0;j--)
- {
- if(ba[j]==start+i*4+4) done=j=0;
- if(ba[j]==start+i*4+8) done=j=0;
- }
+ done=2;
}
else {
if(stop_after_jal) done=1;
if(i>MAXBLOCK/2) done=1;
}
if(itype[i]==SYSCALL&&stop_after_jal) done=1;
- if(itype[i]==HLECALL) done=1;
+ if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
+ if(done==2) {
+ // Does the block continue due to a branch?
+ for(j=i-1;j>=0;j--)
+ {
+ if(ba[j]==start+i*4+4) done=j=0;
+ if(ba[j]==start+i*4+8) done=j=0;
+ }
+ }
//assert(i<MAXBLOCK-1);
if(start+i*4==pagelimit-4) done=1;
assert(start+i*4<pagelimit);
break;
case SYSCALL:
case HLECALL:
+ case INTCALL:
syscall_alloc(¤t,i);
break;
case SPAN:
}
}
}
- else if(itype[i]==SYSCALL||itype[i]==HLECALL)
+ else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
{
// SYSCALL instruction (software interrupt)
nr=0;
f_regmap[hr]=regs[i].regmap[hr];
else f_regmap[hr]=-1;
}
- else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
+ else if(regs[i].regmap[hr]>=0) {
+ if(f_regmap[hr]!=regs[i].regmap[hr]) {
+ // dealloc old register
+ int n;
+ for(n=0;n<HOST_REGS;n++)
+ {
+ if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
+ }
+ // and alloc new one
+ f_regmap[hr]=regs[i].regmap[hr];
+ }
+ }
if(branch_regs[i].regmap[hr]>64) {
if(!((branch_regs[i].dirty>>hr)&1))
f_regmap[hr]=branch_regs[i].regmap[hr];
else f_regmap[hr]=-1;
}
- else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
+ else if(branch_regs[i].regmap[hr]>=0) {
+ if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
+ // dealloc old register
+ int n;
+ for(n=0;n<HOST_REGS;n++)
+ {
+ if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
+ }
+ // and alloc new one
+ f_regmap[hr]=branch_regs[i].regmap[hr];
+ }
+ }
if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
||itype[i+1]==FCOMP||itype[i+1]==FCONV
if(!((regs[i].dirty>>hr)&1))
f_regmap[hr]=regs[i].regmap[hr];
}
- else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
+ else if(regs[i].regmap[hr]>=0) {
+ if(f_regmap[hr]!=regs[i].regmap[hr]) {
+ // dealloc old register
+ int n;
+ for(n=0;n<HOST_REGS;n++)
+ {
+ if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
+ }
+ // and alloc new one
+ f_regmap[hr]=regs[i].regmap[hr];
+ }
+ }
else if(regs[i].regmap[hr]<0) count++;
}
}
if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
}
}
- else if(itype[i]==SYSCALL||itype[i]==HLECALL)
+ else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
{
// SYSCALL instruction (software interrupt)
r32=0;
syscall_assemble(i,®s[i]);break;
case HLECALL:
hlecall_assemble(i,®s[i]);break;
+ case INTCALL:
+ intcall_assemble(i,®s[i]);break;
case UJUMP:
ujump_assemble(i,®s[i]);ds=1;break;
case RJUMP: