make_dma_func(4)
make_dma_func(6)
+static u32 io_spu_read16(u32 addr)
+{
+ return SPU_readRegister(addr, psxRegs.cycle);
+}
+
+static u32 io_spu_read32(u32 addr)
+{
+ u32 ret;
+ ret = SPU_readRegister(addr, psxRegs.cycle);
+ ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16;
+ return ret;
+}
+
static void io_spu_write16(u32 value)
{
// meh
map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
+ for (i = 0x1c00; i < 0x2000; i += 2) {
+ map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1);
+ map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1);
+ }
+
// write(u32 data)
map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1);
void new_dyna_pcsx_mem_reset(void)
{
- int i;
-
// plugins might change so update the pointers
map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
-
- for (i = 0x1c00; i < 0x2000; i += 2)
- map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
-
map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
}