RENDER_STATE_MASK_EVALUATE = 0x20,
} render_state_enum;
+typedef enum
+{
+ RENDER_INTERLACE_ENABLED = 0x1,
+ RENDER_INTERLACE_ODD = 0x2,
+ RENDER_DOUBLE_MODE = 0x4,
+} render_mode_enum;
+
typedef struct
{
u16 left_x;
vec_4x32u g_block_span;
vec_4x32u b_block_span;
- // 72 bytes
u32 b;
u32 b_dy;
u32 triangle_color;
u32 dither_table[4];
+ u32 uvrgb_phase;
+
struct render_block_handler_struct *render_block_handler;
void *texture_page_ptr;
void *texture_page_base;
u16 *clut_ptr;
u16 *vram_ptr;
+ u16 *vram_out_ptr;
- // 26 bytes
u16 render_state_base;
u16 render_state;
u16 num_spans;
u16 num_blocks;
- s16 offset_x;
- s16 offset_y;
-
- u16 clut_settings;
- u16 texture_settings;
-
s16 viewport_start_x;
s16 viewport_start_y;
s16 viewport_end_x;
u16 mask_msb;
- // 8 bytes
u8 triangle_winding;
u8 display_area_draw_enable;
u8 texture_window_y;
u8 primitive_type;
+ u8 render_mode;
+
+ s16 offset_x;
+ s16 offset_y;
+
+ u16 clut_settings;
+ u16 texture_settings;
+
+ // enhancement stuff
+ u16 *enhancement_buf_ptr;
+ s16 saved_viewport_start_x;
+ s16 saved_viewport_start_y;
+ s16 saved_viewport_end_x;
+ s16 saved_viewport_end_y;
// Align up to 64 byte boundary to keep the upcoming buffers cache line
- // aligned
- u8 reserved_a[1];
+ // aligned, also make reachable with single immediate addition
+ u8 reserved_a[236];
// 8KB
block_struct blocks[MAX_BLOCKS_PER_ROW];
void flush_render_block_buffer(psx_gpu_struct *psx_gpu);
void initialize_psx_gpu(psx_gpu_struct *psx_gpu, u16 *vram);
-void gpu_parse(psx_gpu_struct *psx_gpu, u32 *list, u32 size);
+u32 gpu_parse(psx_gpu_struct *psx_gpu, u32 *list, u32 size, u32 *last_command);
void triangle_benchmark(psx_gpu_struct *psx_gpu);