static noinline void do_cmd_reset(void)
{
+ renderer_sync();
+
if (unlikely(gpu.cmd_len > 0))
do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len);
gpu.cmd_len = 0;
static noinline void do_reset(void)
{
unsigned int i;
-
do_cmd_reset();
memset(gpu.regs, 0, sizeof(gpu.regs));
int l;
count *= 2; // operate in 16bpp pixels
+ renderer_sync();
+
if (gpu.dma.offset) {
l = w - gpu.dma.offset;
if (count < l)
cmd = data[pos] >> 24;
if (0xa0 <= cmd && cmd <= 0xdf) {
+ if (unlikely((pos+2) >= count)) {
+ // incomplete vram write/read cmd, can't consume yet
+ cmd = -1;
+ break;
+ }
+
// consume vram write/read cmd
start_vram_transfer(data[pos + 1], data[pos + 2], (cmd & 0xe0) == 0xc0);
pos += 3;
case 1: // save
if (gpu.cmd_len > 0)
flush_cmd_buffer();
+
+ renderer_sync();
memcpy(freeze->psxVRam, gpu.vram, 1024 * 512 * 2);
memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs));
memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs));
freeze->ulStatus = gpu.status.reg;
break;
case 0: // load
+ renderer_sync();
memcpy(gpu.vram, freeze->psxVRam, 1024 * 512 * 2);
memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
return;
}
+ renderer_notify_update_lace(0);
+
if (!gpu.state.fb_dirty)
return;
vout_update();
gpu.state.fb_dirty = 0;
gpu.state.blanked = 0;
+ renderer_notify_update_lace(1);
}
void GPUvBlank(int is_vblank, int lcf)