+ ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r
+ SuperChange(op,1);\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#endif\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ opend_check_interrupt = 1;\r
+ opend_check_trace = 1;\r
+ OpEnd(0x10,0);\r
+ return 0;\r
+\r
+ case 5: // rts\r
+ OpStart(op,0x10); Cycles=16;\r
+ PopPc();\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1 ;@ address error?\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ OpEnd(0x10);\r
+ return 0;\r
+\r
+ case 6: // trapv\r
+ OpStart(op,0x10,0,1); Cycles=4;\r
+ ot(" tst r10,#0x10000000\n");\r
+ ot(" subne r5,r5,#%i\n",34);\r
+ ot(" movne r0,#7 ;@ TRAPV exception\n");\r
+ ot(" blne Exception\n");\r
+ opend_op_changes_cycles = 1;\r
+ OpEnd(0x10,0);\r