- unsigned int pc=0;\r
-\r
- pc=*(unsigned int *)(cpu+0x40);\r
-\r
-#ifdef EMU_A68K\r
- memcpy(M68000_regs.d,cpu,0x40);\r
- M68000_regs.pc=pc;\r
- M68000_regs.ccr=*(unsigned char *)(cpu+0x44);\r
- M68000_regs.srh=*(unsigned char *)(cpu+0x45);\r
- M68000_regs.isp=*(unsigned int *)(cpu+0x48);\r
-#endif\r
-\r
-#ifdef EMU_C68K\r
- CycloneSetSr(&PicoCpu, *(unsigned int *)(cpu+0x44));\r
- PicoCpu.osp=*(unsigned int *)(cpu+0x48);\r
- memcpy(PicoCpu.d,cpu,0x40);\r
- PicoCpu.membase=0;\r
- PicoCpu.pc =PicoCpu.checkpc(pc); // Base pc\r
-#endif\r
-\r
-#ifdef EMU_M68K\r
- memcpy(m68ki_cpu.dar,cpu,0x40);\r
- m68ki_cpu.pc=pc;\r
+#if defined(EMU_C68K)\r
+ struct Cyclone *context = is_sub ? &PicoCpuCS68k : &PicoCpuCM68k;\r
+ CycloneSetSr(context, *(unsigned int *)(cpu+0x44));\r
+ context->osp=*(unsigned int *)(cpu+0x48);\r
+ memcpy(context->d,cpu,0x40);\r
+ context->membase=0;\r
+ context->pc = context->checkpc(*(unsigned int *)(cpu+0x40)); // Base pc\r
+ context->irq = cpu[0x4c];\r
+ context->state_flags = 0;\r
+ if (cpu[0x4d])\r
+ context->state_flags |= 1;\r
+#elif defined(EMU_M68K)\r
+ void *oldcontext = m68ki_cpu_p;\r
+ m68k_set_context(is_sub ? &PicoCpuMS68k : &PicoCpuMM68k);\r
+ memcpy(m68ki_cpu_p->dar,cpu,0x40);\r
+ m68ki_cpu_p->pc=*(unsigned int *)(cpu+0x40);\r