+/* handle writes r0 to (rX). Trashes r1.
+ * fortunately we can ignore modulo increment modes for writes. */
+static void tr_rX_write(int op)
+{
+ if ((op&3) == 3)
+ {
+ int mod = (op>>2) & 3; // direct addressing
+ tr_bank_write((op & 0x100) + mod);
+ }
+ else
+ {
+ int r = (op&3) | ((op>>6)&4);
+ if (known_regb & (1 << (r + 8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
+ }
+}
+
+/* read (rX) to r0. Trashes r1-r3. */
+static void tr_rX_read(int r, int mod)
+{
+ if ((r&3) == 3)
+ {
+ tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
+ }
+ else
+ {
+ if (known_regb & (1 << (r + 8))) {
+ tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ hostreg_r[0] = hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, mod, 1, 1);
+ }
+}
+
+/* read ((rX)) to r0. Trashes r1,r2. */
+static void tr_rX_read2(int op)
+{
+ int r = (op&3) | ((op>>6)&4); // src
+
+ if ((r&3) == 3) {
+ tr_bank_read((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_read((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ }
+ EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
+ EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
+ EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
+ if ((r&3) == 3) {
+ tr_bank_write((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
+ hostreg_r[0] = hostreg_r[2] = -1;
+}
+
+/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
+static int tr_cond_check(int op)
+{
+ int f = (op & 0x100) >> 8;
+ switch (op&0xf0) {
+ case 0x00: return A_COND_AL; /* always true */
+ case 0x50: /* Z matches f(?) bit */
+ if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
+ EOP_TST_IMM(6, 0, 4);
+ return f ? A_COND_NE : A_COND_EQ;
+ case 0x70: /* N matches f(?) bit */
+ if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
+ EOP_TST_IMM(6, 0, 8);
+ return f ? A_COND_NE : A_COND_EQ;
+ default:
+ printf("unimplemented cond?\n");
+ tr_unhandled();
+ return 0;
+ }
+}
+
+static int tr_neg_cond(int cond)
+{
+ switch (cond) {
+ case A_COND_AL: printf("neg for AL?\n"); exit(1);
+ case A_COND_EQ: return A_COND_NE;
+ case A_COND_NE: return A_COND_EQ;
+ case A_COND_MI: return A_COND_PL;
+ case A_COND_PL: return A_COND_MI;
+ default: printf("bad cond for neg\n"); exit(1);
+ }
+ return 0;
+}
+
+static int tr_aop_ssp2arm(int op)
+{
+ switch (op) {
+ case 1: return A_OP_SUB;
+ case 3: return A_OP_CMP;
+ case 4: return A_OP_ADD;
+ case 5: return A_OP_AND;
+ case 6: return A_OP_ORR;
+ case 7: return A_OP_EOR;
+ }
+
+ tr_unhandled();
+ return 0;
+}
+
+// -----------------------------------------------------
+
+// SSP_GR0, SSP_X, SSP_Y, SSP_A,
+// SSP_ST, SSP_STACK, SSP_PC, SSP_P,
+//@ r4: XXYY
+//@ r5: A
+//@ r6: STACK and emu flags
+//@ r7: SSP context
+//@ r10: P
+
+// read general reg to r0. Trashes r1
+static void tr_GR0_to_r0(int op)
+{
+ tr_mov16(0, 0xffff);
+}
+
+static void tr_X_to_r0(int op)
+{
+ if (hostreg_r[0] != (SSP_X<<16)) {
+ EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
+ hostreg_r[0] = SSP_X<<16;
+ }
+}
+
+static void tr_Y_to_r0(int op)
+{
+ // TODO..
+ if (hostreg_r[0] != (SSP_Y<<16)) {
+ EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
+ hostreg_r[0] = SSP_Y<<16;
+ }
+}
+
+static void tr_A_to_r0(int op)
+{
+ if (hostreg_r[0] != (SSP_A<<16)) {
+ EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
+ hostreg_r[0] = SSP_A<<16;
+ }
+}
+
+static void tr_ST_to_r0(int op)
+{
+ // VR doesn't need much accuracy here..
+ EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
+ EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
+ hostreg_r[0] = -1;
+}
+
+static void tr_STACK_to_r0(int op)
+{
+ // 448
+ EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
+ EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
+ EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
+ EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
+ EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
+ hostreg_r[0] = hostreg_r[1] = -1;
+}
+
+static void tr_PC_to_r0(int op)
+{
+ tr_mov16(0, known_regs.gr[SSP_PC].h);
+}
+
+static void tr_P_to_r0(int op)
+{
+ tr_flush_dirty_P();
+ EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
+ hostreg_r[0] = -1;
+}
+
+static void tr_AL_to_r0(int op)
+{
+ if (op == 0x000f) {
+ if (known_regb & KRREG_PMC) {
+ known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
+ } else {
+ EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
+ EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
+ EOP_STR_IMM(0,7,0x484);
+ }
+ }
+
+ if (hostreg_r[0] != (SSP_AL<<16)) {
+ EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
+ hostreg_r[0] = SSP_AL<<16;
+ }
+}
+
+static void tr_PMX_to_r0(int reg)
+{
+ if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
+ {
+ known_regs.pmac_read[reg] = known_regs.pmc.v;
+ known_regs.emu_status &= ~SSP_PMC_SET;
+ known_regb |= 1 << (20+reg);
+ dirty_regb |= 1 << (20+reg);
+ return;
+ }
+
+ if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
+ {
+ u32 pmcv = known_regs.pmac_read[reg];
+ int mode = pmcv>>16;
+ known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
+
+ if ((mode & 0xfff0) == 0x0800)
+ {
+ EOP_LDR_IMM(1,7,0x488); // rom_ptr
+ emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
+ EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
+ known_regs.pmac_read[reg] += 1;
+ }
+ else if ((mode & 0x47ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ EOP_LDR_IMM(1,7,0x490); // dram_ptr
+ emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
+ EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
+ if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
+ {
+ int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
+ tr_flush_dirty_ST();
+ EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
+ EOP_TST_REG_SIMPLE(0,0);
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // addeq r11, r11, #1024
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
+ EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
+ }
+ known_regs.pmac_read[reg] += inc;
+ }
+ else
+ {
+ tr_unhandled();
+ }
+ known_regs.pmc.v = known_regs.pmac_read[reg];
+ //known_regb |= KRREG_PMC;
+ dirty_regb |= KRREG_PMC;
+ dirty_regb |= 1 << (20+reg);
+ hostreg_r[0] = hostreg_r[1] = -1;
+ return;
+ }
+
+ known_regb &= ~KRREG_PMC;
+ dirty_regb &= ~KRREG_PMC;
+ known_regb &= ~(1 << (20+reg));
+ dirty_regb &= ~(1 << (20+reg));
+
+ // call the C code to handle this
+ tr_flush_dirty_ST();
+ //tr_flush_dirty_pmcrs();
+ tr_mov16(0, reg);
+ emit_call(ssp_pm_read);
+ hostreg_clear();
+}
+
+static void tr_PM0_to_r0(int op)
+{
+ tr_PMX_to_r0(0);
+}
+
+static void tr_PM1_to_r0(int op)
+{
+ tr_PMX_to_r0(1);
+}
+
+static void tr_PM2_to_r0(int op)
+{
+ tr_PMX_to_r0(2);
+}
+
+static void tr_XST_to_r0(int op)
+{
+ EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
+ EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
+}
+
+static void tr_PM4_to_r0(int op)
+{
+ tr_PMX_to_r0(4);
+}
+
+static void tr_PMC_to_r0(int op)
+{
+ if (known_regb & KRREG_PMC)
+ {
+ if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
+ known_regs.emu_status |= SSP_PMC_SET;
+ known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
+ // do nothing - this is handled elsewhere
+ } else {
+ tr_mov16(0, known_regs.pmc.l);
+ known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
+ }
+ }
+ else
+ {
+ EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
+ tr_flush_dirty_ST();
+ if (op != 0x000e)
+ EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
+ EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
+ EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
+ EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
+ EOP_STR_IMM(1,7,0x484);
+ hostreg_r[0] = hostreg_r[1] = -1;
+ }
+}
+
+
+typedef void (tr_read_func)(int op);
+
+static tr_read_func *tr_read_funcs[16] =
+{
+ tr_GR0_to_r0,
+ tr_X_to_r0,
+ tr_Y_to_r0,
+ tr_A_to_r0,
+ tr_ST_to_r0,
+ tr_STACK_to_r0,
+ tr_PC_to_r0,
+ tr_P_to_r0,
+ tr_PM0_to_r0,
+ tr_PM1_to_r0,
+ tr_PM2_to_r0,
+ tr_XST_to_r0,
+ tr_PM4_to_r0,
+ (tr_read_func *)tr_unhandled,
+ tr_PMC_to_r0,
+ tr_AL_to_r0
+};
+
+
+// write r0 to general reg handlers. Trashes r1
+#define TR_WRITE_R0_TO_REG(reg) \
+{ \
+ hostreg_sspreg_changed(reg); \
+ hostreg_r[0] = (reg)<<16; \
+ if (const_val != -1) { \
+ known_regs.gr[reg].h = const_val; \
+ known_regb |= 1 << (reg); \
+ } else { \
+ known_regb &= ~(1 << (reg)); \
+ } \
+}
+
+static void tr_r0_to_GR0(int const_val)
+{
+ // do nothing
+}
+
+static void tr_r0_to_X(int const_val)
+{
+ EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
+ EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
+ EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
+ dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
+ TR_WRITE_R0_TO_REG(SSP_X);
+}
+
+static void tr_r0_to_Y(int const_val)
+{
+ EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
+ EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
+ EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
+ dirty_regb |= KRREG_P;
+ TR_WRITE_R0_TO_REG(SSP_Y);
+}
+
+static void tr_r0_to_A(int const_val)
+{
+ EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
+ EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
+ EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
+ TR_WRITE_R0_TO_REG(SSP_A);
+}
+
+static void tr_r0_to_ST(int const_val)
+{
+ // VR doesn't need much accuracy here..
+ EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
+ EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
+ EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
+ TR_WRITE_R0_TO_REG(SSP_ST);
+ hostreg_r[1] = -1;
+ dirty_regb &= ~KRREG_ST;
+}
+
+static void tr_r0_to_STACK(int const_val)
+{
+ // 448
+ EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
+ EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
+ EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
+ EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
+ EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
+ hostreg_r[1] = -1;
+}
+
+static void tr_r0_to_PC(int const_val)
+{
+ EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
+ EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
+ hostreg_r[1] = -1;
+}
+
+static void tr_r0_to_AL(int const_val)
+{
+ EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
+ EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
+ EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
+ hostreg_sspreg_changed(SSP_AL);
+ if (const_val != -1) {
+ known_regs.gr[SSP_A].l = const_val;
+ known_regb |= 1 << SSP_AL;
+ } else
+ known_regb &= ~(1 << SSP_AL);
+}
+
+static void tr_r0_to_PMX(int reg)
+{
+#if 1
+ if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
+ {
+ known_regs.pmac_write[reg] = known_regs.pmc.v;
+ known_regs.emu_status &= ~SSP_PMC_SET;
+ known_regb |= 1 << (25+reg);
+ dirty_regb |= 1 << (25+reg);
+ return;
+ }
+#endif
+#if 1
+ if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
+ {
+ int mode, addr;
+
+ known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
+
+ mode = known_regs.pmac_write[reg]>>16;
+ addr = known_regs.pmac_write[reg]&0xffff;
+ if ((mode & 0x43ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ if (mode & 0x0400) tr_unhandled();
+ EOP_LDR_IMM(1,7,0x490); // dram_ptr
+ emit_mov_const(A_COND_AL, 2, addr<<1);
+ EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
+ known_regs.pmac_write[reg] += inc;
+ }
+ else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
+ {
+ if (mode & 0x0400) tr_unhandled();
+ EOP_LDR_IMM(1,7,0x490); // dram_ptr
+ emit_mov_const(A_COND_AL, 2, addr<<1);
+ EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
+ known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
+ }
+ else if ((mode & 0x47ff) == 0x001c) // IRAM
+ {
+ int inc = get_inc(mode);
+ EOP_LDR_IMM(1,7,0x48c); // iram_ptr
+ emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
+ EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
+ EOP_MOV_IMM(1,0,1);
+ EOP_STR_IMM(1,7,0x494); // iram_dirty
+ known_regs.pmac_write[reg] += inc;
+ }
+ else
+ tr_unhandled();
+
+ known_regs.pmc.v = known_regs.pmac_write[reg];
+ //known_regb |= KRREG_PMC;
+ dirty_regb |= KRREG_PMC;
+ dirty_regb |= 1 << (25+reg);
+ hostreg_r[1] = hostreg_r[2] = -1;
+ return;
+ }
+
+ known_regb &= ~KRREG_PMC;
+ dirty_regb &= ~KRREG_PMC;
+ known_regb &= ~(1 << (25+reg));
+ dirty_regb &= ~(1 << (25+reg));
+#else
+tr_flush_dirty_pmcrs();
+hostreg_clear();
+known_regb &= ~KRREG_PMC;
+dirty_regb &= ~KRREG_PMC;
+known_regb &= ~(1 << (25+reg));
+dirty_regb &= ~(1 << (25+reg));
+#endif
+
+
+ // call the C code to handle this
+ tr_flush_dirty_ST();
+ //tr_flush_dirty_pmcrs();
+ tr_mov16(1, reg);
+ emit_call(ssp_pm_write);
+ hostreg_clear();
+}
+
+static void tr_r0_to_PM0(int const_val)
+{
+ tr_r0_to_PMX(0);
+}
+
+static void tr_r0_to_PM1(int const_val)
+{
+ tr_r0_to_PMX(1);
+}
+
+static void tr_r0_to_PM2(int const_val)
+{
+ tr_r0_to_PMX(2);
+}
+
+static void tr_r0_to_PM4(int const_val)
+{
+ tr_r0_to_PMX(4);
+}
+
+static void tr_r0_to_PMC(int const_val)
+{
+ if ((known_regb & KRREG_PMC) && const_val != -1)
+ {
+ if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
+ known_regs.emu_status |= SSP_PMC_SET;
+ known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
+ known_regs.pmc.h = const_val;
+ } else {
+ known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
+ known_regs.pmc.l = const_val;
+ }
+ }
+ else
+ {
+ tr_flush_dirty_ST();
+ if (known_regb & KRREG_PMC) {
+ emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
+ EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
+ known_regb &= ~KRREG_PMC;
+ dirty_regb &= ~KRREG_PMC;
+ }
+ EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
+ EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
+ EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
+ EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
+ EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
+ EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
+ EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
+ EOP_STR_IMM(1,7,0x484);
+ hostreg_r[1] = hostreg_r[2] = -1;
+ }
+}
+
+typedef void (tr_write_func)(int const_val);
+
+static tr_write_func *tr_write_funcs[16] =
+{
+ tr_r0_to_GR0,
+ tr_r0_to_X,
+ tr_r0_to_Y,
+ tr_r0_to_A,
+ tr_r0_to_ST,
+ tr_r0_to_STACK,
+ tr_r0_to_PC,
+ (tr_write_func *)tr_unhandled,
+ tr_r0_to_PM0,
+ tr_r0_to_PM1,
+ tr_r0_to_PM2,
+ (tr_write_func *)tr_unhandled,
+ tr_r0_to_PM4,
+ (tr_write_func *)tr_unhandled,
+ tr_r0_to_PMC,
+ tr_r0_to_AL
+};
+
+static void tr_mac_load_XY(int op)
+{
+ tr_rX_read(op&3, (op>>2)&3); // X
+ EOP_MOV_REG_LSL(4, 0, 16);
+ tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
+ EOP_ORR_REG_SIMPLE(4, 0);
+ dirty_regb |= KRREG_P;
+ hostreg_sspreg_changed(SSP_X);
+ hostreg_sspreg_changed(SSP_Y);
+ known_regb &= ~KRREG_X;
+ known_regb &= ~KRREG_Y;
+}
+
+// -----------------------------------------------------
+
+static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
+{
+ u32 pmcv, tmpv;
+ if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
+
+ // programming PMC:
+ // ldi PMC, imm1
+ // ldi PMC, imm2
+ (*pc)++;
+ pmcv = imm | (PROGRAM((*pc)++) << 16);
+ known_regs.pmc.v = pmcv;
+ known_regb |= KRREG_PMC;
+ dirty_regb |= KRREG_PMC;
+ known_regs.emu_status |= SSP_PMC_SET;
+
+ // check for possible reg programming
+ tmpv = PROGRAM(*pc);
+ if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
+ {
+ int is_write = (tmpv & 0xff8f) == 0x80;
+ int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
+ if (reg > 4) tr_unhandled();
+ if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
+ known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
+ known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
+ dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
+ known_regs.emu_status &= ~SSP_PMC_SET;
+ (*pc)++;
+ return 5;
+ }
+
+ tr_unhandled();
+ return 4;
+}
+
+static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
+
+static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
+{
+ // ldi ST, 0
+ // ldi PM0, 0
+ // ldi PM0, 0
+ // ldi ST, 60h
+ unsigned short *pp;
+ if (op != 0x0840 || imm != 0) return 0;
+ pp = PROGRAM_P(*pc);
+ if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
+
+ EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
+ EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
+ hostreg_sspreg_changed(SSP_ST);
+ known_regs.gr[SSP_ST].h = 0x60;
+ known_regb |= 1 << SSP_ST;
+ dirty_regb &= ~KRREG_ST;
+ (*pc) += 3*2;
+ return 4*2;
+}
+
+static int tr_detect_rotate(unsigned int op, int *pc, int imm)
+{
+ // @ 3DA2 and 426A
+ // ld PMC, (r3|00)
+ // ld (r3|00), PMC
+ // ld -, AL
+ if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
+
+ tr_bank_read(0);
+ EOP_MOV_REG_LSL(0, 0, 4);
+ EOP_ORR_REG_LSR(0, 0, 0, 16);
+ tr_bank_write(0);
+ (*pc) += 2;
+ return 3;
+}
+
+// -----------------------------------------------------