+ if (modulo_shift == -1)
+ {
+ int reg = (r < 4) ? 8 : 9;
+ tr_release_pr(r);
+ if (dirty_regb & KRREG_ST) {
+ // avoid flushing ARM flags
+ EOP_AND_IMM(1, 6, 0, 0x70);
+ EOP_SUB_IMM(1, 1, 0, 0x10);
+ EOP_AND_IMM(1, 1, 0, 0x70);
+ EOP_ADD_IMM(1, 1, 0, 0x10);
+ } else {
+ EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
+ }
+ EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
+ EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
+ EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
+ if (r&3)
+ EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
+ EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
+ if (mod == 2)
+ EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
+ else EOP_ADD_REG2_LSL(reg,reg,3,2);
+ EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
+ EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
+ hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
+ }
+ else if (known_regb & (1 << (r + 8)))
+ {
+ int modulo = (1 << modulo_shift) - 1;
+ if (mod == 2)
+ known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
+ else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
+ }
+ else
+ {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
+ EOP_MOV_REG_ROR(reg,reg,ror);
+ // {add|sub} reg, reg, #1<<shift
+ EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
+ EOP_MOV_REG_ROR(reg,reg,32-ror);
+ }
+}
+
+/* handle writes r0 to (rX). Trashes r1.
+ * fortunately we can ignore modulo increment modes for writes. */
+static void tr_rX_write(int op)
+{
+ if ((op&3) == 3)
+ {
+ int mod = (op>>2) & 3; // direct addressing
+ tr_bank_write((op & 0x100) + mod);
+ }
+ else
+ {
+ int r = (op&3) | ((op>>6)&4);
+ if (known_regb & (1 << (r + 8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
+ }
+}
+
+/* read (rX) to r0. Trashes r1-r3. */
+static void tr_rX_read(int r, int mod)
+{
+ if ((r&3) == 3)
+ {
+ tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
+ }
+ else
+ {
+ if (known_regb & (1 << (r + 8))) {
+ tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ hostreg_r[0] = hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, mod, 1, 1);
+ }
+}
+
+/* read ((rX)) to r0. Trashes r1,r2. */
+static void tr_rX_read2(int op)
+{
+ int r = (op&3) | ((op>>6)&4); // src
+
+ if ((r&3) == 3) {
+ tr_bank_read((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_read((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ }
+ EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
+ EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
+ EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
+ if ((r&3) == 3) {
+ tr_bank_write((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
+ hostreg_r[0] = hostreg_r[2] = -1;
+}
+
+// check if AL is going to be used later in block
+static int tr_predict_al_need(void)
+{
+ int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
+
+ while (1)
+ {
+ op = PROGRAM(pc);
+ switch (op >> 9)
+ {
+ // ld d, s
+ case 0x00:
+ tmpv2 = (op >> 4) & 0xf; // dst
+ tmpv = op & 0xf; // src
+ if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
+ return 0;
+ break;
+
+ // ld (ri), s
+ case 0x02:
+ // ld ri, s
+ case 0x0a:
+ // OP a, s
+ case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
+ tmpv = op & 0xf; // src
+ if (tmpv == SSP_AL) // OP *, AL
+ return 1;
+ break;
+
+ case 0x04:
+ case 0x06:
+ case 0x14:
+ case 0x34:
+ case 0x44:
+ case 0x64:
+ case 0x74: pc++; break;
+
+ // call cond, addr
+ case 0x24:
+ // bra cond, addr
+ case 0x26:
+ // mod cond, op
+ case 0x48:
+ // mpys?
+ case 0x1b:
+ // mpya (rj), (ri), b
+ case 0x4b: return 1;
+
+ // mld (rj), (ri), b
+ case 0x5b: return 0; // cleared anyway
+
+ // and A, *
+ case 0x50:
+ tmpv = op & 0xf; // src
+ if (tmpv == SSP_AL) return 1;
+ case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
+ return 0;
+ }
+ pc++;
+ }
+}
+
+
+/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
+static int tr_cond_check(int op)
+{
+ int f = (op & 0x100) >> 8;
+ switch (op&0xf0) {
+ case 0x00: return A_COND_AL; /* always true */
+ case 0x50: /* Z matches f(?) bit */
+ if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
+ EOP_TST_IMM(6, 0, 4);
+ return f ? A_COND_NE : A_COND_EQ;
+ case 0x70: /* N matches f(?) bit */
+ if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
+ EOP_TST_IMM(6, 0, 8);
+ return f ? A_COND_NE : A_COND_EQ;
+ default:
+ elprintf(EL_ANOMALY, "unimplemented cond?\n");
+ tr_unhandled();
+ return 0;
+ }
+}
+
+static int tr_neg_cond(int cond)
+{
+ switch (cond) {
+ case A_COND_AL: elprintf(EL_ANOMALY, "neg for AL?\n"); exit(1);
+ case A_COND_EQ: return A_COND_NE;
+ case A_COND_NE: return A_COND_EQ;
+ case A_COND_MI: return A_COND_PL;
+ case A_COND_PL: return A_COND_MI;
+ default: elprintf(EL_ANOMALY, "bad cond for neg\n"); exit(1);
+ }
+ return 0;
+}
+
+static int tr_aop_ssp2arm(int op)
+{
+ switch (op) {
+ case 1: return A_OP_SUB;
+ case 3: return A_OP_CMP;
+ case 4: return A_OP_ADD;
+ case 5: return A_OP_AND;
+ case 6: return A_OP_ORR;
+ case 7: return A_OP_EOR;