+/* update P, if needed. Trashes r1 */
+static void tr_flush_dirty_P(void)
+{
+ // TODO: const regs
+ if (!(dirty_regb & KRREG_P)) return;
+ EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
+ EOP_MOV_REG_LSL( 1, 4, 16); // mov r1, r4, lsl #16
+ EOP_MOV_REG_ASR( 1, 1, 15); // mov r1, r1, asr #15
+ EOP_MUL(10, 1, 10); // mul r10, r1, r10
+ dirty_regb &= ~KRREG_P;
+}
+
+/* write dirty r0-r7 to host regs. Nothing is trashed */
+static void tr_flush_dirty_pr(void)
+{
+ int i, ror = 0, reg;
+ int dirty = dirty_regb >> 8;
+ /* r0-r7 */
+ for (i = 0; dirty && i < 8; i++, dirty >>= 1)
+ {
+ if (!(dirty&1)) continue;
+ switch (i&3) {
+ case 0: ror = 0; break;
+ case 1: ror = 24/2; break;
+ case 2: ror = 16/2; break;
+ }
+ reg = (i < 4) ? 8 : 9;
+ EOP_BIC_IMM(reg,reg,ror,0xff);
+ if (known_regs.r[i] != 0)
+ EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
+ }
+ dirty_regb &= ~0xff00;
+}
+
+/* fush ARM PSR to r6. Trashes r0 */
+static void tr_flush_dirty_ST(void)
+{
+ if (!(dirty_regb & KRREG_ST)) return;
+ EOP_BIC_IMM(6,6,0,0x0f);
+ EOP_MRS(0);
+ EOP_ORR_REG_LSR(6,6,0,28);
+ dirty_regb &= ~KRREG_ST;
+ hostreg_r[0] = -1;
+}
+
+/* load 16bit val into host reg r0-r3. Nothing is trashed */
+static void tr_mov16(int r, int val)
+{
+ if (hostreg_r[r] != val) {
+ emit_mov_const(A_COND_AL, r, val);
+ hostreg_r[r] = val;
+ }
+}
+
+static void tr_mov16_cond(int cond, int r, int val)
+{
+ emit_mov_const(cond, r, val);
+ hostreg_r[r] = -1;
+}
+
+/* read bank word to r0. Thrashes r1. */
+static void tr_bank_read(int addr) /* word addr 0-0x1ff */
+{
+ int breg = 7;
+ if (addr > 0x7f) {
+ if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
+ EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
+ hostreg_r[1] = 0x100000|((addr&0x180)<<1);
+ }
+ breg = 1;
+ }
+ EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
+ hostreg_r[0] = -1;
+}
+
+/* write r0 to bank. Trashes r1. */
+static void tr_bank_write(int addr)
+{
+ int breg = 7;
+ if (addr > 0x7f) {
+ if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
+ EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
+ hostreg_r[1] = 0x100000|((addr&0x180)<<1);
+ }
+ breg = 1;
+ }
+ EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
+}
+
+/* handle RAM bank pointer modifiers. Nothing is trashed. */
+static void tr_ptrr_mod(int r, int mod, int need_modulo)
+{
+ int modulo_shift = -1; /* unknown */
+
+ if (mod == 0) return;
+
+ if (!need_modulo || mod == 1) // +!
+ modulo_shift = 8;
+ else if (need_modulo && (known_regb & KRREG_ST)) {
+ modulo_shift = known_regs.gr[SSP_ST].h & 7;
+ if (modulo_shift == 0) modulo_shift = 8;
+ }
+
+ if (mod > 1 && modulo_shift == -1) {
+/* TODO
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
+ EOP_MOV_REG_ROR(reg,reg,ror);
+ // {add|sub} reg, reg, #1<<shift
+ EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
+ EOP_MOV_REG_ROR(reg,reg,32-ror);
+*/
+
+ printf("need var modulo\n"); exit(1);
+ }
+ else if (known_regb & (1 << (r + 8)))
+ {
+ int modulo = (1 << modulo_shift) - 1;
+ if (mod == 2)
+ known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - 1) & modulo);
+ else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + 1) & modulo);
+ }
+ else
+ {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
+ EOP_MOV_REG_ROR(reg,reg,ror);
+ // {add|sub} reg, reg, #1<<shift
+ EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, 1<<(8 - modulo_shift));
+ EOP_MOV_REG_ROR(reg,reg,32-ror);
+ }
+}
+
+/* handle writes r0 to (rX). Trashes r1.
+ * fortunately we can ignore modulo increment modes for writes. */
+static void tr_rX_write1(int op)
+{
+ if ((op&3) == 3)
+ {
+ int mod = (op>>2) & 3; // direct addressing
+ tr_bank_write((op & 0x100) + mod);
+ }
+ else
+ {
+ int r = (op&3) | ((op>>6)&4);
+ if (known_regb & (1 << (r + 8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ tr_ptrr_mod(r, (op>>2) & 3, 0);
+ }
+}
+
+/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
+static int tr_cond_check(int op)
+{
+ int f = op & 0x100;
+ switch (op&0xf0) {
+ case 0x00: return A_COND_AL; /* always true */
+ case 0x50: /* Z matches f(?) bit */
+ if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
+ EOP_TST_IMM(6, 0, 4);
+ return f ? A_COND_NE : A_COND_EQ;
+ case 0x70: /* N matches f(?) bit */
+ if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
+ EOP_TST_IMM(6, 0, 8);
+ return f ? A_COND_NE : A_COND_EQ;
+ default:
+ printf("unimplemented cond?\n");
+ exit(1);
+ return 0;
+ }
+}
+
+static int tr_neg_cond(int cond)
+{
+ switch (cond) {
+ case A_COND_AL: printf("neg for AL?\n"); exit(1);
+ case A_COND_EQ: return A_COND_NE;
+ case A_COND_NE: return A_COND_EQ;
+ case A_COND_MI: return A_COND_PL;
+ case A_COND_PL: return A_COND_MI;
+ default: printf("bad cond for neg\n"); exit(1);
+ }
+ return 0;
+}
+
+// SSP_GR0, SSP_X, SSP_Y, SSP_A,
+// SSP_ST, SSP_STACK, SSP_PC, SSP_P,
+//@ r4: XXYY
+//@ r5: A
+//@ r6: STACK and emu flags
+//@ r7: SSP context
+//@ r10: P
+
+// read general reg to r0. Trashes r1
+static void tr_GR0_to_r0(void)
+{
+ tr_mov16(0, 0xffff);
+}
+
+static void tr_X_to_r0(void)
+{
+ if (hostreg_r[0] != (SSP_X<<16)) {
+ EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
+ hostreg_r[0] = SSP_X<<16;
+ }
+}
+
+static void tr_Y_to_r0(void)
+{
+ // TODO..
+ if (hostreg_r[0] != (SSP_Y<<16)) {
+ EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
+ hostreg_r[0] = SSP_Y<<16;
+ }
+}
+
+static void tr_A_to_r0(void)
+{
+ if (hostreg_r[0] != (SSP_A<<16)) {
+ EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
+ hostreg_r[0] = SSP_A<<16;
+ }
+}
+
+static void tr_ST_to_r0(void)
+{
+ // VR doesn't need much accuracy here..
+ EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
+ EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
+ hostreg_r[0] = -1;
+}
+
+static void tr_STACK_to_r0(void)
+{
+ // 448
+ EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
+ EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
+ EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
+ EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
+ EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
+ hostreg_r[0] = hostreg_r[1] = -1;
+}
+
+static void tr_PC_to_r0(void)
+{
+ tr_mov16(0, known_regs.gr[SSP_PC].h);
+}
+
+static void tr_P_to_r0(void)
+{
+ tr_flush_dirty_P();
+ EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
+ hostreg_r[0] = -1;
+}
+
+typedef void (tr_read_func)(void);
+
+static tr_read_func *tr_read_funcs[8] =
+{
+ tr_GR0_to_r0,
+ tr_X_to_r0,
+ tr_Y_to_r0,
+ tr_A_to_r0,
+ tr_ST_to_r0,
+ tr_STACK_to_r0,
+ tr_PC_to_r0,
+ tr_P_to_r0
+};
+
+
+// write r0 to general reg handlers. Trashes r1
+static void tr_unhandled(void)
+{
+ printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
+ exit(1);
+}
+
+static void tr_r0_to_GR0(void)
+{
+ // do nothing
+}
+
+static void tr_r0_to_X(void)
+{
+ EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
+ EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
+ EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
+ dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
+ hostreg_r[0] = SSP_X<<16;
+}
+
+static void tr_r0_to_Y(void)
+{
+ EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
+ EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
+ EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
+ dirty_regb |= KRREG_P;
+ hostreg_r[0] = SSP_Y<<16;
+}
+
+static void tr_r0_to_A(void)
+{
+ EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
+ EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
+ EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
+ hostreg_r[0] = SSP_A<<16;
+}
+
+static void tr_r0_to_ST(void)
+{
+ // VR doesn't need much accuracy here..
+ EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
+ EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
+ EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
+ hostreg_r[1] = -1;
+}
+
+static void tr_r0_to_STACK(void)
+{
+ // 448
+ EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
+ EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
+ EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
+ EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
+ EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
+ hostreg_r[1] = -1;
+}
+
+static void tr_r0_to_PC(void)
+{
+ EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
+ EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
+ hostreg_r[1] = -1;
+}
+
+typedef void (tr_write_func)(void);
+
+static tr_write_func *tr_write_funcs[8] =
+{
+ tr_r0_to_GR0,
+ tr_r0_to_X,
+ tr_r0_to_Y,
+ tr_r0_to_A,
+ tr_r0_to_ST,
+ tr_r0_to_STACK,
+ tr_r0_to_PC,
+ tr_unhandled
+};
+
+
+static int translate_op(unsigned int op, int *pc, int imm)
+{
+ u32 tmpv, tmpv2;
+ int ret = 0;
+ known_regs.gr[SSP_PC].h = *pc;
+
+ switch (op >> 9)
+ {
+ // ld d, s
+ case 0x00:
+ if (op == 0) { ret++; break; } // nop
+ tmpv = op & 0xf; // src
+ tmpv2 = (op >> 4) & 0xf; // dst
+ if (tmpv >= 8 || tmpv2 >= 8) return -1; // TODO
+ if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
+ tr_flush_dirty_P();
+ EOP_MOV_REG_SIMPLE(5, 10);
+ known_regb &= ~(KRREG_A|KRREG_AL);
+ ret++; break;
+ }
+ tr_read_funcs[tmpv]();
+ tr_write_funcs[tmpv2]();
+ if (known_regb & (1 << tmpv)) {
+ known_regs.gr[tmpv2].h = known_regs.gr[tmpv].h;
+ known_regb |= 1 << tmpv2;
+ } else
+ known_regb &= ~(1 << tmpv2);
+ ret++; break;
+
+ // ld d, (ri)
+ //case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
+
+ // ld (ri), s
+ case 0x02:
+ tmpv = (op >> 4) & 0xf; // src
+ if (tmpv >= 8) return -1; // TODO
+ tr_read_funcs[tmpv]();
+ tr_rX_write1(op);
+ ret++; break;
+
+ // ld a, adr
+ case 0x03:
+ tr_bank_read(op&0x1ff);
+ tr_r0_to_A();
+ known_regb &= ~KRREG_A;
+ hostreg_r[0] = SSP_A<<16;
+ ret++; break;
+
+ // ldi d, imm
+ case 0x04:
+ tmpv = (op & 0xf0) >> 4;
+ if (tmpv < 8)
+ {
+ tr_mov16(0, imm);
+ tr_write_funcs[tmpv]();
+ known_regs.gr[tmpv].h = imm;
+ known_regb |= 1 << tmpv;
+ ret += 2; break;
+ }
+ else if (tmpv == 0xe && (PROGRAM(*pc) >> 9) == 4)
+ {
+ // programming PMC..
+ (*pc)++;
+ tmpv = imm | (PROGRAM((*pc)++) << 16);
+ ret += 2;
+ emit_mov_const(A_COND_AL, 0, tmpv);
+ EOP_LDR_IMM(1,7,0x484); // ldr r0, [r7, #0x484] // emu_status
+ EOP_STR_IMM(0,7,0x400+14*4); // PMC
+ // reads on fe06, fe08; next op is ld -,
+ if ((tmpv == 0x187f03 || tmpv == 0x187f04) && (PROGRAM(*pc) & 0xfff0) == 0)
+ {
+ int flag = (tmpv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
+ tr_flush_dirty_ST();
+ EOP_LDR_IMM(0,7,0x490); // dram_ptr
+ EOP_ADD_IMM(0,0,24/2,0xfe); // add r0, r0, #0xfe00
+ EOP_LDRH_IMM(0,0,8); // ldrh r0, [r0, #8]
+ EOP_TST_REG_SIMPLE(0,0);
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ADD,0,11,11,22/2,1); // add r11, r11, #1024
+ EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orr r1, r1, #SSP_WAIT_30FE08
+ }
+ EOP_ORR_IMM(1,1,0,SSP_PMC_SET); // orr r1, r1, #SSP_PMC_SET
+ EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
+ hostreg_r[0] = hostreg_r[1] = -1;
+ ret += 2; break;
+ }
+ else
+ return -1; /* TODO.. */
+
+ // ld d, ((ri))
+ case 0x05: {
+ int r;
+ r = (op&3) | ((op>>6)&4); // src
+ tmpv2 = (op >> 4) & 0xf; // dst
+ if (tmpv2 >= 8) return -1; // TODO
+
+ if ((r&3) == 3) {
+ tr_bank_read((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_read((op&0x100) | known_regs.r[r]);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
+ if (r >= 4)
+ EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
+ if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
+ else EOP_ADD_REG_LSL(1,7,1,1);
+ EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
+ }
+ EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
+ EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
+ EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
+ if ((r&3) == 3) {
+ tr_bank_write((op&0x100) | ((op>>2)&3));
+ } else if (known_regb & (1 << (r+8))) {
+ tr_bank_write((op&0x100) | known_regs.r[r]);
+ } else {
+ EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
+ hostreg_r[1] = -1;
+ }
+ EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r0]
+ hostreg_r[0] = hostreg_r[2] = -1;
+ known_regb &= ~(1 << tmpv2);
+ tr_write_funcs[tmpv2]();
+ ret += 3; break; /* should certainly take > 1 */
+ }
+
+ // ldi (ri), imm
+ case 0x06:
+ tr_mov16(0, imm);
+ tr_rX_write1(op);
+ ret += 2; break;
+
+ // ld adr, a
+ case 0x07:
+ if (hostreg_r[0] != (SSP_A<<16)) {
+ EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ A
+ hostreg_r[0] = SSP_A<<16;
+ }
+ tr_bank_write(op&0x1ff);
+ ret++; break;
+
+ // ld d, ri
+ case 0x09: {
+ int r;
+ r = (op&3) | ((op>>6)&4); // src
+ tmpv2 = (op >> 4) & 0xf; // dst
+ if (tmpv2 >= 8) tr_unhandled();
+ if ((r&3) == 3) tr_unhandled();
+
+ if (known_regb & (1 << (r+8))) {
+ tr_mov16(0, known_regs.r[r]);
+ known_regs.gr[tmpv2].h = known_regs.r[r];
+ known_regb |= 1 << tmpv2;
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
+ EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
+ hostreg_r[0] = -1;
+ known_regb &= ~(1 << tmpv2);
+ }
+ tr_write_funcs[tmpv2]();
+ ret++; break;
+ }
+
+ // ld ri, s
+ case 0x0a: {
+ int r;
+ r = (op&3) | ((op>>6)&4); // dst
+ tmpv = (op >> 4) & 0xf; // src
+ if (tmpv >= 8) tr_unhandled();
+ if ((r&3) == 3) tr_unhandled();
+
+ if (known_regb & (1 << tmpv)) {
+ known_regs.r[r] = known_regs.gr[tmpv].h;
+ known_regb |= 1 << (r + 8);
+ dirty_regb |= 1 << (r + 8);
+ } else {
+ int reg = (r < 4) ? 8 : 9;
+ int ror = ((4 - (r&3))*8) & 0x1f;
+ tr_read_funcs[tmpv]();
+ EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
+ EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
+ EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
+ hostreg_r[0] = -1;
+ known_regb &= ~(1 << (r+8));
+ dirty_regb &= ~(1 << (r+8));
+ }
+ ret++; break;
+ }
+
+ // ldi ri, simm
+ case 0x0c ... 0x0f:
+ tmpv = (op>>8)&7;
+ known_regs.r[tmpv] = op;
+ known_regb |= 1 << (tmpv + 8);
+ dirty_regb |= 1 << (tmpv + 8);
+ ret++; break;
+
+ // call cond, addr
+ case 0x24:
+ tr_mov16(0, *pc);
+ tr_r0_to_STACK();
+ tmpv = tr_cond_check(op);
+ tr_mov16_cond(tmpv, 0, imm);
+ if (tmpv != A_COND_AL) {
+ tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
+ }
+ tr_r0_to_PC();
+ ret += 2; break;
+
+ // ld d, (a)
+ case 0x25:
+ tmpv2 = (op >> 4) & 0xf; // dst
+ if (tmpv2 >= 8) return -1; // TODO
+
+ tr_A_to_r0();
+ EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
+ EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
+ EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
+ hostreg_r[0] = hostreg_r[1] = -1;
+ known_regb &= ~(1 << tmpv2);
+ tr_write_funcs[tmpv2]();
+ ret += 3; break;
+
+ // bra cond, addr
+ case 0x26:
+ tmpv = tr_cond_check(op);
+ tr_mov16_cond(tmpv, 0, imm);
+ if (tmpv != A_COND_AL) {
+ tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
+ }
+ tr_r0_to_PC();
+ ret += 2; break;
+
+
+/*
+ // mpys?
+ case 0x1b:
+ read_P(); // update P
+ rA32 -= rP.v; // maybe only upper word?
+ UPD_ACC_ZN // there checking flags after this
+ rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
+ rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+ break;
+
+ // mpya (rj), (ri), b
+ case 0x4b:
+ read_P(); // update P
+ rA32 += rP.v; // confirmed to be 32bit
+ UPD_ACC_ZN // ?
+ rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
+ rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
+ break;
+
+ // mld (rj), (ri), b
+ case 0x5b:
+ EOP_MOV_IMM(5, 0, 0); // mov r5, #0
+ known_regs.r[SSP_A].v = 0;
+ known_regb |= (KRREG_A|KRREG_AL);
+ EOP_BIC_IMM(6, 6, 0, 0x0f); // bic r6, r6, 0xf // flags
+ EOP_BIC_IMM(6, 6, 0, 0x04); // bic r6, r6, 4 // set Z
+ // TODO
+ ret++; break;
+*/
+ }
+
+ return ret;
+}
+