+#define rA32 ssp->gr[SSP_A].v
+#define rIJ ssp->r
+
+#define IJind (((op>>6)&4)|(op&3))
+
+#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
+#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
+#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
+
+#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
+#define REG_WRITE(r,d) { \
+ int r1 = r; \
+ if (r1 >= 4) write_handlers[r1](d); \
+ else if (r1 > 0) ssp->gr[r1].h = d; \
+}
+
+// flags
+#define SSP_FLAG_L (1<<0xc)
+#define SSP_FLAG_Z (1<<0xd)
+#define SSP_FLAG_V (1<<0xe)
+#define SSP_FLAG_N (1<<0xf)
+
+// update ZN according to 32bit ACC.
+#define UPD_ACC_ZN \
+ rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
+ if (!rA32) rST |= SSP_FLAG_Z; \
+ else rST |= (rA32>>16)&SSP_FLAG_N;
+
+// it seems SVP code never checks for L and OV, so we leave them out.
+// rST |= (t>>4)&SSP_FLAG_L;
+#define UPD_LZVN \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!rA32) rST |= SSP_FLAG_Z; \
+ else rST |= (rA32>>16)&SSP_FLAG_N;
+
+// standard cond processing.
+// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
+#define COND_CHECK \
+ switch (op&0xf0) { \
+ case 0x00: cond = 1; break; /* always true */ \
+ case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
+ case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
+ default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
+ }
+
+// ops with accumulator.
+// how is low word really affected by these?
+// nearly sure 'ld A' doesn't affect flags
+#define OP_LDA(x) \
+ ssp->gr[SSP_A].h = x
+
+#define OP_LDA32(x) \
+ rA32 = x
+
+#define OP_SUBA(x) { \
+ rA32 -= (x) << 16; \
+ UPD_LZVN \
+}
+
+#define OP_SUBA32(x) { \
+ rA32 -= (x); \
+ UPD_LZVN \
+}
+
+#define OP_CMPA(x) { \
+ u32 t = rA32 - ((x) << 16); \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!t) rST |= SSP_FLAG_Z; \
+ else rST |= (t>>16)&SSP_FLAG_N; \
+}
+
+#define OP_CMPA32(x) { \
+ u32 t = rA32 - (x); \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!t) rST |= SSP_FLAG_Z; \
+ else rST |= (t>>16)&SSP_FLAG_N; \
+}
+
+#define OP_ADDA(x) { \
+ rA32 += (x) << 16; \
+ UPD_LZVN \
+}
+
+#define OP_ADDA32(x) { \
+ rA32 += (x); \
+ UPD_LZVN \
+}
+
+#define OP_ANDA(x) \
+ rA32 &= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_ANDA32(x) \
+ rA32 &= (x); \
+ UPD_ACC_ZN
+
+#define OP_ORA(x) \
+ rA32 |= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_ORA32(x) \
+ rA32 |= (x); \
+ UPD_ACC_ZN
+
+#define OP_EORA(x) \
+ rA32 ^= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_EORA32(x) \
+ rA32 ^= (x); \
+ UPD_ACC_ZN
+
+
+#define OP_CHECK32(OP) \
+ if ((op & 0x0f) == SSP_P) { /* A <- P */ \
+ read_P(); /* update P */ \
+ OP(ssp->gr[SSP_P].v); \
+ break; \
+}
+
+
+static ssp1601_t *ssp = NULL;
+static unsigned short *PC;
+static int g_cycles;
+
+#ifdef USE_DEBUGGER
+static int running = 0;
+static int last_iram = 0;
+#endif
+
+// -----------------------------------------------------
+// register i/o handlers
+
+// 0-4, 13
+static u32 read_unknown(void)
+{
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
+ return 0;
+}
+
+static void write_unknown(u32 d)
+{
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
+}
+
+// 4
+static void write_ST(u32 d)
+{
+ //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
+ if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
+ rST = d;
+}
+
+// 5
+static u32 read_STACK(void)
+{
+ --rSTACK;
+ if ((short)rSTACK < 0) {
+ rSTACK = 5;
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ }
+ return ssp->stack[rSTACK];
+}
+
+static void write_STACK(u32 d)
+{
+ if (rSTACK >= 6) {
+ elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ rSTACK = 0;
+ }
+ ssp->stack[rSTACK++] = d;
+}
+
+// 6
+static u32 read_PC(void)
+{
+ return GET_PC();
+}
+
+static void write_PC(u32 d)
+{
+ SET_PC(d);
+ g_cycles--;
+}
+
+// 7
+static u32 read_P(void)
+{
+ int m1 = (signed short)rX;
+ int m2 = (signed short)rY;
+ rP.v = (m1 * m2 * 2);
+ return rP.h;
+}
+
+// -----------------------------------------------------
+
+static int get_inc(int mode)
+{
+ int inc = (mode >> 11) & 7;
+ if (inc != 0) {
+ if (inc != 7) inc--;
+ inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
+ if (mode & 0x8000) inc = -inc; // decrement mode
+ }
+ return inc;
+}
+
+#define overwite_write(dst, d) \
+{ \
+ if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
+ if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
+ if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
+ if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
+}
+
+static u32 pm_io(int reg, int write, u32 d)
+{
+ if (ssp->emu_status & SSP_PMC_SET)
+ {
+ // this MUST be blind r or w
+ if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
+ reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
+ ssp->emu_status &= ~SSP_PMC_SET;
+ return 0;
+ }
+ elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
+ ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
+ ssp->emu_status &= ~SSP_PMC_SET;
+ if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
+ elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
+#ifdef USE_DEBUGGER
+ last_iram = (ssp->RAM1[0]-1)<<1;
+#endif
+ }
+ return 0;
+ }
+
+ // just in case
+ if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
+ reg, write ? 'w' : 'r', GET_PPC_OFFS());
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ }
+
+ if (reg == 4 || (rST & 0x60))
+ {
+ #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
+ unsigned short *dram = (unsigned short *)svp->dram;
+ if (write)
+ {
+ int mode = ssp->pmac_write[reg]&0xffff;
+ int addr = ssp->pmac_write[reg]>>16;
+ if ((mode & 0xb800) == 0xb800)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
+ if ((mode & 0x43ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
+ reg, CADDR, d, inc >> 16, (mode>>10)&1);
+ if (mode & 0x0400) {
+ overwite_write(dram[addr], d);
+ } else dram[addr] = d;
+ ssp->pmac_write[reg] += inc;
+ }
+ else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
+ {
+ elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
+ reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
+ if (mode & 0x0400) {
+ overwite_write(dram[addr], d);
+ } else dram[addr] = d;
+ ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
+ }
+ else if ((mode & 0x47ff) == 0x001c) // IRAM
+ {
+ int inc = get_inc(mode);
+ if ((addr&0xfc00) != 0x8000)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
+ elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
+ ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
+ ssp->pmac_write[reg] += inc;
+ }
+ else
+ {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
+ reg, mode, CADDR, d, GET_PPC_OFFS());
+ }
+ }
+ else
+ {
+ int mode = ssp->pmac_read[reg]&0xffff;
+ int addr = ssp->pmac_read[reg]>>16;
+ if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
+ {
+ elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
+ ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
+ if ((signed int)ssp->pmac_read[reg] >> 16 == -1)
+ ssp->pmac_read[reg]++;
+ ssp->pmac_read[reg] += 1<<16;
+ d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
+ }
+ else if ((mode & 0x47ff) == 0x0018) // DRAM
+ {
+ int inc = get_inc(mode);
+ elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
+ d = dram[addr];
+ ssp->pmac_read[reg] += inc;
+ }
+ else
+ {
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
+ reg, mode, CADDR, GET_PPC_OFFS());
+ d = 0;
+ }
+ }
+
+ // PMC value corresponds to last PMR accessed (not sure).
+ rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
+
+ return d;
+ }
+
+ return (u32)-1;
+}
+
+// 8
+static u32 read_PM0(void)
+{
+ u32 d = pm_io(0, 0, 0);
+ if (d != (u32)-1) return d;
+ elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
+ d = rPM0;
+ if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
+ ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
+ }
+ rPM0 &= ~2; // ?
+ return d;
+}
+
+static void write_PM0(u32 d)
+{
+ u32 r = pm_io(0, 1, d);
+ if (r != (u32)-1) return;
+ elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM0 = d;
+}
+
+// 9
+static u32 read_PM1(void)
+{
+ u32 d = pm_io(1, 0, 0);
+ if (d != (u32)-1) return d;
+ // can be removed?
+ elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
+ return rPM1;
+}
+
+static void write_PM1(u32 d)
+{
+ u32 r = pm_io(1, 1, d);
+ if (r != (u32)-1) return;
+ // can be removed?
+ elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM1 = d;
+}
+
+// 10
+static u32 read_PM2(void)
+{
+ u32 d = pm_io(2, 0, 0);
+ if (d != (u32)-1) return d;
+ // can be removed?
+ elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
+ return rPM2;
+}
+
+static void write_PM2(u32 d)
+{
+ u32 r = pm_io(2, 1, d);
+ if (r != (u32)-1) return;
+ // can be removed?
+ elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM2 = d;
+}
+
+// 11
+static u32 read_XST(void)
+{
+ // can be removed?
+ u32 d = pm_io(3, 0, 0);
+ if (d != (u32)-1) return d;
+
+ elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
+ return rXST;
+}
+
+static void write_XST(u32 d)
+{
+ // can be removed?
+ u32 r = pm_io(3, 1, d);
+ if (r != (u32)-1) return;
+
+ elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM0 |= 1;
+ rXST = d;
+}
+
+// 12
+static u32 read_PM4(void)
+{
+ u32 d = pm_io(4, 0, 0);
+ if (d == 0) {
+ switch (GET_PPC_OFFS()) {
+ case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
+ case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
+ }
+ }
+ if (d != (u32)-1) return d;
+ // can be removed?
+ elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
+ return rPM4;
+}
+
+static void write_PM4(u32 d)
+{
+ u32 r = pm_io(4, 1, d);
+ if (r != (u32)-1) return;
+ // can be removed?
+ elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM4 = d;
+}
+
+// 14
+static u32 read_PMC(void)
+{
+ elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
+ (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
+ if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
+ //if (ssp->emu_status & SSP_PMC_SET)
+ // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ ssp->emu_status |= SSP_PMC_SET;
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ } else {
+ ssp->emu_status |= SSP_PMC_HAVE_ADDR;
+ }
+ return rPMC.h;
+}
+
+static void write_PMC(u32 d)
+{
+ if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
+ //if (ssp->emu_status & SSP_PMC_SET)
+ // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ ssp->emu_status |= SSP_PMC_SET;
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ rPMC.l = d;
+ elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
+ } else {
+ ssp->emu_status |= SSP_PMC_HAVE_ADDR;
+ rPMC.h = d;
+ elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
+ }
+}
+
+// 15
+static u32 read_AL(void)
+{
+ if (*(PC-1) == 0x000f) {
+ elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
+ ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
+ }
+ return rAL;
+}
+
+static void write_AL(u32 d)
+{
+ rAL = d;
+}
+
+
+typedef u32 (*read_func_t)(void);
+typedef void (*write_func_t)(u32 d);
+
+static read_func_t read_handlers[16] =
+{
+ read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
+ read_unknown, // 4 ST
+ read_STACK,
+ read_PC,
+ read_P,
+ read_PM0, // 8
+ read_PM1,
+ read_PM2,
+ read_XST,
+ read_PM4, // 12
+ read_unknown, // 13 gr13
+ read_PMC,
+ read_AL
+};
+
+static write_func_t write_handlers[16] =
+{
+ write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
+// write_unknown, // 4 ST
+ write_ST, // 4 ST (debug hook)
+ write_STACK,
+ write_PC,
+ write_unknown, // 7 P
+ write_PM0, // 8
+ write_PM1,
+ write_PM2,
+ write_XST,
+ write_PM4, // 12
+ write_unknown, // 13 gr13
+ write_PMC,
+ write_AL
+};
+
+// -----------------------------------------------------
+// pointer register handlers
+
+//
+#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
+
+static u32 ptr1_read_(int ri, int isj2, int modi3)
+{
+ //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
+ u32 mask, add = 0, t = ri | isj2 | modi3;
+ unsigned char *rp = NULL;
+ switch (t)
+ {
+ // mod=0 (00)
+ case 0x00:
+ case 0x01:
+ case 0x02: return ssp->RAM0[ssp->r0[t&3]];
+ case 0x03: return ssp->RAM0[0];
+ case 0x04:
+ case 0x05:
+ case 0x06: return ssp->RAM1[ssp->r1[t&3]];
+ case 0x07: return ssp->RAM1[0];
+ // mod=1 (01), "+!"
+ case 0x08:
+ case 0x09:
+ case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
+ case 0x0b: return ssp->RAM0[1];
+ case 0x0c:
+ case 0x0d:
+ case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
+ case 0x0f: return ssp->RAM1[1];
+ // mod=2 (10), "-"
+ case 0x10:
+ case 0x11:
+ case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
+ if (!(rST&7)) { (*rp)--; return t; }
+ add = -1; goto modulo;
+ case 0x13: return ssp->RAM0[2];
+ case 0x14:
+ case 0x15:
+ case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
+ if (!(rST&7)) { (*rp)--; return t; }
+ add = -1; goto modulo;
+ case 0x17: return ssp->RAM1[2];
+ // mod=3 (11), "+"
+ case 0x18:
+ case 0x19:
+ case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
+ if (!(rST&7)) { (*rp)++; return t; }
+ add = 1; goto modulo;
+ case 0x1b: return ssp->RAM0[3];
+ case 0x1c:
+ case 0x1d:
+ case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
+ if (!(rST&7)) { (*rp)++; return t; }
+ add = 1; goto modulo;
+ case 0x1f: return ssp->RAM1[3];
+ }
+
+ return 0;
+
+modulo:
+ mask = (1 << (rST&7)) - 1;
+ *rp = (*rp & ~mask) | ((*rp + add) & mask);
+ return t;
+}
+
+static void ptr1_write(int op, u32 d)
+{
+ int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
+ switch (t)
+ {
+ // mod=0 (00)
+ case 0x00:
+ case 0x01:
+ case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
+ case 0x03: ssp->RAM0[0] = d; return;
+ case 0x04:
+ case 0x05:
+ case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
+ case 0x07: ssp->RAM1[0] = d; return;
+ // mod=1 (01), "+!"
+ // mod=3, "+"
+ case 0x08:
+ case 0x18:
+ case 0x09:
+ case 0x19:
+ case 0x0a:
+ case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
+ case 0x0b: ssp->RAM0[1] = d; return;
+ case 0x0c:
+ case 0x1c:
+ case 0x0d:
+ case 0x1d:
+ case 0x0e:
+ case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
+ case 0x0f: ssp->RAM1[1] = d; return;
+ // mod=2 (10), "-"
+ case 0x10:
+ case 0x11:
+ case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
+ case 0x13: ssp->RAM0[2] = d; return;
+ case 0x14:
+ case 0x15:
+ case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
+ case 0x17: ssp->RAM1[2] = d; return;
+ // mod=3 (11)
+ case 0x1b: ssp->RAM0[3] = d; return;
+ case 0x1f: ssp->RAM1[3] = d; return;
+ }
+}
+
+static u32 ptr2_read(int op)
+{
+ int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
+ switch (t)
+ {
+ // mod=0 (00)
+ case 0x00:
+ case 0x01:
+ case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
+ case 0x03: mv = ssp->RAM0[0]++; break;
+ case 0x04:
+ case 0x05:
+ case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
+ case 0x07: mv = ssp->RAM1[0]++; break;
+ // mod=1 (01)
+ case 0x0b: mv = ssp->RAM0[1]++; break;
+ case 0x0f: mv = ssp->RAM1[1]++; break;
+ // mod=2 (10)
+ case 0x13: mv = ssp->RAM0[2]++; break;
+ case 0x17: mv = ssp->RAM1[2]++; break;
+ // mod=3 (11)
+ case 0x1b: mv = ssp->RAM0[3]++; break;
+ case 0x1f: mv = ssp->RAM1[3]++; break;
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
+ return 0;
+ }
+
+ return ((unsigned short *)svp->iram_rom)[mv];
+}