+#define rA32 ssp->gr[SSP_A].v
+#define rIJ ssp->r
+
+#define IJind (((op>>6)&4)|(op&3))
+
+#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
+#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
+#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
+
+#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
+#define REG_WRITE(r,d) { \
+ int r1 = r; \
+ if (r1 >= 4) write_handlers[r1](d); \
+ else if (r1 > 0) ssp->gr[r1].h = d; \
+}
+
+// flags
+#define SSP_FLAG_L (1<<0xc)
+#define SSP_FLAG_Z (1<<0xd)
+#define SSP_FLAG_V (1<<0xe)
+#define SSP_FLAG_N (1<<0xf)
+
+// update ZN according to 32bit ACC.
+#define UPD_ACC_ZN \
+ rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
+ if (!rA32) rST |= SSP_FLAG_Z; \
+ else rST |= (rA32>>16)&SSP_FLAG_N;
+
+// it seems SVP code never checks for L and OV, so we leave them out.
+// rST |= (t>>4)&SSP_FLAG_L;
+#define UPD_t_LZVN \
+ rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
+ if (!t) rST |= SSP_FLAG_Z; \
+ else rST |= t&SSP_FLAG_N; \
+
+// standard cond processing.
+// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
+#define COND_CHECK \
+ switch (op&0xf0) { \
+ case 0x00: cond = 1; break; /* always true */ \
+ case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
+ case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
+ default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
+ }
+
+// ops with accumulator.
+// how is low word really affected by these?
+// nearly sure 'ld A' doesn't affect flags
+#define OP_LDA(x) \
+ ssp->gr[SSP_A].h = x
+
+#define OP_SUBA(x) { \
+ u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
+ UPD_t_LZVN \
+ ssp->gr[SSP_A].h = t; \
+}
+
+#define OP_CMPA(x) { \
+ u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
+ UPD_t_LZVN \
+}
+
+#define OP_ADDA(x) { \
+ u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
+ UPD_t_LZVN \
+ ssp->gr[SSP_A].h = t; \
+}
+
+#define OP_ANDA(x) \
+ ssp->gr[SSP_A].v &= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_ORA(x) \
+ ssp->gr[SSP_A].v |= (x) << 16; \
+ UPD_ACC_ZN
+
+#define OP_EORA(x) \
+ ssp->gr[SSP_A].v ^= (x) << 16; \
+ UPD_ACC_ZN
+
+
+static ssp1601_t *ssp = NULL;
+static unsigned short *PC;
+static int g_cycles;
+// debug
+static int running = 0;
+static int last_iram = 0;
+
+// -----------------------------------------------------
+// register i/o handlers
+
+// 0-4, 13
+static u32 read_unknown(void)
+{
+ elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
+ return 0;
+}
+
+static void write_unknown(u32 d)
+{
+ elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
+}
+
+// 4
+static void write_ST(u32 d)
+{
+ if ((rST ^ d) & 7) {
+ elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
+// running = 0;
+ }
+ rST = d;
+}
+
+// 5
+static u32 read_STACK(void)
+{
+ //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
+ --rSTACK;
+ if ((short)rSTACK < 0) {
+ rSTACK = 5;
+ elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ }
+ return ssp->stack[rSTACK];
+}
+
+static void write_STACK(u32 d)
+{
+ if (rSTACK >= 6) {
+ running = 0;
+ elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
+ rSTACK = 0;
+ }
+ ssp->stack[rSTACK++] = d;
+}
+
+// 6
+static u32 read_PC(void)
+{
+ return GET_PC();
+}
+
+static void write_PC(u32 d)
+{
+ SET_PC(d);
+ g_cycles--;
+}
+
+// 7
+static u32 read_P(void)
+{
+ rP.v = (u32)rX * rY * 2;
+ return rP.h;
+}
+
+// -----------------------------------------------------
+
+static void iram_write(int addr, u32 d, int reg, int inc)
+{
+ if ((addr&0xfc00) != 0x8000)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
+ elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
+ ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
+ ssp->pmac_write[reg] += inc<<16;
+}
+
+int lil[32] = { 0, }, lilp = 0;
+
+static void debug_dump2file(const char *fname, void *mem, int len);
+
+#define overwite_write(dst, d) \
+{ \
+ if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
+ if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
+ if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
+ if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
+}
+
+static u32 pm_io(int reg, int write, u32 d)
+{
+ if (ssp->emu_status & SSP_PMC_SET) {
+ elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
+ ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
+ ssp->emu_status &= ~SSP_PMC_SET;
+ if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
+ elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
+/*
+ {
+ int i;
+ char buff[64];
+ for (i = 0; i < 32; i++) {
+ if (lil[i] == last_iram) break;
+ if (lil[i] == 0) {
+ lil[i] = last_iram;
+ sprintf(buff, "iramrom_%04x.bin", last_iram);
+ debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
+ break;
+ }
+ }
+ }
+*/
+ last_iram = (ssp->RAM1[0]-1)<<1;
+ }
+ return 0;
+ }
+
+ // just in case
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+
+// if (ssp->pmac_read[reg] != 0)
+ if (reg == 4 || (rST & 0x60))
+ {
+ #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
+ unsigned short *dram = (unsigned short *)svp->dram;
+ if (write)
+ {
+ /* TODO: 0c18 mode? */
+ int mode = ssp->pmac_write[reg]&0xffff;
+ int addr = ssp->pmac_write[reg]>>16;
+ switch (mode) {
+ case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", CADDR, d);
+ dram[addr] = d;
+ break;
+ case 0x0418: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (overwr)", CADDR, d);
+ overwite_write(dram[addr], d);
+ break;
+ case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", CADDR, d);
+ dram[addr] = d;
+ ssp->pmac_write[reg] += 1<<16;
+ break;
+ case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
+ case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
+ case 0x4018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (cell inc)", CADDR, d);
+ dram[addr] = d;
+ ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
+ break;
+ case 0x4418: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (overwr, cell inc)", CADDR, d);
+ overwite_write(dram[addr], d);
+ ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
+ break;
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
+ reg, mode, CADDR, d, GET_PPC_OFFS()); break;
+ }
+ }
+ else
+ {
+ int mode = ssp->pmac_read[reg]&0xffff;
+ int addr = ssp->pmac_read[reg]>>16;
+ if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
+ elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
+ ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
+ ssp->pmac_read[reg] += 1<<16;
+ d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
+ goto ext_io_end;
+ }
+
+ switch (mode) {
+ case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
+ d = dram[addr]; // checked
+ break;
+ case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", CADDR, dram[addr]);
+ ssp->pmac_read[reg] += 1<<16;
+ d = dram[addr];
+ break;
+ case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
+ ssp->pmac_read[reg] += 32<<16;
+ d = dram[addr];
+ break;
+ case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
+ ssp->pmac_read[reg] -= 16<<16;
+ d = dram[addr];
+ break;
+ case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
+ ssp->pmac_read[reg] -= 128<<16;
+ d = dram[addr];
+ break;
+ default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
+ reg, mode, CADDR, GET_PPC_OFFS());
+ d = 0;
+ break;
+ }
+ }
+
+ext_io_end:
+ // PMC value corresponds to last PMR accessed (not sure).
+ rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
+
+ return d;
+ }
+
+ return (u32)-1;
+}
+
+// 8
+static u32 read_PM0(void)
+{
+ u32 d = pm_io(0, 0, 0);
+ if (d != (u32)-1) return d;
+ if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
+ elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
+ d = rPM0;
+ if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
+ ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
+ }
+ rPM0 &= ~2; // ?
+ return d;
+}
+
+static void write_PM0(u32 d)
+{
+ u32 r = pm_io(0, 1, d);
+ if (r != (u32)-1) return;
+ elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM0 = d;
+}
+
+// 9
+static u32 read_PM1(void)
+{
+ u32 d = pm_io(1, 0, 0);
+ if (d != (u32)-1) return d;
+ // can be removed?
+ elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
+ return rPM1;
+}
+
+static void write_PM1(u32 d)
+{
+ u32 r = pm_io(1, 1, d);
+ if (r != (u32)-1) return;
+ // can be removed?
+ elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM1 = d;
+}
+
+// 10
+static u32 read_PM2(void)
+{
+ u32 d = pm_io(2, 0, 0);
+ if (d != (u32)-1) return d;
+ // can be removed?
+ elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
+ return rPM2;
+}
+
+static void write_PM2(u32 d)
+{
+ u32 r = pm_io(2, 1, d);
+ if (r != (u32)-1) return;
+ // can be removed?
+ elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM2 = d;
+}
+
+// 11
+static u32 read_XST(void)
+{
+ // can be removed?
+ u32 d = pm_io(3, 0, 0);
+ if (d != (u32)-1) return d;
+
+ elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
+ return rXST;
+}
+
+static void write_XST(u32 d)
+{
+ // can be removed?
+ u32 r = pm_io(3, 1, d);
+ if (r != (u32)-1) return;
+
+ elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM0 |= 1;
+ rXST = d;
+}
+
+// 12
+static u32 read_PM4(void)
+{
+ u32 d = pm_io(4, 0, 0);
+ if (d == 0) {
+ switch (GET_PPC_OFFS()) {
+ case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
+ case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
+ }
+ }
+ if (d != (u32)-1) return d;
+ // can be removed?
+ elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
+ return rPM4;
+}
+
+static void write_PM4(u32 d)
+{
+ u32 r = pm_io(4, 1, d);
+ if (r != (u32)-1) return;
+ // can be removed?
+ elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
+ rPM4 = d;
+}
+
+// 14
+static u32 read_PMC(void)
+{
+ elprintf(EL_SVP, "PMC r %08x @ %04x", rPMC.v, GET_PPC_OFFS());
+ if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
+ if (ssp->emu_status & SSP_PMC_SET)
+ elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ ssp->emu_status |= SSP_PMC_SET;
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ return rPMC.l;
+ } else {
+ ssp->emu_status |= SSP_PMC_HAVE_ADDR;
+ return rPMC.h;
+ }
+}
+
+static void write_PMC(u32 d)
+{
+ if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
+ if (ssp->emu_status & SSP_PMC_SET)
+ elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
+ ssp->emu_status |= SSP_PMC_SET;
+ ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
+ rPMC.l = d;
+ } else {
+ ssp->emu_status |= SSP_PMC_HAVE_ADDR;
+ rPMC.h = d;
+ }
+}
+
+// 15
+static u32 read_AL(void)
+{
+ // TODO: figure out what's up with those blind reads..
+ if (*(PC-1) == 0x000f)
+ elprintf(EL_SVP|EL_ANOMALY, "ssp unhandled AL blind read..");
+ return rAL;
+}
+
+static void write_AL(u32 d)
+{
+ rAL = d;
+}
+
+
+typedef u32 (*read_func_t)(void);
+typedef void (*write_func_t)(u32 d);
+
+static read_func_t read_handlers[16] =
+{
+ read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
+ read_unknown, // 4 ST
+ read_STACK,
+ read_PC,
+ read_P,
+ read_PM0, // 8
+ read_PM1,
+ read_PM2,
+ read_XST,
+ read_PM4, // 12
+ read_unknown, // 13 gr13
+ read_PMC,
+ read_AL
+};
+
+static write_func_t write_handlers[16] =
+{
+ write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
+// write_unknown, // 4 ST
+ write_ST, // 4 ST (debug hook)
+ write_STACK,
+ write_PC,
+ write_unknown, // 7 P
+ write_PM0, // 8
+ write_PM1,
+ write_PM2,
+ write_XST,
+ write_PM4, // 12
+ write_unknown, // 13 gr13
+ write_PMC,
+ write_AL
+};
+
+// -----------------------------------------------------
+// pointer register handlers