- #define SSP_PMC_HAVE_ADDR 1 // address written to PMAC, waiting for mode
- #define SSP_PMC_SET 2 // PMAC is set
- unsigned int emu_status;
- unsigned int pad[30];
+ #define SSP_PMC_HAVE_ADDR 0x0001 // address written to PMAC, waiting for mode
+ #define SSP_PMC_SET 0x0002 // PMAC is set
+ #define SSP_WAIT_PM0 0x2000 // bit1 in PM0
+ #define SSP_WAIT_30FE06 0x4000 // ssp tight loops on 30FE06 to become non-zero
+ #define SSP_WAIT_30FE08 0x8000 // same for 30FE06
+ #define SSP_WAIT_MASK 0xe000
+ unsigned int emu_status; // 484
+ /* used by recompiler only: */
+ struct {
+ unsigned int ptr_rom; // 488
+ unsigned int ptr_iram_rom; // 48c
+ unsigned int ptr_dram; // 490
+ unsigned int iram_dirty; // 494
+ unsigned int iram_context; // 498
+ unsigned int ptr_btable; // 49c
+ unsigned int ptr_btable_iram; // 4a0
+ unsigned int tmp0; // 4a4
+ unsigned int tmp1; // 4a8
+ unsigned int tmp2; // 4ac
+ } drc;