+ mov r0, #0x400
+ beq ssp_drc_end
+ orrne r0, r0, #0x004
+ b ssp_drc_next
+
+
+.macro hle_flushflags
+ bic r6, r6, #0xf
+ mrs r1, cpsr
+ orr r6, r6, r1, lsr #28
+.endm
+
+.macro hle_popstack
+ sub r6, r6, #0x20000000
+ add r1, r7, #0x400
+ add r1, r1, #0x048 @ stack
+ add r1, r1, r6, lsr #28
+ ldrh r0, [r1]
+.endm
+
+ssp_hle_902:
+ cmp r11, #0
+ ble ssp_drc_end
+
+ add r1, r7, #0x200
+ ldrh r0, [r1]
+ ldr r3, [r7, #SSP_OFFS_IRAM_ROM]
+ add r2, r3, r0, lsl #1 @ (r7|00)
+ ldrh r0, [r2], #2
+ mov r5, r5, lsl #16
+ mov r5, r5, lsr #16
+ bic r0, r0, #0xfc00
+ add r3, r3, r0, lsl #1 @ IRAM dest
+ ldrh r12,[r2], #2 @ length
+ bic r3, r3, #3 @ always seen aligned
+@ orr r5, r5, #0x08000000
+@ orr r5, r5, #0x00880000
+@ sub r5, r5, r12, lsl #16
+ bic r6, r6, #0xf
+ add r12,r12,#1
+ mov r0, #1
+ str r0, [r7, #SSP_OFFS_IRAM_DIRTY]
+ sub r11,r11,r12,lsl #1
+ sub r11,r11,r12 @ -= length*3
+
+ssp_hle_902_loop:
+ ldrh r0, [r2], #2
+ ldrh r1, [r2], #2
+ subs r12,r12,#2
+ orr r0, r0, r1, lsl #16
+ str r0, [r3], #4
+ bgt ssp_hle_902_loop
+
+ tst r12, #1
+ ldrneh r0, [r2], #2
+ strneh r0, [r3], #2
+
+ ldr r0, [r7, #SSP_OFFS_IRAM_ROM]
+ add r1, r7, #0x200
+ sub r2, r2, r0
+ mov r2, r2, lsr #1
+ strh r2, [r1] @ (r7|00)
+
+ sub r0, r3, r0
+ mov r0, r0, lsr #1
+ orr r0, r0, #0x08000000
+ orr r0, r0, #0x001c8000
+ str r0, [r7, #(SSP_OFFS_GR+SSP_PMC*4)]
+ str r0, [r7, #(SSP_OFFS_PM_WRITE+4*4)]
+
+ hle_popstack
+ subs r11,r11,#16 @ timeslice is likely to end
+ ble ssp_drc_end
+ b ssp_drc_next
+
+
+@ this one is car rendering related
+.macro hle_11_12c_mla offs_in
+ ldrsh r5, [r7, #(\offs_in+0)]
+ ldrsh r0, [r7, #(\offs_in+2)]
+ ldrsh r1, [r7, #(\offs_in+4)]
+ mul r5, r2, r5
+ ldrsh r12,[r7, #(\offs_in+6)]
+ mla r5, r3, r0, r5
+ mla r5, r4, r1, r5
+ add r5, r5, r12,lsl #11
+
+ movs r5, r5, lsr #13
+ add r1, r7, r8, lsr #23
+ strh r5, [r1]
+ add r8, r8, #(1<<24)
+.endm
+
+ssp_hle_11_12c:
+ cmp r11, #0
+ ble ssp_drc_end
+
+ mov r0, #0
+ bl ssp_pm_read
+ mov r4, r0
+
+ mov r0, #0
+ bl ssp_pm_read
+ mov r5, r0
+
+ mov r0, #0
+ bl ssp_pm_read
+
+ mov r2, r4, lsl #16
+ mov r2, r2, asr #15 @ (r7|00) << 1
+ mov r3, r5, lsl #16
+ mov r3, r3, asr #15 @ (r7|01) << 1
+ mov r4, r0, lsl #16
+ mov r4, r4, asr #15 @ (r7|10) << 1