+#define PS_STEP_M68K ((488<<16)/20) // ~24
+//#define PS_STEP_S68K 13
+
+#ifdef _ASM_CD_PICO_C
+void SekRunPS(int cyc_m68k, int cyc_s68k);
+#else
+static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
+{
+ int cycn, cycn_s68k, cyc_do;
+ int ex;
+ SekCycleAim+=cyc_m68k;
+ SekCycleAimS68k+=cyc_s68k;
+
+// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
+// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
+
+ /* loop 488 downto 0 in steps of PS_STEP */
+ for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
+ {
+ ex = 0;
+ cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
+ if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
+#if defined(EMU_C68K)
+ PicoCpu.cycles = cyc_do;
+ CycloneRun(&PicoCpu);
+ SekCycleCnt += cyc_do - PicoCpu.cycles;
+#elif defined(EMU_M68K)
+ m68k_set_context(&PicoM68kCPU);
+ SekCycleCnt += (ex = m68k_execute(cyc_do));
+#endif
+ }
+ if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
+#if defined(EMU_C68K)
+ PicoCpuS68k.cycles = cyc_do;
+ CycloneRun(&PicoCpuS68k);
+ SekCycleCntS68k += cyc_do - PicoCpuS68k.cycles;
+#elif defined(EMU_M68K)
+ m68k_set_context(&PicoS68kCPU);
+ SekCycleCntS68k += (ex = m68k_execute(cyc_do));
+#endif
+ }
+ }
+}
+#endif
+
+
+static __inline void check_cd_dma(void)
+{
+ int ddx;
+
+ if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
+
+ ddx = Pico_mcd->s68k_regs[4] & 7;
+ if (ddx < 2) return; // invalid
+ if (ddx < 4) {
+ Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
+ return;
+ }
+ if (ddx == 6) return; // invalid
+
+ Update_CDC_TRansfer(ddx); // now go and do the actual transfer
+}
+
+static __inline void update_chips(void)
+{
+ int counter_timer, int3_set;
+ int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
+
+ // 75Hz CDC update
+ if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
+ Pico_mcd->m.counter75hz -= counter75hz_lim;
+ Check_CD_Command();
+ }
+
+ // update timers
+ counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
+ Pico_mcd->m.timer_stopwatch += counter_timer;
+ if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
+ Pico_mcd->m.timer_int3 -= counter_timer;
+ if (Pico_mcd->m.timer_int3 < 0) {
+ if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
+ dprintf("s68k: timer irq 3");
+ SekInterruptS68k(3);
+ Pico_mcd->m.timer_int3 += int3_set << 16;
+ }
+ // is this really what happens if irq3 is masked out?
+ Pico_mcd->m.timer_int3 &= 0xffffff;
+ }
+ }
+
+ // update gfx chip
+ if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
+ gfx_cd_update();
+
+ // delayed setting of DMNA bit (needed for Silpheed)
+ if (Pico_mcd->m.state_flags & 2) {
+ Pico_mcd->m.state_flags &= ~2;
+ if (!(Pico_mcd->s68k_regs[3] & 4)) {
+ Pico_mcd->s68k_regs[3] |= 2;
+ Pico_mcd->s68k_regs[3] &= ~1;
+#ifdef USE_POLL_DETECT
+ if ((s68k_poll_adclk&0xfe) == 2) {
+ SekSetStopS68k(0); s68k_poll_adclk = 0;
+ }
+#endif
+ }
+ }
+}
+