+static __inline void check_cd_dma(void)
+{
+ int ddx;
+
+ if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
+
+ ddx = Pico_mcd->s68k_regs[4] & 7;
+ if (ddx < 2) return; // invalid
+ if (ddx < 4) {
+ Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
+ return;
+ }
+ if (ddx == 6) return; // invalid
+
+ Update_CDC_TRansfer(ddx); // now go and do the actual transfer
+}
+
+static __inline void update_chips(void)
+{
+ int counter_timer, int3_set;
+ int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
+
+ // 75Hz CDC update
+ if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
+ Pico_mcd->m.counter75hz -= counter75hz_lim;
+ Check_CD_Command();
+ }
+
+ // update timers
+ counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
+ Pico_mcd->m.timer_stopwatch += counter_timer;
+ if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
+ Pico_mcd->m.timer_int3 -= counter_timer;
+ if (Pico_mcd->m.timer_int3 < 0) {
+ if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
+ dprintf("s68k: timer irq 3");
+ SekInterruptS68k(3);
+ Pico_mcd->m.timer_int3 += int3_set << 16;
+ }
+ // is this really what happens if irq3 is masked out?
+ Pico_mcd->m.timer_int3 &= 0xffffff;
+ }
+ }
+
+ // update gfx chip
+ if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
+ gfx_cd_update();
+}
+